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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id j11-20020a5d604b000000b003078681a1e8sm7558457wrt.54.2023.06.22.10.42.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 10:42:21 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 24a081d8-1124-11ee-b237-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1687455742; x=1690047742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jGWd4toS3IkNfM131vkRv5VsP8bjWS9kmyCgBgojdfY=; b=bVD1FT3qa56pFK8e4oCv3OnnvGvHhX7wcHPnoy/WANgs4cGQYAgvVhAnv038Yy3vkT bmKiA9Ei+j6k0pg0h9mYQzYcU6sd57H50q3li3btjapEVMLxhjJ2CQbk0Q2985fk3qi5 Rdf5HPTVNCv+FXscZwhnR7wwM3HLMWvjPF09o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687455742; x=1690047742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jGWd4toS3IkNfM131vkRv5VsP8bjWS9kmyCgBgojdfY=; b=TP19V4xYOIHkX+9CcjbSTyzrLFCGIH60Ab1td4eSzfnMdD1pngmMPKtHXXz0oL+h9P 8WTVtexEO5xx0/K496Flcq4PebGKAt4sLM/SiJvZcq545jwHJBtkRQV4tQ7Jj5Q0QPv6 aYifU5b2hCxr06Ndq+/7teuTsnKmMkezRJ4uQKb3jGdPWmWSEkCHkQHSM/+dCPdvdCtI xTNXm04Hx75mlCY6du6ZyJm/NiFYGQwcHmNaWP41BdeZkF7LBQrrJl8DRZipgFvMB1zd wPT9RkC7AWXv+ZLSaBHv/MItZAdQRhSDu5HARw+dRqyBNFzlToV2nhY+7ydNUEzmqyg6 EJZQ== X-Gm-Message-State: AC+VfDxdsazJ7aZMqLoaQL1Q6CqRgFGlRIg0gVDToKErIcOpK6k48yTc e/UClC6a1LDKS+SExUJZxF5Gw6e9qOLtdmOUou0= X-Google-Smtp-Source: ACHHUZ6mbYJvq7iopIkcaLKIhWxgTvRnUwyGp934mPbC9g9ZSCOJtxiNgWWjEXyKY8TCf+6TqRPcyg== X-Received: by 2002:a1c:6a0e:0:b0:3fa:78d1:572 with SMTP id f14-20020a1c6a0e000000b003fa78d10572mr798252wmc.0.1687455742137; Thu, 22 Jun 2023 10:42:22 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v4 1/4] x86/microcode: Allow reading microcode revision even if it can't be updated Date: Thu, 22 Jun 2023 18:42:16 +0100 Message-Id: <20230622174219.8871-2-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622174219.8871-1-alejandro.vallejo@cloud.com> References: <20230622174219.8871-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 microcode_update_one() currently assumes all microcode handlers are set or none are. That won't be the case in a future patch, as apply_microcode() may not be set while the others are. Hence, this patch allows reading the microcode revision even if updating it is unavailable. Signed-off-by: Alejandro Vallejo Reviewed-by: Jan Beulich --- v4: * Only remove the assumptions on handler contents from microcode_update_one() and leave early_microcode_init() alone (Andrew) --- xen/arch/x86/cpu/microcode/core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index c3fee62906..bec8b55db2 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -750,11 +750,12 @@ __initcall(microcode_init); /* Load a cached update to current cpu */ int microcode_update_one(void) { + if ( ucode_ops.collect_cpu_info ) + alternative_vcall(ucode_ops.collect_cpu_info); + if ( !ucode_ops.apply_microcode ) return -EOPNOTSUPP; - alternative_vcall(ucode_ops.collect_cpu_info); - return microcode_update_cpu(NULL); } From patchwork Thu Jun 22 17:42:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13289507 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 69807EB64D8 for ; Thu, 22 Jun 2023 17:42:51 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.553877.864720 (Exim 4.92) (envelope-from ) id 1qCOKB-0007mW-BH; Thu, 22 Jun 2023 17:42:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 553877.864720; Thu, 22 Jun 2023 17:42:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qCOKB-0007ln-7P; Thu, 22 Jun 2023 17:42:27 +0000 Received: by outflank-mailman (input) for mailman id 553877; Thu, 22 Jun 2023 17:42:25 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qCOK9-00072r-4H for xen-devel@lists.xenproject.org; Thu, 22 Jun 2023 17:42:25 +0000 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [2a00:1450:4864:20::42c]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 250604f9-1124-11ee-8611-37d641c3527e; Thu, 22 Jun 2023 19:42:23 +0200 (CEST) Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-31126037f41so7379176f8f.2 for ; Thu, 22 Jun 2023 10:42:23 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. 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Ignore the microcode loading interface in that case. Signed-off-by: Alejandro Vallejo Reviewed-by: Jan Beulich --- v4: * Stop piggybacking on the existing early exit --- xen/arch/x86/cpu/microcode/core.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index bec8b55db2..e67d143c97 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -867,10 +867,21 @@ int __init early_microcode_init(unsigned long *module_map, return -ENODEV; } - microcode_grab_module(module_map, mbi); - ucode_ops.collect_cpu_info(); + /* + * Some hypervisors deliberately report a microcode revision of -1 to + * mean that they will not accept microcode updates. We take the hint + * and ignore the microcode interface in that case. + */ + if ( this_cpu(cpu_sig).rev == ~0 ) { + printk(XENLOG_WARNING "Microcode loading disabled\n"); + ucode_ops.apply_microcode = NULL; + return -ENODEV; + } + + microcode_grab_module(module_map, mbi); + if ( ucode_mod.mod_end || ucode_blob.size ) rc = early_microcode_update_cpu(); From patchwork Thu Jun 22 17:42:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13289506 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73306EB64DA for ; Thu, 22 Jun 2023 17:42:51 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.553875.864701 (Exim 4.92) (envelope-from ) id 1qCOK9-0007Ia-O7; Thu, 22 Jun 2023 17:42:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 553875.864701; Thu, 22 Jun 2023 17:42:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qCOK9-0007IT-Kx; Thu, 22 Jun 2023 17:42:25 +0000 Received: by outflank-mailman (input) for mailman id 553875; Thu, 22 Jun 2023 17:42:24 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qCOK8-00072l-Ek for xen-devel@lists.xenproject.org; Thu, 22 Jun 2023 17:42:24 +0000 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [2a00:1450:4864:20::429]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 2548ad0f-1124-11ee-b237-6b7b168915f2; Thu, 22 Jun 2023 19:42:23 +0200 (CEST) Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-307d20548adso6348479f8f.0 for ; Thu, 22 Jun 2023 10:42:23 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id j11-20020a5d604b000000b003078681a1e8sm7558457wrt.54.2023.06.22.10.42.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 10:42:22 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2548ad0f-1124-11ee-b237-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1687455743; x=1690047743; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fkkmq00OFGsE60gXctG98JB3mmGeBi1VSc4bej5kz7o=; b=SYIU4owM3SR9BFkuXcklRuHcM6yy0X53esCPYKr5HN2sBBpYcKdbuOcEC4kApl3KIu O1XmCAz9gIs4K1bero5qKLgEaPK3nQeM82lclM1VZU4+Ta0akWAt7uNu9maq5YDJA/4x ij3+GOMrPq5X9qidTCr2idNfQyzBPnluGVCpg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687455743; x=1690047743; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fkkmq00OFGsE60gXctG98JB3mmGeBi1VSc4bej5kz7o=; b=BN8oQraax3OPdpkkMlODV7PFRo0enXamx6FVpqo5koPe0TzK/tnAtoyNZBPAfzRE1N w8OPZm3s2Pc37tqDV2+XX7YtYmB334Ge9omWEXB1bSErpp2evwgtPRonJDWYgNp3VU0M vOKdRV8NzRghS3OLQV64iWZjCKAATQ5uV6QTNmeUJ/66vAbjEH/TG1ZFNJxox+S1uXYw XvQkF50OLyurNWOLnNj7boUHu2eGdnEzjJTqt7k8VQ7FKHuwFgGbHkmR3XwHdFGAp4pO x5/B6toNACCkJN9P0ObLJgXRPBWrgoDj4lhMjK8L5uKZrd0LAA5ayPASQNkPxUho5X9T e7Gw== X-Gm-Message-State: AC+VfDyvMSRl9BzNP7kGX8wk7hsgiTqqoi9aTWyT2bnJdtuB8/9ri5vv jE5Vwoi0CfchhENjVuYe2o3ambk7/pKYdE+KDcQ= X-Google-Smtp-Source: ACHHUZ7QnABFgORslLflbptc8JTw1xN8d3pEu14yhYK6EeBJJoY8AzfePjTB9WDlgfabv/EVrTrmIw== X-Received: by 2002:a5d:570b:0:b0:309:53f3:6e3e with SMTP id a11-20020a5d570b000000b0030953f36e3emr11841512wrv.69.1687455743304; Thu, 22 Jun 2023 10:42:23 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v4 3/4] x86: Read MSR_ARCH_CAPS immediately after early_microcode_init() Date: Thu, 22 Jun 2023 18:42:18 +0100 Message-Id: <20230622174219.8871-4-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622174219.8871-1-alejandro.vallejo@cloud.com> References: <20230622174219.8871-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 Move MSR_ARCH_CAPS read code from tsx_init() to early_cpu_init(). Because microcode updates might make them that MSR to appear/have different values we also must reload it after a microcode update in early_microcode_init(). Signed-off-by: Alejandro Vallejo --- v4: * Read MSR_ARCH_CAPS in early_cpu_init(). Otherwise tsx_init() doesn't have current values in the case where microcode wasn't updated (Jan) --- xen/arch/x86/cpu/common.c | 5 +++++ xen/arch/x86/cpu/microcode/core.c | 13 +++++++++++++ xen/arch/x86/tsx.c | 16 ++++------------ 3 files changed, 22 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index cfcdaace12..2f895e7c7c 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -352,6 +352,11 @@ void __init early_cpu_init(void) &c->x86_capability[FEATURESET_7c0], &c->x86_capability[FEATURESET_7d0]); + if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability)) + rdmsr(MSR_ARCH_CAPABILITIES, + c->x86_capability[FEATURESET_m10Al], + c->x86_capability[FEATURESET_m10Ah]); + if (max_subleaf >= 1) cpuid_count(7, 1, &eax, &ebx, &ecx, &c->x86_capability[FEATURESET_7d1]); diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index e67d143c97..dda6f03f7d 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -885,5 +885,18 @@ int __init early_microcode_init(unsigned long *module_map, if ( ucode_mod.mod_end || ucode_blob.size ) rc = early_microcode_update_cpu(); + /* + * MSR_ARCH_CAPS may have appeared after the microcode update. + * Reload relevant fields in boot_cpu_data if so because they are + * needed in tsx_init(). + */ + if ( boot_cpu_data.cpuid_level >= 7 ) + boot_cpu_data.x86_capability[FEATURESET_7d0] + = cpuid_count_edx(7, 0); + if ( cpu_has_arch_caps ) + rdmsr(MSR_ARCH_CAPABILITIES, + boot_cpu_data.x86_capability[FEATURESET_m10Al], + boot_cpu_data.x86_capability[FEATURESET_m10Ah]); + return rc; } diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c index 80c6f4cedd..50d8059f23 100644 --- a/xen/arch/x86/tsx.c +++ b/xen/arch/x86/tsx.c @@ -39,9 +39,10 @@ void tsx_init(void) static bool __read_mostly once; /* - * This function is first called between microcode being loaded, and CPUID - * being scanned generally. Read into boot_cpu_data.x86_capability[] for - * the cpu_has_* bits we care about using here. + * This function is first called between microcode being loaded, and + * CPUID being scanned generally. early_cpu_init() has already prepared + * the feature bits needed here. And early_microcode_init() has ensured + * they are not stale after the microcode update. */ if ( unlikely(!once) ) { @@ -49,15 +50,6 @@ void tsx_init(void) once = true; - if ( boot_cpu_data.cpuid_level >= 7 ) - boot_cpu_data.x86_capability[FEATURESET_7d0] - = cpuid_count_edx(7, 0); - - if ( cpu_has_arch_caps ) - rdmsr(MSR_ARCH_CAPABILITIES, - boot_cpu_data.x86_capability[FEATURESET_m10Al], - boot_cpu_data.x86_capability[FEATURESET_m10Ah]); - has_rtm_always_abort = cpu_has_rtm_always_abort; if ( cpu_has_tsx_ctrl && cpu_has_srbds_ctrl ) From patchwork Thu Jun 22 17:42:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13289503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6CFE9EB64DC for ; Thu, 22 Jun 2023 17:42:42 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.553878.864726 (Exim 4.92) (envelope-from ) id 1qCOKB-0007qn-MY; Thu, 22 Jun 2023 17:42:27 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 553878.864726; Thu, 22 Jun 2023 17:42:27 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qCOKB-0007pl-HB; Thu, 22 Jun 2023 17:42:27 +0000 Received: by outflank-mailman (input) for mailman id 553878; Thu, 22 Jun 2023 17:42:26 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qCOKA-00072r-79 for xen-devel@lists.xenproject.org; Thu, 22 Jun 2023 17:42:26 +0000 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [2a00:1450:4864:20::32e]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 25b0c98e-1124-11ee-8611-37d641c3527e; Thu, 22 Jun 2023 19:42:24 +0200 (CEST) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f9b4bf99c2so44588075e9.3 for ; Thu, 22 Jun 2023 10:42:24 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id j11-20020a5d604b000000b003078681a1e8sm7558457wrt.54.2023.06.22.10.42.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Jun 2023 10:42:23 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 25b0c98e-1124-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1687455744; x=1690047744; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ijOwIEewQGYf1mJf7n5AJxbCxji2gEFwB1bTgLtLhDs=; b=H8qVwRH7wM1fmkv8p0b9WtBfiik/hUnhLr2SsoqB/HRQ5pNls6lt/SPNFpm+MhO/Uy 0bIhuHiornS4rjSjYZN0loHKafmo9pKjekC8NlHIQ9yrm1Xym8s1VLk/50vqHEUUFxvs BzDRQb3BnHA2DhSeDSO3sybBswVbhyi4GhXz4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687455744; x=1690047744; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ijOwIEewQGYf1mJf7n5AJxbCxji2gEFwB1bTgLtLhDs=; b=EOB2UgAYg8AXZMt7Nf2I1Kuz1H6gxvhfUkjWSKrkM93cl6OafZPDfFX/vnfifEzcl9 I0XcME38tp0R11AcE40Ew3XtITTmGHyKqMBMn80PhNksJvLaJ8+oVpqFZEZxDtbqye/d ag9VxyrFX2c3eXrIQHmkTZgH7cEpYtr+ZAhEUAtRvcWDbDLkFzIBSqKq4YG/htY79K2Q AJi1CLG5MGLWSXUr846RtSrWI3LHmA910oGL+mucYJKYB6XjNlxcAIG4Qb1oGVOzIFLl 6bHaJbrVxYSU2zjYwnj5Nj0jWrBHakCtC5GHPImZW0U1sisdArZdHT9pKdNY9ooIoo0N iRxQ== X-Gm-Message-State: AC+VfDzZReKJvFkfTu6rxTYmJX3mmgajks0ztGYx2p6TRkjkRMMOuKDa 6p7st8xUNq0j/WlzzkWef1t8QL+yQT4c875nsJM= X-Google-Smtp-Source: ACHHUZ6WdrgeXMlAJnhEHMAzVM0SLtM5vyeO+avhXb/bMA2tSdEVMeqZi0Ve6yDVFo0Hd1g/hriqFw== X-Received: by 2002:a1c:f603:0:b0:3f8:f80e:7b45 with SMTP id w3-20020a1cf603000000b003f8f80e7b45mr14405599wmc.7.1687455743932; Thu, 22 Jun 2023 10:42:23 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v4 4/4] x86/microcode: Disable microcode update handler if DIS_MCU_UPDATE is set Date: Thu, 22 Jun 2023 18:42:19 +0100 Message-Id: <20230622174219.8871-5-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622174219.8871-1-alejandro.vallejo@cloud.com> References: <20230622174219.8871-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 If IA32_MSR_MCU_CONTROL exists then it's possible a CPU may be unable to perform microcode updates. This is controlled through the DIS_MCU_LOAD bit and is intended for baremetal clouds where the owner may not trust the tenant to choose the microcode version in use. If we notice that bit being set then simply disable the "apply_microcode" handler so we can't even try to perform update (as it's known to be silently dropped). While at it, remove the Intel family check, as microcode loading is supported on every Intel 64 CPU. Signed-off-by: Alejandro Vallejo --- v4: * Moved the Intel family-check removal here. Previously integrated in other patches * Moved DIS_MCU_LOAD logic into a vendor-specific intel_can_load_microcode() function. --- xen/arch/x86/cpu/microcode/core.c | 10 +++++++--- xen/arch/x86/cpu/microcode/intel.c | 13 +++++++++++++ xen/arch/x86/cpu/microcode/private.h | 7 +++++++ xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/include/asm/msr-index.h | 5 +++++ 5 files changed, 33 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index dda6f03f7d..de0e61d3dd 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -847,17 +847,21 @@ int __init early_microcode_init(unsigned long *module_map, { const struct cpuinfo_x86 *c = &boot_cpu_data; int rc = 0; + bool can_load = false; switch ( c->x86_vendor ) { case X86_VENDOR_AMD: if ( c->x86 >= 0x10 ) + { ucode_ops = amd_ucode_ops; + can_load = true; + } break; case X86_VENDOR_INTEL: - if ( c->x86 >= 6 ) - ucode_ops = intel_ucode_ops; + ucode_ops = intel_ucode_ops; + can_load = intel_can_load_microcode(); break; } @@ -874,7 +878,7 @@ int __init early_microcode_init(unsigned long *module_map, * mean that they will not accept microcode updates. We take the hint * and ignore the microcode interface in that case. */ - if ( this_cpu(cpu_sig).rev == ~0 ) { + if ( this_cpu(cpu_sig).rev == ~0 || !can_load ) { printk(XENLOG_WARNING "Microcode loading disabled\n"); ucode_ops.apply_microcode = NULL; return -ENODEV; diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcode/intel.c index 8d4d6574aa..c51757da90 100644 --- a/xen/arch/x86/cpu/microcode/intel.c +++ b/xen/arch/x86/cpu/microcode/intel.c @@ -385,6 +385,19 @@ static struct microcode_patch *cf_check cpu_request_microcode( return patch; } +bool __init intel_can_load_microcode(void) +{ + uint64_t mcu_ctrl; + + if ( !cpu_has_mcu_ctrl ) + return true; + + rdmsrl(MSR_MCU_CONTROL, mcu_ctrl); + + /* If DIS_MCU_LOAD is set applying microcode updates won't work */ + return !(mcu_ctrl & MCU_CONTROL_DIS_MCU_LOAD); +} + const struct microcode_ops __initconst_cf_clobber intel_ucode_ops = { .cpu_request_microcode = cpu_request_microcode, .collect_cpu_info = collect_cpu_info, diff --git a/xen/arch/x86/cpu/microcode/private.h b/xen/arch/x86/cpu/microcode/private.h index 626aeb4d08..87fcf84373 100644 --- a/xen/arch/x86/cpu/microcode/private.h +++ b/xen/arch/x86/cpu/microcode/private.h @@ -60,6 +60,13 @@ struct microcode_ops { const struct microcode_patch *new, const struct microcode_patch *old); }; +/** + * Checks whether we can perform microcode updates on this Intel system + * + * @return True iff the microcode update facilities are enabled + */ +bool __init intel_can_load_microcode(void); + extern const struct microcode_ops amd_ucode_ops, intel_ucode_ops; #endif /* ASM_X86_MICROCODE_PRIVATE_H */ diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index e2cb8f3cc7..608bc4dce0 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -192,6 +192,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_if_pschange_mc_no boot_cpu_has(X86_FEATURE_IF_PSCHANGE_MC_NO) #define cpu_has_tsx_ctrl boot_cpu_has(X86_FEATURE_TSX_CTRL) #define cpu_has_taa_no boot_cpu_has(X86_FEATURE_TAA_NO) +#define cpu_has_mcu_ctrl boot_cpu_has(X86_FEATURE_MCU_CTRL) #define cpu_has_fb_clear boot_cpu_has(X86_FEATURE_FB_CLEAR) #define cpu_has_rrsba boot_cpu_has(X86_FEATURE_RRSBA) diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 2749e433d2..5c1350b5f9 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -165,6 +165,11 @@ #define PASID_PASID_MASK 0x000fffff #define PASID_VALID (_AC(1, ULL) << 31) +#define MSR_MCU_CONTROL 0x00001406 +#define MCU_CONTROL_LOCK (_AC(1, ULL) << 0) +#define MCU_CONTROL_DIS_MCU_LOAD (_AC(1, ULL) << 1) +#define MCU_CONTROL_EN_SMM_BYPASS (_AC(1, ULL) << 2) + #define MSR_UARCH_MISC_CTRL 0x00001b01 #define UARCH_CTRL_DOITM (_AC(1, ULL) << 0)