From patchwork Fri Jun 23 09:55:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13290229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C093BEB64D7 for ; Fri, 23 Jun 2023 09:56:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=PQhkSWSABCREN12kaIh5RT9kiYWBgQh9hXmOXP5QePw=; b=w20nnT3xgjlZ1J WdaYA3dQX4CpKgQ8Dau0jFe+XRsczzwnp7q/RnCZiHImf5JIjlW2aH2Euo/5zIFoBrUlYR5K1+q6H geExroWHCu5+yOyfVF6Z6ckhoR+QXbyLxb/M/Vgi4gzMbo0VNwxLqtVkllJbiKc1DgHjiIbIpO5cy mZqN48PGgGXrrStl2TVEIjjKsYLzpEzbCvoW9SgxzWgYMejx2vzPzD7397zTcGcALOJUKP6P/Fk8l K2ixVFuZcC8sxp5kLzR0doRrszo98NE+0enfbi++/BNx4mZ9cwt2edEGxNkhM/otCDDPn+tlx1MsF 6HKq945KUzOtwoXeE24A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qCdWG-00357h-0s; Fri, 23 Jun 2023 09:55:56 +0000 Received: from mail-lf1-x12c.google.com ([2a00:1450:4864:20::12c]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qCdWC-00356S-2Y for linux-riscv@lists.infradead.org; Fri, 23 Jun 2023 09:55:54 +0000 Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-4f875b267d9so519769e87.1 for ; Fri, 23 Jun 2023 02:55:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1687514150; x=1690106150; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=wJtAM0L0emx8T5IXtJyi6+wwS3eppT8Ww5R/dqqSfCU=; b=NKkG8bNv3EO4QeYMT85sNX4yymCntNQSlDHlNCBUiXhJCFZLTYnc1fxigDu1UDYqjT x/WHlYdO1RARm72vbFOKJXt7Xi2B+Gc7a/WaQSbrVle9IwixizNMq29S5TYpy7Lsr2La iuQ1s6+4Jt+oah+t9i0eHptytK7zsSCgpuxYNEom/yED+at5UjJcN8Tkw48lkezSp3ZW CgEHz9obTkkSzWUlis3Ov9jN3wq4G5X/i2+Uqp2Q8SdXAU4otfDnNsnspefpXF63Vo3w juyH31zimZv063v6oUxIjqsuPXY+ALHeFtdf+vqPr3TRwAXtLlJc5Cz6sDKOFfu7VbTq FOUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687514150; x=1690106150; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=wJtAM0L0emx8T5IXtJyi6+wwS3eppT8Ww5R/dqqSfCU=; b=GSyb9rDFKpJbITrt5uHqA4iZ/1GepyOOG08JShCPLTlunnbW9rmkdkAjo4ehqkv7sz hR3jNKhrG/lFm2tci/KntGK+EmuoIvfjC4AZFjSPHwZ9lwAdPt0Ub+DNleYsmsekBXyu GIVEqbC3TUoUSUd/uShh42mbZsQ3BwTBCM0Al/59Ubwd0mRz9HzXUse14KbFbd2jgVPy VzZxSd1Q2Xk5eJJybtHPzo12QbQYC/SBxDMjH2lgnAydew+hgCtcrmwU/3f2PPeM8jd5 ZIqP4shZwtAix9OjIz+cgKj1h6U3gLTZIJIO/iDhRpoPBucrx7lEmao+MOm8YI7ka2MS pnpQ== X-Gm-Message-State: AC+VfDx5gmnz2q2lRCtpE0F7Zovj4eXICronWM1W8HxjvjXsHumJZSDi 9yIxgpr377fmq4YL7Yg8TGg9gg== X-Google-Smtp-Source: ACHHUZ56QVDSKsm4uhHAhKIZIWN2wRB+s5t+Y+A8bNdb79k8zsowL0ID1EaqAwo4QKkcWaDAMc8Rsw== X-Received: by 2002:a19:2d01:0:b0:4f8:7568:e94b with SMTP id k1-20020a192d01000000b004f87568e94bmr7651114lfj.56.1687514149706; Fri, 23 Jun 2023 02:55:49 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id g17-20020a7bc4d1000000b003f7f87ba116sm1876221wmk.19.2023.06.23.02.55.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 02:55:49 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Andrew Jones , Conor Dooley , Sunil V L , Song Shuai , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti Subject: [PATCH v3 1/3] Documentation: arm: Add bootargs to the table of added DT parameters Date: Fri, 23 Jun 2023 11:55:45 +0200 Message-Id: <20230623095547.51881-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230623_025553_052894_DF206C37 X-CRM114-Status: GOOD ( 10.64 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The bootargs node is also added by the EFI stub in the function update_fdt(), so add it to the table. Signed-off-by: Alexandre Ghiti Reviewed-by: Atish Patra Reviewed-by: Song Shuai --- Documentation/arm/uefi.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/arm/uefi.rst b/Documentation/arm/uefi.rst index baebe688a006..2b7ad9bd7cd2 100644 --- a/Documentation/arm/uefi.rst +++ b/Documentation/arm/uefi.rst @@ -50,7 +50,7 @@ The stub populates the FDT /chosen node with (and the kernel scans for) the following parameters: ========================== ====== =========================================== -Name Size Description +Name Type Description ========================== ====== =========================================== linux,uefi-system-table 64-bit Physical address of the UEFI System Table. @@ -67,4 +67,6 @@ linux,uefi-mmap-desc-ver 32-bit Version of the mmap descriptor format. kaslr-seed 64-bit Entropy used to randomize the kernel image base address location. + +bootargs String Kernel command line ========================== ====== =========================================== From patchwork Fri Jun 23 09:55:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13290230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E8D54EB64D7 for ; Fri, 23 Jun 2023 09:57:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=oQMgHix3DhutEZw9FMaQAOSSH+UXOnV4sbdUrQ5tEV8=; b=nNFZERpVs46Vbh 4isXu1AN0cwHpW7YzQjViNzxKp3ML2zPAZoQc6yIGrCcGLk1CGJ393T2qYcEWJKkguGfJGOg6LqX4 s4V+x59NpQt/j93U+j+5CGjotF4cxpsPRdtWWBHijE4ISgaL3FmXeVagP9AsYYvDdxfNqvhEysh6x mfXFOJI6OJOvHzEP+kTgFA2E2u7Fe4u1+RGrBp9BNooXoi+qtuOAU6cYTCn9zTE2TfL+4gE/ydl7H Zycs6wcUPefyEdXYQn0L6J2DZuZ/9dbeACFGyoVbdgD8fQvzw45fYN1gh8yKfD/VoeQURJ0tKQTUJ Q2OvTLsYFmjyq72/Utww==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qCdXI-0035Fq-1T; Fri, 23 Jun 2023 09:57:00 +0000 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qCdXF-0035EL-0i for linux-riscv@lists.infradead.org; Fri, 23 Jun 2023 09:56:59 +0000 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-3f9ede60140so5253225e9.0 for ; Fri, 23 Jun 2023 02:56:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1687514211; x=1690106211; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S3+xGQt5ulSXCYIKXq9LTvJxlZMgIZ3ZSbz4eE3t9xo=; b=N8wOG3JOiJNpjM1rGvxuo5jL4YQo9XSD8uCyOVvqtuVYjxY8/SMCRnInVG7I8C0epn 75CrPaMcSsZueTsOOnzFUTOTdshZ0wxg2FpoI6qm2V1SDcjmkksrBFp4bC/JRt+PAV/w 1TxjWhoagLhjZjFkYp/ljzinLWXUGOHdl6ZYhvlv6CUCoggj8WNbv4Ouvchu7+iNkE5C nhpm+qXwbpJitkTo8IHAgjL2OuCSDCgInLOewtDIslU7A8IrTbtzr5IIzUrP4ETP0uNe Q7CbULVP6nfk0X4jS2mIW7mbEp4BtlSGNrEEqg/uWcH+6UdrxZCvFNEnYEXrLIOsXyRf ZodQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687514211; x=1690106211; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S3+xGQt5ulSXCYIKXq9LTvJxlZMgIZ3ZSbz4eE3t9xo=; b=VsMX5ZD8LGQRUsGRiw8TIxodf12U3azaeGklS9ZnAMGYUq/sb1cefTPNvyM3W8qkjD nZKN+wI/Hahml4KqQsGsta0X4qWZEjcxtcQNY00fcaYmhwIkEa6RnNvdgIj8lifNPYvn E9C28Kf6XBvOiwcF4C2AObjDrTmctwk3gFeWGpLB0/2YYninUHwg2CxmjkzTC2Y9jOwr yFI6AHEfQaI/vk0pycHF0lWckMwDOmMxSK9f0D/GYHTr0Jb2oMoR2KLkRLx7f4m5mm3L g65DRu0p2x6DAA+qxyhfRSSt/cikG6eJqE5A1MoB2gWKd8+0X0R/QSn1KTWnA1dSvfYp Sn9Q== X-Gm-Message-State: AC+VfDyySp7nEmmYe675yQ3MNmgMweqPrldiDpVO8jSy1jbmFdzfdYCk oiHSuqyVOYJxqfDMSx1qNIt9SQ== X-Google-Smtp-Source: ACHHUZ4wFYCl45U6+3XGFZ0igi9u0XKB3BK0f3m2ahlhTBqundaqHsmrEPKCi+7GEWhrJm52VecuYw== X-Received: by 2002:a1c:6a0a:0:b0:3f9:2c0:b58 with SMTP id f10-20020a1c6a0a000000b003f902c00b58mr13020846wmc.4.1687514210863; Fri, 23 Jun 2023 02:56:50 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id y12-20020a05600c364c00b003f7f249e7dfsm1911581wmq.4.2023.06.23.02.56.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 02:56:50 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Andrew Jones , Conor Dooley , Sunil V L , Song Shuai , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , Palmer Dabbelt Subject: [PATCH v3 2/3] Documentation: riscv: Add early boot document Date: Fri, 23 Jun 2023 11:55:46 +0200 Message-Id: <20230623095547.51881-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230623095547.51881-1-alexghiti@rivosinc.com> References: <20230623095547.51881-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230623_025657_265302_277B4CCF X-CRM114-Status: GOOD ( 33.24 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This document describes the constraints and requirements of the early boot process in a RISC-V kernel. Signed-off-by: Alexandre Ghiti Reviewed-by: Björn Töpel Reviewed-by: Conor Dooley Reviewed-by: Sunil V L Reviewed-by: Andrew Jones Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Reviewed-by: Atish Patra Reviewed-by: Song Shuai --- Documentation/riscv/boot-image-header.rst | 3 - Documentation/riscv/boot.rst | 170 ++++++++++++++++++++++ Documentation/riscv/index.rst | 1 + 3 files changed, 171 insertions(+), 3 deletions(-) create mode 100644 Documentation/riscv/boot.rst diff --git a/Documentation/riscv/boot-image-header.rst b/Documentation/riscv/boot-image-header.rst index d7752533865f..a4a45310c4c4 100644 --- a/Documentation/riscv/boot-image-header.rst +++ b/Documentation/riscv/boot-image-header.rst @@ -7,9 +7,6 @@ Boot image header in RISC-V Linux This document only describes the boot image header details for RISC-V Linux. -TODO: - Write a complete booting guide. - The following 64-byte header is present in decompressed Linux kernel image:: u32 code0; /* Executable code */ diff --git a/Documentation/riscv/boot.rst b/Documentation/riscv/boot.rst new file mode 100644 index 000000000000..09997bbe1b52 --- /dev/null +++ b/Documentation/riscv/boot.rst @@ -0,0 +1,170 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=============================================== +RISC-V Kernel Boot Requirements and Constraints +=============================================== + +:Author: Alexandre Ghiti +:Date: 23 May 2023 + +This document describes what the RISC-V kernel expects from bootloaders and +firmware, but also the constraints that any developer must have in mind when +touching the early boot process. For the purposes of this document, the +'early boot process' refers to any code that runs before the final virtual +mapping is set up. + +Pre-kernel Requirements and Constraints +======================================= + +The RISC-V kernel expects the following of bootloaders and platform firmware: + +Register state +-------------- + +The RISC-V kernel expects: + + * `$a0` to contain the hartid of the current core. + * `$a1` to contain the address of the devicetree in memory. + +CSR state +--------- + +The RISC-V kernel expects: + + * `$satp = 0`: the MMU, if present, must be disabled. + +Reserved memory for resident firmware +------------------------------------- + +The RISC-V kernel must not map any resident memory, or memory protected with +PMPs, in the direct mapping, so the firmware must correctly mark those regions +as per the devicetree specification and/or the UEFI specification. + +Kernel location +--------------- + +The RISC-V kernel expects to be placed at a PMD boundary (2MB aligned for rv64 +and 4MB aligned for rv32). Note that the EFI stub will physically relocate the +kernel if that's not the case. + +Hardware description +-------------------- + +The firmware can pass either a devicetree or ACPI tables to the RISC-V kernel. + +The devicetree is either passed directly to the kernel from the previous stage +using the `$a1` register, or when booting with UEFI, it can be passed using the +EFI configuration table. + +The ACPI tables are passed to the kernel using the EFI configuration table. In +this case, a tiny devicetree is still created by the EFI stub. Please refer to +"EFI stub and devicetree" section below for details about this devicetree. + +Kernel entrance +--------------- + +On SMP systems, there are 2 methods to enter the kernel: + +- `RISCV_BOOT_SPINWAIT`: the firmware releases all harts in the kernel, one hart + wins a lottery and executes the early boot code while the other harts are + parked waiting for the initialization to finish. This method is mostly used to + support older firmwares without SBI HSM extension and M-mode RISC-V kernel. +- `Ordered booting`: the firmware releases only one hart that will execute the + initialization phase and then will start all other harts using the SBI HSM + extension. The ordered booting method is the preferred booting method for + booting the RISC-V kernel because it can support cpu hotplug and kexec. + +UEFI +---- + +UEFI memory map +~~~~~~~~~~~~~~~ + +When booting with UEFI, the RISC-V kernel will use only the EFI memory map to +populate the system memory. + +The UEFI firmware must parse the subnodes of the `/reserved-memory` devicetree +node and abide by the devicetree specification to convert the attributes of +those subnodes (`no-map` and `reusable`) into their correct EFI equivalent +(refer to section "3.5.4 /reserved-memory and UEFI" of the devicetree +specification v0.4-rc1). + +RISCV_EFI_BOOT_PROTOCOL +~~~~~~~~~~~~~~~~~~~~~~~ + +When booting with UEFI, the EFI stub requires the boot hartid in order to pass +it to the RISC-V kernel in `$a1`. The EFI stub retrieves the boot hartid using +one of the following methods: + +- `RISCV_EFI_BOOT_PROTOCOL` (**preferred**). +- `boot-hartid` devicetree subnode (**deprecated**). + +Any new firmware must implement `RISCV_EFI_BOOT_PROTOCOL` as the devicetree +based approach is deprecated now. + +Early Boot Requirements and Constraints +======================================= + +The RISC-V kernel's early boot process operates under the following constraints: + +EFI stub and devicetree +----------------------- + +When booting with UEFI, the devicetree is supplemented (or created) by the EFI +stub with the same parameters as arm64 which are described at the paragraph +"UEFI kernel support on ARM" in Documentation/arm/uefi.rst. + +Virtual mapping installation +---------------------------- + +The installation of the virtual mapping is done in 2 steps in the RISC-V kernel: + +1. :c:func:`setup_vm` installs a temporary kernel mapping in + :c:var:`early_pg_dir` which allows discovery of the system memory. Only the + kernel text/data are mapped at this point. When establishing this mapping, no + allocation can be done (since the system memory is not known yet), so + :c:var:`early_pg_dir` page table is statically allocated (using only one + table for each level). + +2. :c:func:`setup_vm_final` creates the final kernel mapping in + :c:var:`swapper_pg_dir` and takes advantage of the discovered system memory + to create the linear mapping. When establishing this mapping, the kernel + can allocate memory but cannot access it directly (since the direct mapping + is not present yet), so it uses temporary mappings in the fixmap region to + be able to access the newly allocated page table levels. + +For :c:func:`virt_to_phys` and :c:func:`phys_to_virt` to be able to correctly +convert direct mapping addresses to physical addresses, they need to know the +start of the DRAM. This happens after step 1, right before step 2 installs the +direct mapping (see :c:func:`setup_bootmem` function in arch/riscv/mm/init.c). +Any usage of those macros before the final virtual mapping is installed must +be carefully examined. + +Devicetree mapping via fixmap +----------------------------- + +As the :c:var:`reserved_mem` array is initialized with virtual addresses +established by :c:func:`setup_vm`, and used with the mapping established by +:c:func:`setup_vm_final`, the RISC-V kernel uses the fixmap region to map the +devicetree. This ensures that the devicetree remains accessible by both virtual +mappings. + +Pre-MMU execution +----------------- + +A few pieces of code need to run before even the first virtual mapping is +established. These are the installation of the first virtual mapping itself, +patching of early alternatives and the early parsing of the kernel command line. +That code must be very carefully compiled as: + +- `-fno-pie`: This is needed for relocatable kernels which use `-fPIE`, since + otherwise, any access to a global symbol would go through the GOT which is + only relocated virtually. +- `-mcmodel=medany`: Any access to a global symbol must be PC-relative to avoid + any relocations to happen before the MMU is setup. +- *all* instrumentation must also be disabled (that includes KASAN, ftrace and + others). + +As using a symbol from a different compilation unit requires this unit to be +compiled with those flags, we advise, as much as possible, not to use external +symbols. diff --git a/Documentation/riscv/index.rst b/Documentation/riscv/index.rst index 175a91db0200..1f66062def6d 100644 --- a/Documentation/riscv/index.rst +++ b/Documentation/riscv/index.rst @@ -5,6 +5,7 @@ RISC-V architecture .. toctree:: :maxdepth: 1 + boot boot-image-header vm-layout hwprobe From patchwork Fri Jun 23 09:55:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13290231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87924C001B0 for ; Fri, 23 Jun 2023 09:58:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=W0JY3rH/7vfIEQJvkxNRp1pHZLLmQKNHaIUsGugpmyk=; b=oxQMg43fWdeWsw 45eeSS9UpAD9vyf+DUOVWca2NBleVMbcinP7Uinb3sNfmtQYELnNxoKGYddVw1SIcbGSH7Ne87jaA c1kRdCtqeNPmz7l24yrVjyZG6PdenhHPLrI6iXpNadKbUDY/elLPBcCSTMjdQW/fYVnNjlbTYLyXB 2oz9O2wjvUhvHfUpYsAgX876qVLwClSlF89prl70RsagZ9YIinRAT0wdJ2xbmJUZlzEmK5PHWfPjn Pofs037QF/LJpCwBL08qQUhfgXHC8yIKtlkIgwOrV1mNmBNLyVi0T6ch/sF60oJswKF3jJL3onZRp iAQ4OO2bUbHDcWUZMCHg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qCdYC-0035Mr-1X; Fri, 23 Jun 2023 09:57:56 +0000 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qCdY9-0035MS-1o for linux-riscv@lists.infradead.org; Fri, 23 Jun 2023 09:57:54 +0000 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-3f9bdb01ec0so5824085e9.2 for ; Fri, 23 Jun 2023 02:57:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1687514272; x=1690106272; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/pQzPxsmpV8ILmUDokZDt4x2j1OZGQdakvLzX04+Ejg=; b=DRlPNLsK/mZ3irMEYdZmnmDdlPds7DvI5au6/NXLEmObZ0q2j+riTTvnF4pnaba5Eb DH2TXjFL5OFBSrzNE1j4a5aGqGz48UHjYrVhZd3wVtPnW2C22JGEuGjsrq+JpfMRJV2k MkWPC6wPxJC27j2xRo0NYQY4kjlkcSDEwr9JRvSSwtmlCEF3IowczoAHbtWW345VGYQr DLQu/ZwtBg6Q81ga1VMS7w7OdSttnxx7sF4T278R3LjJ8THYdUsFWjekXwF9VxCxViVY kF8/QayqIlynx9XhIUmUIXrLU/LQ5y0rz+dMU2qOPVvjSn5y1zTvusx3LzoxEB2uMWUr 2K6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687514272; x=1690106272; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/pQzPxsmpV8ILmUDokZDt4x2j1OZGQdakvLzX04+Ejg=; b=Ak5C74tBoK8u+Z9zOsWNvVd3r/fodiX9H/Oo7gOcywwRBXgR/mv8FH8zrK580TSqMm 6OV4Y/QW9YbTmLnfn/SMs4uBFe7mqMi9rlLexHWE5I70OtOOHN9qNtaLpMKQXBvWkeDk +pCE9wdZL/AF3xDjFAMPTLoMJ7FdoFk1fR7m8lbE31VU6Rx4mt3Jz4ZpBDxwzE/UbHOT is27ljkON1dr3FVguDzJ9CuYyzEY5wg2yb0jQd8DAWPqEr2I1eqBVgmaWX2LqZfJflp+ Lb72qYIvQy2nJB70exAXmDzd4O0R7TGPio89liL+9SuIBeo/jCRdbYpCEq3YJEg+ivNg bRfQ== X-Gm-Message-State: AC+VfDwB+97tfgB/TvrKC+xE1Z4/g1xLnaYA/+92woUOa8OkndiR31TZ 2Nr5u6ByJAEvHEKa4GNTdEmJEQ== X-Google-Smtp-Source: ACHHUZ7JjYmbOrvMcpUGZTC3uEGAoLXqDRseSay3/vHcvG0f5A9N3KF1iNgjt3GTjbTfRCaqYSCqCQ== X-Received: by 2002:a05:600c:230b:b0:3f1:6fb3:ffcc with SMTP id 11-20020a05600c230b00b003f16fb3ffccmr17377352wmo.22.1687514272211; Fri, 23 Jun 2023 02:57:52 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id s9-20020a7bc389000000b003fa745f3264sm1824671wmj.43.2023.06.23.02.57.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 02:57:52 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Andrew Jones , Conor Dooley , Sunil V L , Song Shuai , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , Atish Patra , Palmer Dabbelt Subject: [PATCH v3 3/3] Documentation: riscv: Update boot image header since EFI stub is supported Date: Fri, 23 Jun 2023 11:55:47 +0200 Message-Id: <20230623095547.51881-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230623095547.51881-1-alexghiti@rivosinc.com> References: <20230623095547.51881-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230623_025753_602780_2C5FCCEE X-CRM114-Status: GOOD ( 14.03 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The EFI stub is supported on RISC-V so update the documentation that explains how the boot image header was reused to support it. Signed-off-by: Alexandre Ghiti Reviewed-by: Atish Patra Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- Documentation/riscv/boot-image-header.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/riscv/boot-image-header.rst b/Documentation/riscv/boot-image-header.rst index a4a45310c4c4..df2ffc173e80 100644 --- a/Documentation/riscv/boot-image-header.rst +++ b/Documentation/riscv/boot-image-header.rst @@ -28,11 +28,11 @@ header in future. Notes ===== -- This header can also be reused to support EFI stub for RISC-V in future. EFI - specification needs PE/COFF image header in the beginning of the kernel image - in order to load it as an EFI application. In order to support EFI stub, - code0 should be replaced with "MZ" magic string and res3(at offset 0x3c) should - point to the rest of the PE/COFF header. +- This header is also reused to support EFI stub for RISC-V. EFI specification + needs PE/COFF image header in the beginning of the kernel image in order to + load it as an EFI application. In order to support EFI stub, code0 is replaced + with "MZ" magic string and res3(at offset 0x3c) points to the rest of the + PE/COFF header. - version field indicate header version number