From patchwork Fri Jun 23 14:09:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Olivier Moysan X-Patchwork-Id: 13290665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 571E5EB64D7 for ; Fri, 23 Jun 2023 14:13:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zfPdXEJMGFpN9BO7q8ukSJt51iBjGcj6YqWc0oaYfUI=; b=zfi7qRN9V7QYmN q25xAKC2zj1EMhsNb+us/fsQ238/LJW/UCqzqebiOBvwtMZL/hJtcsVSAFuVbL1VPB+thnNSVIsX1 75djiTVoBmCSBptasdyUvkJKfNZHTSKWGhJwDaC9HAr7k9LMUj4PQ/qsokZ8Un1n3PhddFh2egU1R Dz6YEima6OB0YIgxdaA/sDFmkcc07lwIgwRm1JIEmdjLn0s26QcmtyOerhcKq1Wv367Qhez8E2OIh 4/xKPorGPBwqHLvcVbENO3NTHWq1BR4XMG2x4lMXtg4UCYs7sriBW+p3KsE9Iwwqo4SW+rXLedYrq Q4mH2Sx85iayte2YDmVg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qChWk-003ixy-03; Fri, 23 Jun 2023 14:12:42 +0000 Received: from mx07-00178001.pphosted.com ([185.132.182.106]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qChWg-003iwO-2i for linux-arm-kernel@lists.infradead.org; Fri, 23 Jun 2023 14:12:40 +0000 Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35NCnMJi001404; Fri, 23 Jun 2023 16:12:29 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=4w+XTZcklvwz2Fhwwbd75o/e+Qy9XSNVKTR2QtoHRfQ=; b=I1FOOH3qMs0c6+tO8nXhqgi0NqOFcX19AArVGvRgovBerWSnSUd95b2IbecB6aGO7Qxh VlfcXiAylMXRCowmmZXqUeQYF0D55GJnK/qVDxT/DfVkzU/bqVsZ7fpIuBrFuYj+0V9P sIIMNCKct8UKFeKT76VS1oK5argxk4BGb5ZHXGfioYfMpsaNAILi47lK1Iv49dDuLj+T 9QmCO/yFBX8W0APzO6qccg7i0G/OHUrTdPfFsLLXVxSECAboubdYBBCG7NU9pqstEtwb I4V8j+n2h7k4JIuvir6AZj+CTdCda80Asdsb8ei8/g8fg8q+e5Np0TlRSKnXCNt5QlKc HA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3rd1t6vb2t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Jun 2023 16:12:29 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 90F80100079; Fri, 23 Jun 2023 16:12:28 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 88E9E22D16A; Fri, 23 Jun 2023 16:12:28 +0200 (CEST) Received: from localhost (10.252.5.198) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 16:12:28 +0200 From: Olivier Moysan To: Jonathan Cameron , Lars-Peter Clausen , Maxime Coquelin , Alexandre Torgue CC: Olivier Moysan , , , , Subject: [RFC PATCH 3/7] iio: adc: stm32-dfsdm: manage dfsdm as a channel provider Date: Fri, 23 Jun 2023 16:09:39 +0200 Message-ID: <20230623140944.2613002-4-olivier.moysan@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623140944.2613002-1-olivier.moysan@foss.st.com> References: <20230623140944.2613002-1-olivier.moysan@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.5.198] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-23_08,2023-06-22_02,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230623_071239_173231_B76596AC X-CRM114-Status: GOOD ( 16.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The STM32 is currently implemented as a channels consumer of the sigma delta modulator. Change the topology to expose a single IIO device for DFSDM and remove the IIO device associated to the SD modulator. Manage the DFSDM as a channel provider to allow this change. Signed-off-by: Olivier Moysan --- drivers/iio/adc/stm32-dfsdm-adc.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/drivers/iio/adc/stm32-dfsdm-adc.c b/drivers/iio/adc/stm32-dfsdm-adc.c index a428bdb567d5..20756d496c52 100644 --- a/drivers/iio/adc/stm32-dfsdm-adc.c +++ b/drivers/iio/adc/stm32-dfsdm-adc.c @@ -76,7 +76,6 @@ struct stm32_dfsdm_adc { /* ADC specific */ unsigned int oversamp; - struct iio_hw_consumer *hwc; struct completion completion; u32 *buffer; @@ -1006,12 +1005,6 @@ static int stm32_dfsdm_postenable(struct iio_dev *indio_dev) /* Reset adc buffer index */ adc->bufi = 0; - if (adc->hwc) { - ret = iio_hw_consumer_enable(adc->hwc); - if (ret < 0) - return ret; - } - ret = stm32_dfsdm_start_dfsdm(adc->dfsdm); if (ret < 0) goto err_stop_hwc; @@ -1035,8 +1028,6 @@ static int stm32_dfsdm_postenable(struct iio_dev *indio_dev) stop_dfsdm: stm32_dfsdm_stop_dfsdm(adc->dfsdm); err_stop_hwc: - if (adc->hwc) - iio_hw_consumer_disable(adc->hwc); return ret; } @@ -1051,9 +1042,6 @@ static int stm32_dfsdm_predisable(struct iio_dev *indio_dev) stm32_dfsdm_stop_dfsdm(adc->dfsdm); - if (adc->hwc) - iio_hw_consumer_disable(adc->hwc); - return 0; } @@ -1230,7 +1218,6 @@ static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev, ret = iio_device_claim_direct_mode(indio_dev); if (ret) return ret; - ret = iio_hw_consumer_enable(adc->hwc); if (ret < 0) { dev_err(&indio_dev->dev, "%s: IIO enable failed (channel %d)\n", @@ -1239,7 +1226,6 @@ static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev, return ret; } ret = stm32_dfsdm_single_conv(indio_dev, chan, val); - iio_hw_consumer_disable(adc->hwc); if (ret < 0) { dev_err(&indio_dev->dev, "%s: Conversion failed (channel %d)\n", @@ -1449,11 +1435,6 @@ static int stm32_dfsdm_adc_init(struct device *dev, struct iio_dev *indio_dev) return num_ch < 0 ? num_ch : -EINVAL; } - /* Bind to SD modulator IIO device */ - adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev); - if (IS_ERR(adc->hwc)) - return -EPROBE_DEFER; - ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch), GFP_KERNEL); if (!ch) From patchwork Fri Jun 23 14:09:40 2023 Content-Type: text/plain; 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Fri, 23 Jun 2023 16:12:29 +0200 (CEST) Received: from localhost (10.252.5.198) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 16:12:29 +0200 From: Olivier Moysan To: Jonathan Cameron , Lars-Peter Clausen , Maxime Coquelin , Alexandre Torgue CC: Olivier Moysan , , , , Subject: [RFC PATCH 4/7] iio: adc: stm32-dfsdm: adopt generic channel bindings Date: Fri, 23 Jun 2023 16:09:40 +0200 Message-ID: <20230623140944.2613002-5-olivier.moysan@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623140944.2613002-1-olivier.moysan@foss.st.com> References: <20230623140944.2613002-1-olivier.moysan@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.5.198] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-23_08,2023-06-22_02,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230623_071239_173439_369BEC5B X-CRM114-Status: GOOD ( 21.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adopt the generic channel bindings to ease the configuration of the DFSDM channels as consumers of the SD modulator backend device. Also adopt unified device property API in the same patch for this RFC. Signed-off-by: Olivier Moysan --- drivers/iio/adc/stm32-dfsdm-adc.c | 93 ++++++++++++++++--------------- 1 file changed, 49 insertions(+), 44 deletions(-) diff --git a/drivers/iio/adc/stm32-dfsdm-adc.c b/drivers/iio/adc/stm32-dfsdm-adc.c index 20756d496c52..2e76497cee51 100644 --- a/drivers/iio/adc/stm32-dfsdm-adc.c +++ b/drivers/iio/adc/stm32-dfsdm-adc.c @@ -595,45 +595,35 @@ static int stm32_dfsdm_filter_configure(struct iio_dev *indio_dev, static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm, struct iio_dev *indio_dev, + struct fwnode_handle *node, struct iio_chan_spec *ch) { struct stm32_dfsdm_channel *df_ch; const char *of_str; - int chan_idx = ch->scan_index; int ret, val; - ret = of_property_read_u32_index(indio_dev->dev.of_node, - "st,adc-channels", chan_idx, - &ch->channel); + ret = fwnode_property_read_u32(node, "reg", &ch->channel); if (ret < 0) { - dev_err(&indio_dev->dev, - " Error parsing 'st,adc-channels' for idx %d\n", - chan_idx); + dev_err(&indio_dev->dev, "Missing channel index %d\n", ret); return ret; } if (ch->channel >= dfsdm->num_chs) { - dev_err(&indio_dev->dev, - " Error bad channel number %d (max = %d)\n", + dev_err(&indio_dev->dev, " Error bad channel number %d (max = %d)\n", ch->channel, dfsdm->num_chs); return -EINVAL; } - ret = of_property_read_string_index(indio_dev->dev.of_node, - "st,adc-channel-names", chan_idx, - &ch->datasheet_name); + ret = fwnode_property_read_string(node, "label", &ch->datasheet_name); if (ret < 0) { dev_err(&indio_dev->dev, - " Error parsing 'st,adc-channel-names' for idx %d\n", - chan_idx); + " Error parsing 'label' for idx %d\n", ch->channel); return ret; } df_ch = &dfsdm->ch_list[ch->channel]; df_ch->id = ch->channel; - ret = of_property_read_string_index(indio_dev->dev.of_node, - "st,adc-channel-types", chan_idx, - &of_str); + ret = fwnode_property_read_string(node, "st,adc-channel-types", &of_str); if (!ret) { val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type); if (val < 0) @@ -643,9 +633,7 @@ static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm, } df_ch->type = val; - ret = of_property_read_string_index(indio_dev->dev.of_node, - "st,adc-channel-clk-src", chan_idx, - &of_str); + ret = fwnode_property_read_string(node, "st,adc-channel-clk-src", &of_str); if (!ret) { val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src); if (val < 0) @@ -655,10 +643,8 @@ static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm, } df_ch->src = val; - ret = of_property_read_u32_index(indio_dev->dev.of_node, - "st,adc-alt-channel", chan_idx, - &df_ch->alt_si); - if (ret < 0) + ret = fwnode_property_read_u32(node, "st,adc-alt-channel", &df_ch->alt_si); + if (ret != -EINVAL) df_ch->alt_si = 0; return 0; @@ -1353,14 +1339,17 @@ static int stm32_dfsdm_dma_request(struct device *dev, } static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev, + struct fwnode_handle *child, struct iio_chan_spec *ch) { struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); int ret; - ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch); - if (ret < 0) + ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, child, ch); + if (ret < 0) { + dev_err(&indio_dev->dev, "Failed to parse channel %d\n", ch->scan_index); return ret; + } ch->type = IIO_VOLTAGE; ch->indexed = 1; @@ -1386,6 +1375,31 @@ static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev, &adc->dfsdm->ch_list[ch->channel]); } +static int stm32_dfsdm_generic_chan_init(struct iio_dev *indio_dev, struct stm32_dfsdm_adc *adc, + struct iio_chan_spec *channels) +{ + struct fwnode_handle *child; + int chan_idx = 0, ret; + + device_for_each_child_node(&indio_dev->dev, child) { + channels[chan_idx].scan_index = chan_idx; + ret = stm32_dfsdm_adc_chan_init_one(indio_dev, child, &channels[chan_idx]); + if (ret < 0) { + dev_err(&indio_dev->dev, "Channels init failed\n"); + goto err; + } + + chan_idx++; + } + + return chan_idx; + +err: + fwnode_handle_put(child); + + return ret; +} + static int stm32_dfsdm_audio_init(struct device *dev, struct iio_dev *indio_dev) { struct iio_chan_spec *ch; @@ -1399,7 +1413,7 @@ static int stm32_dfsdm_audio_init(struct device *dev, struct iio_dev *indio_dev) ch->scan_index = 0; - ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch); + stm32_dfsdm_generic_chan_init(indio_dev, adc, ch); if (ret < 0) { dev_err(&indio_dev->dev, "Channels init failed\n"); return ret; @@ -1421,33 +1435,24 @@ static int stm32_dfsdm_adc_init(struct device *dev, struct iio_dev *indio_dev) struct iio_chan_spec *ch; struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); int num_ch; - int ret, chan_idx; + int ret; adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING; ret = stm32_dfsdm_compute_all_osrs(indio_dev, adc->oversamp); if (ret < 0) return ret; - num_ch = of_property_count_u32_elems(indio_dev->dev.of_node, - "st,adc-channels"); - if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) { - dev_err(&indio_dev->dev, "Bad st,adc-channels\n"); - return num_ch < 0 ? num_ch : -EINVAL; - } + num_ch = device_get_child_node_count(&indio_dev->dev); + if (!num_ch) + return -EINVAL; - ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch), - GFP_KERNEL); + ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch), GFP_KERNEL); if (!ch) return -ENOMEM; - for (chan_idx = 0; chan_idx < num_ch; chan_idx++) { - ch[chan_idx].scan_index = chan_idx; - ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]); - if (ret < 0) { - dev_err(&indio_dev->dev, "Channels init failed\n"); - return ret; - } - } + stm32_dfsdm_generic_chan_init(indio_dev, adc, ch); + if (ret < 0) + return ret; indio_dev->num_channels = num_ch; indio_dev->channels = ch; From patchwork Fri Jun 23 14:09:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Olivier Moysan X-Patchwork-Id: 13290667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F9B4EB64DD for ; Fri, 23 Jun 2023 14:14:05 +0000 (UTC) DKIM-Signature: v=1; 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Fri, 23 Jun 2023 16:13:31 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 425DB100075; Fri, 23 Jun 2023 16:13:31 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 349E122D170; Fri, 23 Jun 2023 16:13:31 +0200 (CEST) Received: from localhost (10.252.5.198) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 16:13:30 +0200 From: Olivier Moysan To: Jonathan Cameron , Lars-Peter Clausen , Maxime Coquelin , Alexandre Torgue , Liam Girdwood , Mark Brown CC: Olivier Moysan , , , , Subject: [RFC PATCH 6/7] iio: adc: stm32-dfsdm: add scaling support to dfsdm Date: Fri, 23 Jun 2023 16:09:42 +0200 Message-ID: <20230623140944.2613002-7-olivier.moysan@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623140944.2613002-1-olivier.moysan@foss.st.com> References: <20230623140944.2613002-1-olivier.moysan@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.5.198] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-23_08,2023-06-22_02,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230623_071337_690874_12F9CB1D X-CRM114-Status: GOOD ( 26.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add scaling support to STM32 DFSDM. Signed-off-by: Olivier Moysan --- drivers/iio/adc/sd_adc_modulator.c | 31 ++++++++++++++- drivers/iio/adc/stm32-dfsdm-adc.c | 64 ++++++++++++++++++++++++++++-- 2 files changed, 91 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/sd_adc_modulator.c b/drivers/iio/adc/sd_adc_modulator.c index 61246a52dc79..749c46da9c72 100644 --- a/drivers/iio/adc/sd_adc_modulator.c +++ b/drivers/iio/adc/sd_adc_modulator.c @@ -12,15 +12,23 @@ #include #include #include +#include struct iio_sd_mod_priv { + struct regulator *vref; + int vref_mv; }; static int sd_mod_enable(struct iio_backend *backend) { struct iio_sd_mod_priv *priv = backend->priv; + int ret; /* PM resume */ + ret = regulator_enable(priv->vref); + + ret = regulator_get_voltage(priv->vref); + priv->vref_mv = ret / 1000; return 0; }; @@ -30,6 +38,7 @@ static int sd_mod_disable(struct iio_backend *backend) struct iio_sd_mod_priv *priv = backend->priv; /* PM suspend */ + regulator_disable(priv->vref); return 0; }; @@ -39,7 +48,15 @@ static int sd_mod_read(struct iio_backend *backend, int *val, int *val2, long ma struct iio_sd_mod_priv *priv = backend->priv; switch (mask) { - /* Process channel info */ + case IIO_CHAN_INFO_SCALE: + *val = priv->vref_mv; + *val2 = 0; + return IIO_VAL_INT; + + case IIO_CHAN_INFO_OFFSET: + *val = 0; + *val2 = 0; + return IIO_VAL_INT; } return -EINVAL; @@ -54,12 +71,24 @@ static const struct iio_backend_ops sd_mod_ops = { static int iio_sd_mod_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct regulator *vref; struct iio_backend *backend; struct iio_sd_mod_priv *priv; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + vref = devm_regulator_get_optional(dev, "vref"); + if (IS_ERR(vref)) { + ret = PTR_ERR(vref); + if (ret != -ENODEV) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "vref get failed, %d\n", ret); + return ret; + } + } + priv->vref = vref; + backend = iio_backend_alloc(dev); backend->priv = priv; diff --git a/drivers/iio/adc/stm32-dfsdm-adc.c b/drivers/iio/adc/stm32-dfsdm-adc.c index 2e76497cee51..468d72ab079d 100644 --- a/drivers/iio/adc/stm32-dfsdm-adc.c +++ b/drivers/iio/adc/stm32-dfsdm-adc.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -76,6 +77,7 @@ struct stm32_dfsdm_adc { /* ADC specific */ unsigned int oversamp; + struct iio_backend **backend; struct completion completion; u32 *buffer; @@ -599,6 +601,8 @@ static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm, struct iio_chan_spec *ch) { struct stm32_dfsdm_channel *df_ch; + struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); + struct iio_backend *backend; const char *of_str; int ret, val; @@ -647,6 +651,9 @@ static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm, if (ret != -EINVAL) df_ch->alt_si = 0; + backend = iio_backend_get(node->dev); + adc->backend[df_ch->id] = backend; + return 0; } @@ -1090,7 +1097,7 @@ static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev, { struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); long timeout; - int ret; + int ret, idx = chan->scan_index; reinit_completion(&adc->completion); @@ -1100,6 +1107,8 @@ static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev, if (ret < 0) return ret; + adc->backend[idx]->ops->enable(adc->backend[idx]); + ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id), DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1)); if (ret < 0) @@ -1133,6 +1142,8 @@ static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev, stm32_dfsdm_process_data(adc, res); stop_dfsdm: + adc->backend[idx]->ops->disable(adc->backend[idx]); + stm32_dfsdm_stop_dfsdm(adc->dfsdm); return ret; @@ -1197,7 +1208,14 @@ static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev, int *val2, long mask) { struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); - int ret; + + struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id]; + struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast]; + u32 max = flo->max << (flo->lshift - chan->scan_type.shift); + int ret, idx = chan->scan_index; + + if (flo->lshift < chan->scan_type.shift) + max = flo->max >> (chan->scan_type.shift - flo->lshift); switch (mask) { case IIO_CHAN_INFO_RAW: @@ -1231,6 +1249,41 @@ static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev, *val = adc->sample_freq; return IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + /* + * Scale is expressed in mV. + * When fast mode is disabled, actual resolution may be lower + * than 2^n, where n=realbits-1. + * This leads to underestimating input voltage. To + * compensate this deviation, the voltage reference can be + * corrected with a factor = realbits resolution / actual max + */ + adc->backend[idx]->ops->read_raw(adc->backend[idx], val, val2, mask); + + *val = div_u64((u64)*val * (u64)BIT(DFSDM_DATA_RES - 1), max); + *val2 = chan->scan_type.realbits; + if (chan->differential) + *val *= 2; + return IIO_VAL_FRACTIONAL_LOG2; + + case IIO_CHAN_INFO_OFFSET: + /* + * DFSDM output data are in the range [-2^n,2^n-1], + * with n=realbits-1. + * - Differential modulator: + * Offset correspond to SD modulator offset. + * - Single ended modulator: + * Input is in [0V,Vref] range, where 0V corresponds to -2^n. + * Add 2^n to offset. (i.e. middle of input range) + * offset = offset(sd) * vref / res(sd) * max / vref. + */ + adc->backend[idx]->ops->read_raw(adc->backend[idx], val, val2, mask); + + *val = div_u64((u64)max * *val, BIT(*val2 - 1)); + if (chan->differential) + *val += max; + return IIO_VAL_INT; } return -EINVAL; @@ -1358,7 +1411,10 @@ static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev, * IIO_CHAN_INFO_RAW: used to compute regular conversion * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling */ - ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); + ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OFFSET); + ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | BIT(IIO_CHAN_INFO_SAMP_FREQ); @@ -1454,6 +1510,8 @@ static int stm32_dfsdm_adc_init(struct device *dev, struct iio_dev *indio_dev) if (ret < 0) return ret; + adc->backend = devm_kzalloc(&indio_dev->dev, sizeof(*adc->backend) * num_ch, GFP_KERNEL); + indio_dev->num_channels = num_ch; indio_dev->channels = ch; From patchwork Fri Jun 23 14:09:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Olivier Moysan X-Patchwork-Id: 13290668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05B46EB64DD for ; Fri, 23 Jun 2023 14:14:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 23 Jun 2023 16:13:32 +0200 (CEST) Received: from localhost (10.252.5.198) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 16:13:31 +0200 From: Olivier Moysan To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: Olivier Moysan , , , , Subject: [RFC PATCH 7/7] ARM: dts: stm32: add dfsdm iio suppport Date: Fri, 23 Jun 2023 16:09:43 +0200 Message-ID: <20230623140944.2613002-8-olivier.moysan@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623140944.2613002-1-olivier.moysan@foss.st.com> References: <20230623140944.2613002-1-olivier.moysan@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.5.198] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-23_08,2023-06-22_02,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230623_071338_950631_8EF7E19A X-CRM114-Status: GOOD ( 14.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This DT is an example of backend iio device use for STM32 DFSDM. DFSDM filter0 has a single input channel, while filter1 is configured for scan mode with two input channels. Signed-off-by: Olivier Moysan --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 62 +++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index ba8e9d9a42fa..ebd67a219df2 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -73,6 +73,24 @@ panel_backlight: panel-backlight { default-on; status = "okay"; }; + + sd_adc0: simple-sd-adc0 { + compatible = "sd-modulator"; + io-backend-cells = <0>; + vref-supply = <&v3v3>; + }; + + sd_adc1: simple-sd-adc1 { + compatible = "sd-modulator"; + io-backend-cells = <0>; + vref-supply = <&v3v3>; + }; + + sd_adc2: simple-sd-adc2 { + compatible = "sd-modulator"; + io-backend-cells = <0>; + vref-supply = <&v3v3>; + }; }; &cec { @@ -99,6 +117,50 @@ dcmi_0: endpoint { }; }; +&dfsdm { + spi-max-frequency = <2048000>; + + clocks = <&rcc DFSDM_K>, <&rcc ADFSDM_K>; + clock-names = "dfsdm", "audio"; + status = "disabled"; + + dfsdm0: filter@0 { + compatible = "st,stm32-dfsdm-adc"; + st,filter-order = <3>; + status = "okay"; + + channel@1 { + reg = <1>; + label = "in1"; + st,adc-channel-types = "SPI_R"; + st,adc-channel-clk-src = "CLKOUT"; + io-backend = <&sd_adc0>; + }; + }; + + dfsdm1: filter@1 { + compatible = "st,stm32-dfsdm-adc"; + st,filter-order = <3>; + status = "okay"; + + channel@2 { + reg = <2>; + label = "in2"; + st,adc-channel-types = "SPI_R"; + st,adc-channel-clk-src = "CLKOUT"; + io-backend = <&sd_adc1>; + }; + + channel@3 { + reg = <3>; + label = "in3"; + st,adc-channel-types = "SPI_F"; + st,adc-channel-clk-src = "CLKOUT"; + io-backend = <&sd_adc2>; + }; + }; +}; + &dsi { phy-dsi-supply = <®18>; status = "okay";