From patchwork Fri Jun 23 14:40:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13290747 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD892EB64DD for ; Fri, 23 Jun 2023 14:41:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231938AbjFWOlU (ORCPT ); Fri, 23 Jun 2023 10:41:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231665AbjFWOlT (ORCPT ); Fri, 23 Jun 2023 10:41:19 -0400 Received: from mail-qk1-x730.google.com (mail-qk1-x730.google.com [IPv6:2607:f8b0:4864:20::730]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFD982688 for ; Fri, 23 Jun 2023 07:41:09 -0700 (PDT) Received: by mail-qk1-x730.google.com with SMTP id af79cd13be357-7624e8ceef7so60290285a.2 for ; Fri, 23 Jun 2023 07:41:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1687531268; x=1690123268; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=H/MnZlXk/4MfIX0Zs4hYPeMhGkoL8SprRM9WTvKMY24=; b=BttqBtgeyKQYKgfwjS8Ne9zM/0TI10iQGX8kNemb/icXbKrzzWhR01zccE21L8dlOe WFCVCCbByiInJQo9n0kcr59w89i5M9TTwMR6CIN9oCyHnTBVEsQeY+SSIH6OeAy9youA 4rdYL6XkNIghJTPMYIyWYZBIPUUn55a8SFKV8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687531268; x=1690123268; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=H/MnZlXk/4MfIX0Zs4hYPeMhGkoL8SprRM9WTvKMY24=; b=VI2yAIHadbC15O8bMfxwtbwhcuiKYEVuNJ2liD156PWTz/m6TPjKs0xzgGoVCDjAEe ebMdu1RmrC3TpMa8pRtVGgL1Wys6sLvgbm/8HRFhv/YTR380nWhRzDf4UT4jrRaKwHjr mWS5Uqtxpg2MO71lgsMVH79zQPj/qW/MnRafk1ewM+6fW6S3hYWh9l+69RkLCnhGC+AU Ye77Vj6AkXKYE92p77c1dtTaw00Vjokmau+I/W3p1P1BA1ZVem1HGr2gBbhxeBFcGRIU RH0a08/atzxOfvxrEoFtb3C//x8VYECOH3rT/q1EXxmuDxL8MjIdJ8zYL98WHgNGL9Xo b8wQ== X-Gm-Message-State: AC+VfDyV0L88ZB9NlEMHMXldFcrZ1H1nCWJPxI/qxIClea3H6mZ0lCTE 86q+0HCNk5VnmqgrvT0ZO7GmXC0gxhln7RApSsuodocIfoFCOs6QQ3WZIXOwY2Uy0Jsr1t3c8Ty GNdCDLu5+63NyWv9XOQTOlSaF5Lt7oW8x/FCFzjO1PQq7dIyqD60gZ81h0OWxFtYFEESBPjYPbn op4v6cqZ/A4Q== X-Google-Smtp-Source: ACHHUZ6VEUGWHyC6gT/qBlxdtFs8HESOkMiVWwwv0lzZBtEqaLYNovEbLqSls92mOSWoka1L+bDJrg== X-Received: by 2002:a05:620a:424d:b0:75b:23a1:3606 with SMTP id w13-20020a05620a424d00b0075b23a13606mr15726420qko.23.1687531268377; Fri, 23 Jun 2023 07:41:08 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id i18-20020a05620a145200b007625382f4ccsm4564613qkl.69.2023.06.23.07.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 07:41:07 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Jim Quinlan , Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE), linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property Date: Fri, 23 Jun 2023 10:40:54 -0400 Message-Id: <20230623144100.34196-2-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230623144100.34196-1-james.quinlan@broadcom.com> References: <20230623144100.34196-1-james.quinlan@broadcom.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This commit adds the boolean "brcm,enable-l1ss" property: The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs -- requires the driver probe() to deliberately place the HW one of three CLKREQ# modes: (a) CLKREQ# driven by the RC unconditionally (b) CLKREQ# driven by the EP for ASPM L0s, L1 (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS). The HW+driver can tell the difference between downstream devices that need (a) and (b), but does not know when to configure (c). All devices should work fine when the driver chooses (a) or (b), but (c) may be desired to realize the extra power savings that L1SS offers. So we introduce the boolean "brcm,enable-l1ss" property to inform the driver that (c) is desired. Setting this property only makes sense when the downstream device is L1SS-capable and the OS is configured to activate this mode (e.g. policy==powersupersave). This property is already present in the Raspian version of Linux, but the upstream driver implementation that follows adds more details and discerns between (a) and (b). Signed-off-by: Jim Quinlan Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 7e15aae7d69e..8b61c2179608 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -64,6 +64,15 @@ properties: aspm-no-l0s: true + brcm,enable-l1ss: + description: Indicates that PCIe L1SS power savings + are desired, the downstream device is L1SS-capable, and the + OS has been configured to enable this mode. For boards + using a mini-card connector, this mode may not meet the + TCRLon maximum time of 400ns, as specified in 3.2.5.2.2 + of the PCI Express Mini CEM 2.0 specification. + type: boolean + brcm,scb-sizes: description: u64 giving the 64bit PCIe memory viewport size of a memory controller. There may be up to From patchwork Fri Jun 23 14:40:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13290748 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AE33C001B3 for ; Fri, 23 Jun 2023 14:41:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231952AbjFWOlV (ORCPT ); Fri, 23 Jun 2023 10:41:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231864AbjFWOlT (ORCPT ); Fri, 23 Jun 2023 10:41:19 -0400 Received: from mail-qk1-x735.google.com (mail-qk1-x735.google.com [IPv6:2607:f8b0:4864:20::735]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F325D172A for ; Fri, 23 Jun 2023 07:41:10 -0700 (PDT) Received: by mail-qk1-x735.google.com with SMTP id af79cd13be357-763e1a22a68so61243185a.0 for ; Fri, 23 Jun 2023 07:41:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1687531269; x=1690123269; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=vr+1q/18XS9nyNJOpnhWi3GT/7Sprc3WsdAtTI7csII=; b=hdWv+ZTLkmwma9LxHwsrueDrlDnXUbZR+cgZTx6fXKWL/lSj6XdcFf3Jq8GujXk3Ol evJCuhVJdH0TLtz2WqUogOOSaU2tHPGYKYqTAIOWa8+GCSX4ltBXbwg9YsHOBXFY01WX e/eayNKkDHZR97eE+Fk5uPCRBonqxeeBPJyGo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687531269; x=1690123269; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=vr+1q/18XS9nyNJOpnhWi3GT/7Sprc3WsdAtTI7csII=; b=kodpozs6WwiN+2iDho4eirkX8F203jALFTzvRh34N7gSjW0K8hBGUj/2gjwP5U7sam KOphM+G130imsi1A5xKjSO8rVQddgxFSBFU88YJs8VY67755Jed433ivvG2uL4aJ4z/y 04cA+H1U3DOZEbyC5dY6DJsBu0TGT0nwIFrtwJST5E6EskPh8DCqXSTtT4vJkWGg8Y+c olvtlejAP7MRvl/cPcgHg8Wbm+aQ1d7eKzw2LhgJkKXVOLjurxoiiXFzd1Qn/fnoTthQ nOd4rq+eolb2uHvcxNUlTCN9KKQ6+moSYYvkOFFiw6SrShO/QJ0c8Pe7+tnl0owi/7UI 1VhA== X-Gm-Message-State: AC+VfDzxglwWny6o2eX+UG4ZEKM+CwPUs1inPYgiE9m+cRrAdu9TSMHf vnNVNgvJND5tCz73aNXtVwbY5cXG7rgwCPcT8UQUyi00/ILNjN0B6vdrFAl5upaN4g3pGaBoL01 AubbqCU73nO1Vq894y2VQjnhAbapN/DNIIVpNG3/zO3GJkl992BiBTuQi46h1mWwaYTSWMJTi5R RQNCk4x1DyZg== X-Google-Smtp-Source: ACHHUZ6qMOU/Dr/xZWfyf58cntxdi4IvXYnS/1XLdfxFGeFg/hftxGR16LNk1v7hMsbUSZhL9cLbew== X-Received: by 2002:a37:ad06:0:b0:763:dc8c:e85 with SMTP id f6-20020a37ad06000000b00763dc8c0e85mr7507800qkm.67.1687531269684; Fri, 23 Jun 2023 07:41:09 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id i18-20020a05620a145200b007625382f4ccsm4564613qkl.69.2023.06.23.07.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 07:41:09 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Jim Quinlan , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 2/5] PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device Date: Fri, 23 Jun 2023 10:40:55 -0400 Message-Id: <20230623144100.34196-3-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230623144100.34196-1-james.quinlan@broadcom.com> References: <20230623144100.34196-1-james.quinlan@broadcom.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The Broadcom STB/CM PCIe HW core, which is also used in RPi SOCs, must be deliberately set by the RC probe() into one of three mutually exclusive modes: (a) No CLKREQ# expected or required, refclk is always available. (b) CLKREQ# is expected to be driven by downstream device when needed. (c) Bidirectional CLKREQ# for L1SS capable devices. Previously, only (b) was supported by the driver, as almost all STB/CM boards operate in this mode. But now there is interest in activating L1SS power savings from STB/CM customers, and also interest in accommodating mode (a) for designs such as the RPi CM4 with IO board. The HW+driver is able to tell us when mode (a) or (b) is needed. All devices should be functional using the RC-driver selected (a) or (b) mode. For those with L1SS-capable devices that desire the power savings that come with mode (c) we rely on the DT prop "brcm,enable-l1ss". It would be nice to do this automatically but there is no easy way to determine this at the time the PCI RC driver executes its probe(). Using this mode only makes sense when the downstream device is L1SS-capable and the OS has been configured to activate L1SS (e.g. policy==powersupersave). The "brcm,enable-l1ss" property has already been in use by Raspian Linux, but this implementation adds more details and discerns between (a) and (b) automatically. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217276 Signed-off-by: Jim Quinlan Tested-by: Florian Fainelli Tested-by: Cyril Brulebois Tested-by: Sam Edwards --- drivers/pci/controller/pcie-brcmstb.c | 69 +++++++++++++++++++++++---- 1 file changed, 59 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index edf283e2b5dd..d30636a725d7 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -48,10 +48,17 @@ #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00 +#define PCIE_RC_CFG_PRIV1_ROOT_CAP 0x4f8 +#define PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK 0xf8 + #define PCIE_RC_DL_MDIO_ADDR 0x1100 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 +#define PCIE_0_RC_PL_PHY_DBG_CLKREQ2_0 0x1e30 +#define CLKREQ2_0_CLKREQ_IN_CNT_MASK 0x3f000000 +#define CLKREQ2_0_CLKREQ_IN_MASK 0x40000000 + #define PCIE_MISC_MISC_CTRL 0x4008 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400 @@ -121,9 +128,12 @@ #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 #define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000 - +#define PCIE_CLKREQ_MASK \ + (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \ + PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK) #define PCIE_INTR2_CPU_BASE 0x4300 #define PCIE_MSI_INTR2_BASE 0x4500 @@ -1024,13 +1034,58 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return 0; } +static void brcm_config_clkreq(struct brcm_pcie *pcie) +{ + bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss"); + void __iomem *base = pcie->base; + u32 clkreq_set, tmp = readl(base + PCIE_0_RC_PL_PHY_DBG_CLKREQ2_0); + bool clkreq_in_seen; + + /* + * We have "seen" CLKREQ# if it is asserted or has been in the past. + * Note that the CLKREQ_IN_MASK is 1 if CLKREQ# is asserted. + */ + clkreq_in_seen = !!(tmp & CLKREQ2_0_CLKREQ_IN_MASK) || + !!FIELD_GET(CLKREQ2_0_CLKREQ_IN_CNT_MASK, tmp); + + /* Start with safest setting where we provide refclk regardless */ + clkreq_set = readl(pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG) & + ~PCIE_CLKREQ_MASK; + + if (l1ss && IS_ENABLED(CONFIG_PCIEASPM)) { + /* + * Note: For boards using a mini-card connector, this mode + * (L1SS CLKREQ# mode) may not meet the TCRLon maximum time + * of 400ns, as specified in 3.2.5.2.2 of the PCI Express + * Mini CEM 2.0 specification. + */ + clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK; + dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings"); + } else { + if (clkreq_in_seen && IS_ENABLED(CONFIG_PCIEASPM)) { + clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; + dev_info(pcie->dev, "uni-dir CLKREQ# for L0s, L1 ASPM\n"); + } else { + dev_info(pcie->dev, "CLKREQ# ignored; no ASPM\n"); + /* Might as well unadvertise ASPM */ + tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY) & + ~PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK; + writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); + } + /* Setting the field to 2 unadvertises L1SS support */ + tmp = readl(base + PCIE_RC_CFG_PRIV1_ROOT_CAP); + u32p_replace_bits(&tmp, 2, PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK); + writel(tmp, base + PCIE_RC_CFG_PRIV1_ROOT_CAP); + } + writel(clkreq_set, pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); +} + static int brcm_pcie_start_link(struct brcm_pcie *pcie) { struct device *dev = pcie->dev; void __iomem *base = pcie->base; u16 nlw, cls, lnksta; bool ssc_good = false; - u32 tmp; int ret, i; /* Unassert the fundamental reset */ @@ -1055,6 +1110,8 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) return -ENODEV; } + brcm_config_clkreq(pcie); + if (pcie->gen) brcm_pcie_set_gen(pcie, pcie->gen); @@ -1073,14 +1130,6 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) pci_speed_string(pcie_link_speed[cls]), nlw, ssc_good ? "(SSC)" : "(!SSC)"); - /* - * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 - * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. - */ - tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); - tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); - return 0; } From patchwork Fri Jun 23 14:40:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13290749 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CBC1C001DB for ; Fri, 23 Jun 2023 14:41:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231864AbjFWOlX (ORCPT ); Fri, 23 Jun 2023 10:41:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231880AbjFWOlU (ORCPT ); Fri, 23 Jun 2023 10:41:20 -0400 Received: from mail-qk1-x733.google.com (mail-qk1-x733.google.com [IPv6:2607:f8b0:4864:20::733]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DB8B19BF for ; Fri, 23 Jun 2023 07:41:12 -0700 (PDT) Received: by mail-qk1-x733.google.com with SMTP id af79cd13be357-7624af57b21so59479185a.1 for ; Fri, 23 Jun 2023 07:41:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1687531271; x=1690123271; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=7JaTTX/u6r9WHG8CBb2nIc/77Q7Cm1gWqR+xNarEVL8=; b=I+viCJg201Gtd7ZT+P2U7TbN5jygxO/f53vLkGn3QZ7W1uN/olak2ftuV3CJq/3eWS byqH6UFKNIHvjQLhQRItIRIGC6mGaGvZaemuuCNW/Lyo3FEQR7soYjUyEQTMjObhaDnQ Ug0vdxAX0lthxd4068ypa280pgcitnpN46qEk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687531271; x=1690123271; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=7JaTTX/u6r9WHG8CBb2nIc/77Q7Cm1gWqR+xNarEVL8=; b=gEgPHGWV8x2NrVKUkpNZfOV3tosPVgCGw3XB6a0ZDRBMBC9yUoweSTfn0N85eZA8Ua qIu+R8le9fthw4l8ut5/3+lFNruRwIdhQbOmpoBkTYE7H8Rlrwi3SaFl4PqwsLT5Dw1g VetOAgmsbV8Q6XRJC0MrOoAhEatMxyIuo1GcoxX9S1ubCNfYS69aZrcVcERAMNMb06it WV63mjxXnaXqW3cDr6rU4SI5hQ6MBX6D7DR3XiM2FuY0OjjSkqoJqPTRuI/gYU8DWoaa 6q4afTZC2dRQuKJEUz9NS9Rw+tZqLvvdPLfRPAXx/lhz1vbmAGTRz//UY5kYsACX9mbg b8Jg== X-Gm-Message-State: AC+VfDyfxgVMGp15hI+J8+w4B/58yjUJLrQ/WKEQE/Dfv9F1ptJCjYll SyDRlTVKjIhzt3gT5AiNMoB0f6sPUOIs3NLvJtZEOV0FpKOOLXxvjRXtRH+RwthfMdNenlEKDLJ 8QfrupLHsJ+GnFVfGd4UqEbZ2uzydz/OgP0tou1tTF8mwdp1/Wh4aWoY4UzI5rRXgdBGwFHGr1f s4ZnSQYUr1ew== X-Google-Smtp-Source: ACHHUZ4VUTc2qoNcrsn8Qp7O9siw73GsqtGEpwTfEu0R/xUCLrc8O1bXbkl3FlCTdDU63D7TU7ARxg== X-Received: by 2002:a05:620a:8290:b0:763:98b4:e81f with SMTP id ox16-20020a05620a829000b0076398b4e81fmr14356285qkn.39.1687531270963; Fri, 23 Jun 2023 07:41:10 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id i18-20020a05620a145200b007625382f4ccsm4564613qkl.69.2023.06.23.07.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 07:41:10 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Jim Quinlan , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 3/5] PCI: brcmstb: Set higher value for internal bus timeout Date: Fri, 23 Jun 2023 10:40:56 -0400 Message-Id: <20230623144100.34196-4-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230623144100.34196-1-james.quinlan@broadcom.com> References: <20230623144100.34196-1-james.quinlan@broadcom.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org During long periods of the PCIe RC HW being in an L1SS sleep state, there may be a timeout on an internal bus access, even though there may not be any PCIe access involved. Such a timeout will cause a subsequent CPU abort. So, when "brcm,enable-l1ss" is observed, we increase the timeout value to four seconds instead of using its HW default. Signed-off-by: Jim Quinlan Tested-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index d30636a725d7..fe0415a98c63 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1034,6 +1034,21 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return 0; } +/* + * This extends the timeout period for an access to an internal bus. This + * access timeout may occur during L1SS sleep periods even without the + * presence of a PCIe access. + */ +static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie) +{ + /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */ + const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; + u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */ + + /* Each unit in timeout register is 1/216,000,000 seconds */ + writel(216 * timeout_us, pcie->base + REG_OFFSET); +} + static void brcm_config_clkreq(struct brcm_pcie *pcie) { bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss"); @@ -1059,6 +1074,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie) * of 400ns, as specified in 3.2.5.2.2 of the PCI Express * Mini CEM 2.0 specification. */ + brcm_extend_rbus_timeout(pcie); clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK; dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings"); } else { From patchwork Fri Jun 23 14:40:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13290750 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD3E2EB64DD for ; Fri, 23 Jun 2023 14:41:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230350AbjFWOlX (ORCPT ); Fri, 23 Jun 2023 10:41:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232017AbjFWOlW (ORCPT ); Fri, 23 Jun 2023 10:41:22 -0400 Received: from mail-qk1-x729.google.com (mail-qk1-x729.google.com [IPv6:2607:f8b0:4864:20::729]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBA4526AE for ; Fri, 23 Jun 2023 07:41:13 -0700 (PDT) Received: by mail-qk1-x729.google.com with SMTP id af79cd13be357-7624012c0b4so60088185a.1 for ; Fri, 23 Jun 2023 07:41:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1687531272; x=1690123272; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=NXsIMdLVeqRmJLvAoHxSsCTJKyoULvGWQBxYVILJlHw=; b=KmXxf2GN07ol57yvkZVILQdt7IMRHcOHQ4wgmO+Dm9xQlGfuS4payO/AMWy0bdIQEW f6YcNPzmMDoRfTT8cUY2WgJB2YxmWMDI41WN7mmMAwVYd6xTToF/VnYCiLgzheG+mpKt AiAk3++rxE7MPUm6hJ7GEfrQJMiT19IrvVBDA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687531272; x=1690123272; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=NXsIMdLVeqRmJLvAoHxSsCTJKyoULvGWQBxYVILJlHw=; b=cSSkCSAGsmHw017yI//V0XI2Uk+lX2nUnyDExJHCWMt5+qQ3C0IbfIW6ZWC0EsWYpH eS0NdtdGtUCEZsQm4GjPhG1GgFM2RDpe10ad6xo+DYwyUEDLG3ZBlM9KuLwjAOHH1ETO noD1Y6FkMCviRQKCitNaVbUkhOVFihB2QCC4uOEg8eBKM7hZG1dxqeHfQEUxSIn5DGWY wpOvr3QhzIQlrITm/W2SGJ5fdZO6o5r2PqZ1X9EgaTy8fsBFJOzJTv7KMUHPZeYbIaKV tZlxG0RsUgYa1Yb7d4t+KWF8nYnkSFKx9DnExmUgLfL2jXbSJo7fDQwva4rlzGNL/d9M f5hg== X-Gm-Message-State: AC+VfDw8OXo9/WGhESfB1T5NXEMm90rRoNoDKh8dxOQWV9jdYqI7QFJ2 b1MecXCYBZDFdSQWb4KM3NEpdUFQqoQf5ZFd7aavs9KTqZwFxLVxMx5bweM59zvbPqtWaCAGoLR A67Qr1JvDcVEdslwrFN+H7VSsVf2/WER6hC1GsteJAauFlMEQ+14NuoS3nfq6cNOfyv71x79ulr EUOwYPuFg/VQ== X-Google-Smtp-Source: ACHHUZ7YaKrVqQ8QnvGuhcY3JvOvengIIXyMeQqiinLnw5eZIkQ6quN3qI+0+AoueIHKsYdVThZWIw== X-Received: by 2002:a05:620a:2955:b0:763:a83c:a9e4 with SMTP id n21-20020a05620a295500b00763a83ca9e4mr18146840qkp.31.1687531272243; Fri, 23 Jun 2023 07:41:12 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id i18-20020a05620a145200b007625382f4ccsm4564613qkl.69.2023.06.23.07.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 07:41:11 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Jim Quinlan , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 4/5] PCI: brcmstb: Assert PERST# on BCM2711 Date: Fri, 23 Jun 2023 10:40:57 -0400 Message-Id: <20230623144100.34196-5-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230623144100.34196-1-james.quinlan@broadcom.com> References: <20230623144100.34196-1-james.quinlan@broadcom.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The current PCIe driver assumes PERST# is asserted when probe() is invoked. Some older versions of the 2711/RPi bootloader left PERST# unasserted, as the Raspian OS does assert PERST# on probe(). For this reason, we assert PERST# for BCM2711 SOCs (i.e. RPi). Signed-off-by: Jim Quinlan --- drivers/pci/controller/pcie-brcmstb.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index fe0415a98c63..7b698a9a851e 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -884,6 +884,11 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) /* Reset the bridge */ pcie->bridge_sw_init_set(pcie, 1); + + /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ + if (pcie->type == BCM2711) + pcie->perst_set(pcie, 1); + usleep_range(100, 200); /* Take the bridge out of reset */ From patchwork Fri Jun 23 14:40:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13290751 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7188EB64DD for ; Fri, 23 Jun 2023 14:41:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232054AbjFWOlm (ORCPT ); Fri, 23 Jun 2023 10:41:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232017AbjFWOl1 (ORCPT ); Fri, 23 Jun 2023 10:41:27 -0400 Received: from mail-qk1-x731.google.com (mail-qk1-x731.google.com [IPv6:2607:f8b0:4864:20::731]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5E982701 for ; Fri, 23 Jun 2023 07:41:14 -0700 (PDT) Received: by mail-qk1-x731.google.com with SMTP id af79cd13be357-763e177ba7cso54197485a.2 for ; Fri, 23 Jun 2023 07:41:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1687531273; x=1690123273; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=u1Tuv+H0UP7jJdQvld4L+xd7DpneNOOfeo+7tc+d0Kc=; b=GRYg1eZy896v/8rrS6B/irWk+oJsZE2G85Tszd28xonxR6uwHsowPGZK0bgShcoLCc g2pZ76jEaiuOjyBgmrE5Ees9TJmTGsqPpIM2BrOi/OGH2DWq2lnRr/7uDtKp595IlWa7 AsjTbRmg4ggenJch/D5OKwxlKEa8hldO0cKm4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687531273; x=1690123273; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=u1Tuv+H0UP7jJdQvld4L+xd7DpneNOOfeo+7tc+d0Kc=; b=cQUKw9NgUuiEc9Kl/SJWj/lkthJMeHqYM46gW99oVDsk1XRUc7l2NDbwZm3u0bXfWp R/1dnFFNc3srm/knFrdvQbw2D7z4lGNbVPJ7NSsvmbetO4Y7QKcZyoS7yMjagfKOYaSA CqiAqnL2BBAfXyuU7uHzBsflEKdd0xGCxRn3vu481Dg/RHCedMfk+dqmchytNXnMXySP H7pC0qfMKC1EoKAubSQ7vhhTYAZsOhK9h9qCtxK6QQmFCZLUAP+Zsolk3j6moA3DD/LT Ji4ZqWsOAmeV23VhVgJdSEg/BTpoA3Uq8NqnGqTrd0YKoSdhHZCrDJUhzMY98EaGwu08 dKuQ== X-Gm-Message-State: AC+VfDzj1liJeQH2aamT81DCGx62tjWKS83ZAKFnRJOZZlMqCzAksk3j vXLvWiFCIb9lVi7gevKYLSODkqTo2CSeWOcisYPvcE5KU8SrBvLDOnSgiQJEtpjCn4N/ao2JrSw rlrywNaSO6e7CE2gtNEs9PPz1a2CpXxfITvmnaMY1FvNtLFtsIzdu1zk8ASjTMm9mejwIr/YDkX ztTRS1piDNwg== X-Google-Smtp-Source: ACHHUZ4z22njj6lm9ZBJ1QTVTo9qcRFq/VHNwFt6J9LH8KydwGK/aHQm1kGoh7wk8yFvvRurz1fwtA== X-Received: by 2002:a05:620a:414f:b0:75b:23a1:830b with SMTP id k15-20020a05620a414f00b0075b23a1830bmr32798557qko.6.1687531273562; Fri, 23 Jun 2023 07:41:13 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id i18-20020a05620a145200b007625382f4ccsm4564613qkl.69.2023.06.23.07.41.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 07:41:13 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Jim Quinlan , Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 5/5] PCI: brcmstb: Remove stale comment Date: Fri, 23 Jun 2023 10:40:58 -0400 Message-Id: <20230623144100.34196-6-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230623144100.34196-1-james.quinlan@broadcom.com> References: <20230623144100.34196-1-james.quinlan@broadcom.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org A comment says that Multi-MSI is not supported by the driver. A past commit [1] added this feature, so the comment is incorrect and is removed. [1] commit 198acab1772f22f2 ("PCI: brcmstb: Enable Multi-MSI") Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 7b698a9a851e..acd478edbe2f 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -449,7 +449,6 @@ static struct irq_chip brcm_msi_irq_chip = { }; static struct msi_domain_info brcm_msi_domain_info = { - /* Multi MSI is supported by the controller, but not by this driver */ .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI), .chip = &brcm_msi_irq_chip,