From patchwork Sat Jun 24 00:40:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291514 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D9272EB64D7 for ; Sat, 24 Jun 2023 00:41:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EEBC310E6E3; Sat, 24 Jun 2023 00:41:06 +0000 (UTC) Received: from relay07.th.seeweb.it (relay07.th.seeweb.it [5.144.164.168]) by gabe.freedesktop.org (Postfix) with ESMTPS id 890B610E087 for ; Sat, 24 Jun 2023 00:41:05 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 1A84F3F7A5; Sat, 24 Jun 2023 02:41:02 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:40:59 +0200 Subject: [PATCH 01/15] arm64: dts: qcom: sm6125: Sort spmi_bus node numerically by reg MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-1-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This node has always resided in the wrong spot, making it somewhat harder to contribute new node entries while maintaining proper sorting around it. Move the node up to sit after hsusb_phy1 where it maintains proper numerial sorting on the (first of its many) reg address property. Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Signed-off-by: Marijn Suijten Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 38 ++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index a596baa6ce3e..722dde560bec 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -679,6 +679,24 @@ hsusb_phy1: phy@1613000 { status = "disabled"; }; + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x01c40000 0x1100>, + <0x01e00000 0x2000000>, + <0x03e00000 0x100000>, + <0x03f00000 0xa0000>, + <0x01c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram"; reg = <0x045f0000 0x7000>; @@ -1184,27 +1202,9 @@ sram@4690000 { reg = <0x04690000 0x10000>; }; - spmi_bus: spmi@1c40000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x01c40000 0x1100>, - <0x01e00000 0x2000000>, - <0x03e00000 0x100000>, - <0x03f00000 0xa0000>, - <0x01c0a000 0x26000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts = ; - qcom,ee = <0>; - qcom,channel = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - apps_smmu: iommu@c600000 { compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; - reg = <0xc600000 0x80000>; + reg = <0x0c600000 0x80000>; interrupts = , , , From patchwork Sat Jun 24 00:41:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291515 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A69F6C001B0 for ; Sat, 24 Jun 2023 00:41:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ECD5910E6EA; Sat, 24 Jun 2023 00:41:12 +0000 (UTC) Received: from relay07.th.seeweb.it (relay07.th.seeweb.it [5.144.164.168]) by gabe.freedesktop.org (Postfix) with ESMTPS id D1C5B10E087; Sat, 24 Jun 2023 00:41:05 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 57A103F7AB; Sat, 24 Jun 2023 02:41:03 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:00 +0200 Subject: [PATCH 02/15] dt-bindings: clock: qcom,dispcc-sm6125: Remove unused GCC_DISP_AHB_CLK MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-2-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The downsteam driver for dispcc only ever gets and puts this clock without ever using it in the clocktree; this unnecessary workaround was never ported to mainline, hence the driver doesn't consume this clock and shouldn't be required by the bindings. Fixes: 8397c9c0c26b ("dt-bindings: clock: add QCOM SM6125 display clock bindings") Signed-off-by: Marijn Suijten Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml index 8a210c4c5f82..2acf487d8a2f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml @@ -28,7 +28,6 @@ properties: - description: Pixel clock from DSI PHY1 - description: Link clock from DP PHY - description: VCO DIV clock from DP PHY - - description: AHB config clock from GCC clock-names: items: @@ -38,7 +37,6 @@ properties: - const: dsi1_phy_pll_out_dsiclk - const: dp_phy_pll_link_clk - const: dp_phy_pll_vco_div_clk - - const: cfg_ahb_clk '#clock-cells': const: 1 @@ -71,15 +69,13 @@ examples: <&dsi0_phy 1>, <&dsi1_phy 1>, <&dp_phy 0>, - <&dp_phy 1>, - <&gcc GCC_DISP_AHB_CLK>; + <&dp_phy 1>; clock-names = "bi_tcxo", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", "dsi1_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", - "dp_phy_pll_vco_div_clk", - "cfg_ahb_clk"; + "dp_phy_pll_vco_div_clk"; #clock-cells = <1>; #power-domain-cells = <1>; }; From patchwork Sat Jun 24 00:41:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8181EB64DD for ; Sat, 24 Jun 2023 00:41:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0405D10E6F4; Sat, 24 Jun 2023 00:41:15 +0000 (UTC) Received: from relay06.th.seeweb.it (relay06.th.seeweb.it [IPv6:2001:4b7a:2000:18::167]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1CE5310E6E4 for ; Sat, 24 Jun 2023 00:41:07 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 871603F7BA; Sat, 24 Jun 2023 02:41:04 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:01 +0200 Subject: [PATCH 03/15] dt-bindings: clock: qcom,dispcc-sm6125: Require GCC PLL0 DIV clock MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-3-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The "gcc_disp_gpll0_div_clk_src" clock is consumed by the driver, will be passed from DT, and should be required by the bindings. Fixes: 8397c9c0c26b ("dt-bindings: clock: add QCOM SM6125 display clock bindings") Signed-off-by: Marijn Suijten --- Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml index 2acf487d8a2f..11ec154503a3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml @@ -23,6 +23,7 @@ properties: clocks: items: - description: Board XO source + - description: GPLL0 div source from GCC - description: Byte clock from DSI PHY0 - description: Pixel clock from DSI PHY0 - description: Pixel clock from DSI PHY1 @@ -32,6 +33,7 @@ properties: clock-names: items: - const: bi_tcxo + - const: gcc_disp_gpll0_div_clk_src - const: dsi0_phy_pll_out_byteclk - const: dsi0_phy_pll_out_dsiclk - const: dsi1_phy_pll_out_dsiclk @@ -65,12 +67,14 @@ examples: compatible = "qcom,sm6125-dispcc"; reg = <0x5f00000 0x20000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, <&dsi0_phy 0>, <&dsi0_phy 1>, <&dsi1_phy 1>, <&dp_phy 0>, <&dp_phy 1>; clock-names = "bi_tcxo", + "gcc_disp_gpll0_div_clk_src", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", "dsi1_phy_pll_out_dsiclk", From patchwork Sat Jun 24 00:41:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291516 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 57C15C001DF for ; Sat, 24 Jun 2023 00:41:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B45610E6F1; Sat, 24 Jun 2023 00:41:14 +0000 (UTC) Received: from m-r2.th.seeweb.it (m-r2.th.seeweb.it [5.144.164.171]) by gabe.freedesktop.org (Postfix) with ESMTPS id 495FE10E6E4; Sat, 24 Jun 2023 00:41:08 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id BDA1C3F7C0; Sat, 24 Jun 2023 02:41:05 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:02 +0200 Subject: [PATCH 04/15] dt-bindings: clock: qcom,dispcc-sm6125: Allow power-domains property MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-4-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On SM6125 the dispcc block is gated behind VDDCX: allow this domain to be configured. Signed-off-by: Marijn Suijten Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml index 11ec154503a3..02796675e8f6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml @@ -46,6 +46,9 @@ properties: '#power-domain-cells': const: 1 + power-domains: + maxItems: 1 + reg: maxItems: 1 @@ -63,6 +66,7 @@ examples: - | #include #include + #include clock-controller@5f00000 { compatible = "qcom,sm6125-dispcc"; reg = <0x5f00000 0x20000>; @@ -80,6 +84,7 @@ examples: "dsi1_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", "dp_phy_pll_vco_div_clk"; + power-domains = <&rpmpd SM6125_VDDCX>; #clock-cells = <1>; #power-domain-cells = <1>; }; From patchwork Sat Jun 24 00:41:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291520 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 92B8DEB64DD for ; Sat, 24 Jun 2023 00:41:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8EDC710E6FB; Sat, 24 Jun 2023 00:41:17 +0000 (UTC) Received: from relay05.th.seeweb.it (relay05.th.seeweb.it [IPv6:2001:4b7a:2000:18::166]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5F34F10E6E7 for ; Sat, 24 Jun 2023 00:41:09 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id ED3033F7C9; Sat, 24 Jun 2023 02:41:06 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:03 +0200 Subject: [PATCH 05/15] dt-bindings: display/msm: dsi-controller-main: Document SM6125 MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-5-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Document general compatibility of the DSI controller on SM6125. Signed-off-by: Marijn Suijten Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 01848bdd5873..23926c39407e 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -27,6 +27,7 @@ properties: - qcom,sdm660-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl + - qcom,sm6125-dsi-ctrl - qcom,sm6350-dsi-ctrl - qcom,sm6375-dsi-ctrl - qcom,sm8150-dsi-ctrl @@ -301,6 +302,7 @@ allOf: contains: enum: - qcom,msm8998-dsi-ctrl + - qcom,sm6125-dsi-ctrl - qcom,sm6350-dsi-ctrl then: properties: From patchwork Sat Jun 24 00:41:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291518 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F2E2C04A94 for ; Sat, 24 Jun 2023 00:41:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 543D710E6F6; Sat, 24 Jun 2023 00:41:15 +0000 (UTC) Received: from m-r2.th.seeweb.it (m-r2.th.seeweb.it [5.144.164.171]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9C4EE10E6EC for ; Sat, 24 Jun 2023 00:41:10 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 3093E3F7EE; Sat, 24 Jun 2023 02:41:08 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:04 +0200 Subject: [PATCH 06/15] dt-bindings: display/msm: sc7180-dpu: Describe SM6125 MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-6-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" SM6125 is identical to SM6375 except that while downstream also defines a throttle clock, its presence results in timeouts whereas SM6375 requires it to not observe any timeouts. Signed-off-by: Marijn Suijten --- Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml index 630b11480496..6d2ba9a1cca1 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml @@ -15,6 +15,7 @@ properties: compatible: enum: - qcom,sc7180-dpu + - qcom,sm6125-dpu - qcom,sm6350-dpu - qcom,sm6375-dpu From patchwork Sat Jun 24 00:41:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12CD4C001B3 for ; Sat, 24 Jun 2023 00:41:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 18B4E10E6E5; Sat, 24 Jun 2023 00:41:50 +0000 (UTC) Received: from m-r2.th.seeweb.it (m-r2.th.seeweb.it [5.144.164.171]) by gabe.freedesktop.org (Postfix) with ESMTPS id CFFD510E6EC for ; Sat, 24 Jun 2023 00:41:11 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 6288F3F7EB; Sat, 24 Jun 2023 02:41:09 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:05 +0200 Subject: [PATCH 07/15] dt-bindings: display/msm: Add SM6125 MDSS MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-7-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Document the SM6125 MDSS. Signed-off-by: Marijn Suijten Reviewed-by: Krzysztof Kozlowski --- .../bindings/display/msm/qcom,sm6125-mdss.yaml | 206 +++++++++++++++++++++ 1 file changed, 206 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml new file mode 100644 index 000000000000..e4db05c4a464 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml @@ -0,0 +1,206 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6125 Display MDSS + +maintainers: + - Marijn Suijten + +description: + SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm6125-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6125-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm6125-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-14nm-6125 + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@5e00000 { + compatible = "qcom,sm6125-mdss"; + reg = <0x05e00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "ahb", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x400 0x0>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@5e01000 { + compatible = "qcom,sm6125-dpu"; + reg = <0x05e01000 0x83208>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "iface", + "rot", + "lut", + "core", + "vsync"; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6125_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + }; + + dsi@5e94000 { + compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x05e94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SM6125_VDDMX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + phy@5e94400 { + compatible = "qcom,dsi-phy-14nm-6125"; + reg = <0x05e94400 0x100>, + <0x05e94500 0x300>, + <0x05e94800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + }; + }; +... From patchwork Sat Jun 24 00:41:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291519 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9A839C001B3 for ; Sat, 24 Jun 2023 00:41:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9CA9810E6F8; Sat, 24 Jun 2023 00:41:15 +0000 (UTC) Received: from relay05.th.seeweb.it (relay05.th.seeweb.it [5.144.164.166]) by gabe.freedesktop.org (Postfix) with ESMTPS id 14B0810E6ED for ; Sat, 24 Jun 2023 00:41:13 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 970AF3F7F3; Sat, 24 Jun 2023 02:41:10 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:06 +0200 Subject: [PATCH 08/15] drm/msm/dpu: Add SM6125 support MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-8-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add definitions for the display hardware used on the Qualcomm SM6125 platform. Signed-off-by: Marijn Suijten --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 173 +++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 181 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h new file mode 100644 index 000000000000..39c698f793fe --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Marijn Suijten . All rights reserved. + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_5_4_SM6125_H +#define _DPU_5_4_SM6125_H + +static const struct dpu_caps sm6125_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0x6, + .has_dim_layer = true, + .has_idle_pc = true, + .max_linewidth = 2160, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp = MAX_HORZ_DECIMATION, + .max_vdeci_exp = MAX_VERT_DECIMATION, +}; + +static const struct dpu_ubwc_cfg sm6125_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_10, + .highest_bank_bit = 0x1, + .ubwc_swizzle = 0x1, +}; + +static const struct dpu_mdp_cfg sm6125_mdp[] = { + { + .name = "top_0", .id = MDP_TOP, + .base = 0x0, .len = 0x45c, + .features = 0, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + }, + }, +}; + +static const struct dpu_ctl_cfg sm6125_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a00, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sm6125_sspp[] = { + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SM6125_MASK, + sm6125_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK, + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK, + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), +}; + +static const struct dpu_lm_cfg sm6125_lm[] = { + LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, + &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), + LM_BLK("lm_1", LM_1, 0x45000, MIXER_QCM2290_MASK, + &sdm845_lm_sblk, PINGPONG_1, LM_0, 0), +}; + +static const struct dpu_dspp_cfg sm6125_dspp[] = { + DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, + &sm8150_dspp_sblk), +}; + +static const struct dpu_pingpong_cfg sm6125_pp[] = { + PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + -1), + PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + -1), +}; + +static const struct dpu_intf_cfg sm6125_intf[] = { + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, + INTF_SC7180_MASK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), +}; + +static const struct dpu_perf_cfg sm6125_perf_data = { + .max_bw_low = 4100000, + .max_bw_high = 4100000, + .min_core_ib = 2400000, + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .min_prefill_lines = 24, + .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sm8150_qos_linear), + .entries = sm8150_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +const struct dpu_mdss_cfg dpu_sm6125_cfg = { + .caps = &sm6125_dpu_caps, + .ubwc = &sm6125_ubwc_cfg, + .mdp_count = ARRAY_SIZE(sm6125_mdp), + .mdp = sm6125_mdp, + .ctl_count = ARRAY_SIZE(sm6125_ctl), + .ctl = sm6125_ctl, + .sspp_count = ARRAY_SIZE(sm6125_sspp), + .sspp = sm6125_sspp, + .mixer_count = ARRAY_SIZE(sm6125_lm), + .mixer = sm6125_lm, + .dspp_count = ARRAY_SIZE(sm6125_dspp), + .dspp = sm6125_dspp, + .pingpong_count = ARRAY_SIZE(sm6125_pp), + .pingpong = sm6125_pp, + .intf_count = ARRAY_SIZE(sm6125_intf), + .intf = sm6125_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .perf = &sm6125_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF1_TEAR_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 0de507d4d7b7..8a02bbdaae8a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -33,6 +33,9 @@ #define VIG_SC7180_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) +#define VIG_SM6125_MASK \ + (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) + #define VIG_SC7180_MASK_SDMA \ (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) @@ -348,6 +351,8 @@ static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4); +static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 = + _VIG_SBLK("0", 3, DPU_SSPP_SCALER_QSEED3LITE); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4); @@ -762,6 +767,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { #include "catalog/dpu_5_0_sm8150.h" #include "catalog/dpu_5_1_sc8180x.h" +#include "catalog/dpu_5_4_sm6125.h" #include "catalog/dpu_6_0_sm8250.h" #include "catalog/dpu_6_2_sc7180.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index b860784ade72..4314235cb2b8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -861,6 +861,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; extern const struct dpu_mdss_cfg dpu_sm8250_cfg; extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; +extern const struct dpu_mdss_cfg dpu_sm6125_cfg; extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; extern const struct dpu_mdss_cfg dpu_sm6375_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index aa8499de1b9f..a1c7ffb6dffb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1305,6 +1305,7 @@ static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, }, { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, }, { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, }, + { .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, }, { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, }, { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, }, { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, }, From patchwork Sat Jun 24 00:41:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B01E5C00528 for ; Sat, 24 Jun 2023 00:41:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0E45910E6FF; Sat, 24 Jun 2023 00:41:18 +0000 (UTC) Received: from m-r2.th.seeweb.it (m-r2.th.seeweb.it [5.144.164.171]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4990610E6F4; Sat, 24 Jun 2023 00:41:14 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id CC85F3F81A; Sat, 24 Jun 2023 02:41:11 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:07 +0200 Subject: [PATCH 09/15] drm/msm/mdss: Add SM6125 support MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-9-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" SM6125's UBWC hardware decoder is version 3.0, and supports decoding UBWC 1.0. Signed-off-by: Marijn Suijten --- drivers/gpu/drm/msm/msm_mdss.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 05648c910c68..bf68bae23264 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -559,6 +559,13 @@ static const struct msm_mdss_data sm6115_data = { .ubwc_static = 0x11f, }; +static const struct msm_mdss_data sm6125_data = { + .ubwc_version = UBWC_1_0, + .ubwc_dec_version = UBWC_3_0, + .ubwc_swizzle = 1, + .highest_bank_bit = 1, +}; + static const struct msm_mdss_data sm8250_data = { .ubwc_version = UBWC_4_0, .ubwc_dec_version = UBWC_4_0, @@ -579,6 +586,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data }, { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data }, { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data }, + { .compatible = "qcom,sm6125-mdss", .data = &sm6125_data }, { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data }, { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data }, { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data }, From patchwork Sat Jun 24 00:41:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291524 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 661C8C001DD for ; Sat, 24 Jun 2023 00:41:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1793710E700; Sat, 24 Jun 2023 00:41:38 +0000 (UTC) Received: from m-r2.th.seeweb.it (m-r2.th.seeweb.it [5.144.164.171]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7F0AD10E6F7; Sat, 24 Jun 2023 00:41:15 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 11A163F83D; Sat, 24 Jun 2023 02:41:13 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:08 +0200 Subject: [PATCH 10/15] dt-bindings: msm: dsi-phy-14nm: Document SM6125 variant MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-10-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Document availability of the 14nm DSI PHY on SM6125. Signed-off-by: Marijn Suijten Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml index a43e11d3b00d..60b590f21138 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml @@ -18,6 +18,7 @@ properties: - qcom,dsi-phy-14nm - qcom,dsi-phy-14nm-2290 - qcom,dsi-phy-14nm-660 + - qcom,dsi-phy-14nm-6125 - qcom,dsi-phy-14nm-8953 reg: From patchwork Sat Jun 24 00:41:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291526 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B9BFC001DE for ; Sat, 24 Jun 2023 00:41:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1989E10E704; Sat, 24 Jun 2023 00:41:39 +0000 (UTC) Received: from relay08.th.seeweb.it (relay08.th.seeweb.it [IPv6:2001:4b7a:2000:18::169]) by gabe.freedesktop.org (Postfix) with ESMTPS id B5C5B10E6FC for ; Sat, 24 Jun 2023 00:41:17 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 45C823F84F; Sat, 24 Jun 2023 02:41:14 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:09 +0200 Subject: [PATCH 11/15] drm/msm/dsi: Add 14nm phy configuration for SM6125 MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-11-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" SM6125 features only a single PHY (despite a secondary PHY PLL source being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream sources for this "trinket" SoC do not define the typical "vcca" regulator to be available nor used. Signed-off-by: Marijn Suijten --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 15 +++++++++++++++ 3 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 9d5795c58a98..8688ed502dcf 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -559,6 +559,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_14nm_2290_cfgs }, { .compatible = "qcom,dsi-phy-14nm-660", .data = &dsi_phy_14nm_660_cfgs }, + { .compatible = "qcom,dsi-phy-14nm-6125", + .data = &dsi_phy_14nm_6125_cfgs }, { .compatible = "qcom,dsi-phy-14nm-8953", .data = &dsi_phy_14nm_8953_cfgs }, #endif diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 8b640d174785..ebf915f5e6c6 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -52,6 +52,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_6125_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 3ce45b023e63..5d43c9ec69ae 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -1068,6 +1068,21 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { .num_dsi_phy = 2, }; +const struct msm_dsi_phy_cfg dsi_phy_14nm_6125_cfgs = { + .has_phy_lane = true, + .ops = { + .enable = dsi_14nm_phy_enable, + .disable = dsi_14nm_phy_disable, + .pll_init = dsi_pll_14nm_init, + .save_pll_state = dsi_14nm_pll_save_state, + .restore_pll_state = dsi_14nm_pll_restore_state, + }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, + .io_start = { 0x5e94400 }, + .num_dsi_phy = 1, +}; + const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = { .has_phy_lane = true, .regulator_data = dsi_phy_14nm_17mA_regulators, From patchwork Sat Jun 24 00:41:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291528 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 678FBC001DF for ; Sat, 24 Jun 2023 00:41:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 01C4410E0EA; Sat, 24 Jun 2023 00:41:50 +0000 (UTC) Received: from relay08.th.seeweb.it (relay08.th.seeweb.it [IPv6:2001:4b7a:2000:18::169]) by gabe.freedesktop.org (Postfix) with ESMTPS id 015C010E6F5 for ; Sat, 24 Jun 2023 00:41:17 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 78D663F853; Sat, 24 Jun 2023 02:41:15 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:10 +0200 Subject: [PATCH 12/15] arm64: dts: qcom: sm6125: Switch fixed xo_board clock to RPM XO clock MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-12-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" We have a working RPM XO clock; no other driver except rpmcc should be parenting directly to the fixed-factor xo_board clock nor should it be reachable by that global name. Remove the name to that effect, so that every clock relation is explicitly defined in DTS. Signed-off-by: Marijn Suijten Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 722dde560bec..edb03508dba3 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -22,7 +22,6 @@ xo_board: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; - clock-output-names = "xo_board"; }; sleep_clk: sleep-clk { @@ -306,6 +305,8 @@ rpm_requests: rpm-requests { rpmcc: clock-controller { compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; }; rpmpd: power-controller { @@ -713,7 +714,7 @@ sdhc_1: mmc@4744000 { clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; iommus = <&apps_smmu 0x160 0x0>; @@ -740,7 +741,7 @@ sdhc_2: mmc@4784000 { clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; iommus = <&apps_smmu 0x180 0x0>; From patchwork Sat Jun 24 00:41:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291522 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E143BC001B3 for ; Sat, 24 Jun 2023 00:41:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9853C10E6EC; Sat, 24 Jun 2023 00:41:36 +0000 (UTC) Received: from m-r2.th.seeweb.it (m-r2.th.seeweb.it [5.144.164.171]) by gabe.freedesktop.org (Postfix) with ESMTPS id 415FD10E6F5; Sat, 24 Jun 2023 00:41:19 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id AF3003F858; Sat, 24 Jun 2023 02:41:16 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:11 +0200 Subject: [PATCH 13/15] arm64: dts: qcom: sm6125: Add dispcc node MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-13-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable and configure the dispcc node on SM6125 for consumption by MDSS later on. Signed-off-by: Marijn Suijten --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index edb03508dba3..7d78b4e48ebe 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021, Martin Botka */ +#include #include #include #include @@ -1203,6 +1204,28 @@ sram@4690000 { reg = <0x04690000 0x10000>; }; + dispcc: clock-controller@5f00000 { + compatible = "qcom,sm6125-dispcc"; + reg = <0x05f00000 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + power-domains = <&rpmpd SM6125_VDDCX>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + apps_smmu: iommu@c600000 { compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0c600000 0x80000>; From patchwork Sat Jun 24 00:41:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 731E1C001B0 for ; Sat, 24 Jun 2023 00:41:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ACC5510E6F0; Sat, 24 Jun 2023 00:41:36 +0000 (UTC) Received: from m-r2.th.seeweb.it (m-r2.th.seeweb.it [IPv6:2001:4b7a:2000:18::171]) by gabe.freedesktop.org (Postfix) with ESMTPS id 20F3A10E700 for ; Sat, 24 Jun 2023 00:41:21 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id E36E73F85B; Sat, 24 Jun 2023 02:41:17 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:12 +0200 Subject: [PATCH 14/15] arm64: dts: qcom: sm6125: Add display hardware nodes MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-14-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the DT nodes that describe the MDSS hardware on SM6125, containing one MDP (display controller) together with a single DSI and DSI PHY. No DisplayPort support is added for now. Signed-off-by: Marijn Suijten --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 190 ++++++++++++++++++++++++++++++++++- 1 file changed, 186 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 7d78b4e48ebe..6852dacf54e6 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -1204,16 +1204,198 @@ sram@4690000 { reg = <0x04690000 0x10000>; }; + mdss: display-subsystem@5e00000 { + compatible = "qcom,sm6125-mdss"; + reg = <0x05e00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "ahb", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x400 0x0>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mdss_mdp: display-controller@5e01000 { + compatible = "qcom,sm6125-dpu"; + reg = <0x05e01000 0x83208>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "iface", + "rot", + "lut", + "core", + "vsync"; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6125_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-256000000 { + opp-hz = /bits/ 64 <256000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@5e94000 { + compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x05e94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SM6125_VDDMX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-164000000 { + opp-hz = /bits/ 64 <164000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_svs>; + }; + }; + }; + + mdss_dsi0_phy: phy@5e94400 { + compatible = "qcom,dsi-phy-14nm-6125"; + reg = <0x05e94400 0x100>, + <0x05e94500 0x300>, + <0x05e94800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + dispcc: clock-controller@5f00000 { compatible = "qcom,sm6125-dispcc"; reg = <0x05f00000 0x20000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, <0>, <0>, - <0>, - <0>, - <0>, - <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; + <0>; clock-names = "bi_tcxo", "gcc_disp_gpll0_div_clk_src", "dsi0_phy_pll_out_byteclk", From patchwork Sat Jun 24 00:41:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13291525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D51A1C001B3 for ; Sat, 24 Jun 2023 00:41:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1CD8010E703; Sat, 24 Jun 2023 00:41:38 +0000 (UTC) Received: from relay06.th.seeweb.it (relay06.th.seeweb.it [5.144.164.167]) by gabe.freedesktop.org (Postfix) with ESMTPS id 35F2F10E709; Sat, 24 Jun 2023 00:41:22 +0000 (UTC) Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 22CA43F85C; Sat, 24 Jun 2023 02:41:19 +0200 (CEST) From: Marijn Suijten Date: Sat, 24 Jun 2023 02:41:13 +0200 Subject: [PATCH 15/15] arm64: dts: qcom: sm6125-seine: Configure MDSS, DSI and panel MIME-Version: 1.0 Message-Id: <20230624-sm6125-dpu-v1-15-1d5a638cebf2@somainline.org> References: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> In-Reply-To: <20230624-sm6125-dpu-v1-0-1d5a638cebf2@somainline.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Krishna Manikandan X-Mailer: b4 0.12.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Lux Aliaga , Martin Botka , ~postmarketos/upstreaming@lists.sr.ht, Marijn Suijten , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org, AngeloGioacchino Del Regno Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable MDSS and DSI, and configure the Samsung SOFEF01-M ams597ut01 6.0" 1080x2520 panel. Signed-off-by: Marijn Suijten --- .../dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 9f8a9ef398a2..bdf7c15f9b83 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -179,6 +179,43 @@ &i2c3 { /* Cirrus Logic CS35L41 boosted audio amplifier @ 40 */ }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm6125_l18>; + status = "okay"; + + panel@0 { + compatible = "samsung,sofef01-m-ams597ut01"; + reg = <0>; + + reset-gpios = <&tlmm 90 GPIO_ACTIVE_LOW>; + + vddio-supply = <&pm6125_l12>; + + pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>; + pinctrl-1 = <&sde_dsi_sleep &sde_te_active_sleep>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + &pm6125_adc { pinctrl-names = "default"; pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>; @@ -469,6 +506,28 @@ vol_down_n: vol-down-n-state { drive-strength = <2>; bias-disable; }; + + sde_te_active_sleep: sde-te-active-sleep-state { + pins = "gpio89"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_dsi_active: sde-dsi-active-state { + pins = "gpio90"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + sde_dsi_sleep: sde-dsi-sleep-state { + pins = "gpio90"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; &usb3 {