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If it is enabled by default, it can be problematic when the ocelot driver is a DSA master, and it sidesteps what DSA tries to avoid through __dsa_master_hwtstamp_validate(). Additionally, after the change which made ocelot trap PTP packets only to the CPU at ocelot_hwtstamp_set() time, it is no longer even true that RX timestamping is enabled by default, because until ocelot_hwtstamp_set() is called, the PTP traps are actually not set up. So the rx_filter field of ocelot->hwtstamp_config reflects an incorrect reality. Fixes: 96ca08c05838 ("net: mscc: ocelot: set up traps for PTP packets") Fixes: 4e3b0468e6d7 ("net: mscc: PTP Hardware Clock (PHC) support") Signed-off-by: Vladimir Oltean --- v1->v2: none drivers/net/ethernet/mscc/ocelot_ptp.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot_ptp.c b/drivers/net/ethernet/mscc/ocelot_ptp.c index 2180ae94c744..673bfd70867a 100644 --- a/drivers/net/ethernet/mscc/ocelot_ptp.c +++ b/drivers/net/ethernet/mscc/ocelot_ptp.c @@ -824,11 +824,6 @@ int ocelot_init_timestamp(struct ocelot *ocelot, ocelot_write(ocelot, PTP_CFG_MISC_PTP_EN, PTP_CFG_MISC); - /* There is no device reconfiguration, PTP Rx stamping is always - * enabled. - */ - ocelot->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; - return 0; } EXPORT_SYMBOL(ocelot_init_timestamp); From patchwork Tue Jun 27 16:31:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 13294802 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E03C01C74C for ; Tue, 27 Jun 2023 16:31:35 +0000 (UTC) Received: from EUR02-DB5-obe.outbound.protection.outlook.com (mail-db5eur02on2086.outbound.protection.outlook.com [40.107.249.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CAA283AB2; Tue, 27 Jun 2023 09:31:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CsdFI4WgKG1K0dMUhUvBoHC02NZTtlIKKZ1ephCpx8UJXvcuXwhfSfwpgdzZyVg6urISqMEttbpDSsAOWhgQgHJ5Kfo2HtDvSiaNivQTOFtxjVu/4I5ceVd02LnOI3W/hnv3DltY3PLTpN6ge+fCxlo8PIIwt1cxoQ5Pul7p2ppGqSF6xx9+iDnCWAR0AK1LqIEbIx0Xr5bJk5ddr9weoydl+6bXxzTHYE560T4LGoMppXJqb33jepQ7TuBujjXclz9jX08BawKgJL+7ilfrMgTlElNXSvPEc8UfuZzrKT7LyJM5MaBUrnR0yW77t59mtlKVP69ydfadxd9IfN1LlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Xb/bNxr5qDDU+4/yXYImJYFMcP2Sz2XQqYzvM23C2LE=; b=VqRSvDvC1iiiyYMHhDXBE1WHaGyFZoalw9iFWucrmnomFsLfOAfdNr+PtsKpanadthH2PG8ytpzs6yamEMEUQXifIfEDTsSSDDRs2qrmvi7s6wJYAvdgW60EPLh1zhSyBNq8H6+xcxLRKjxOZmzuPlvgZuDC+gL9xGJ4X0FYLP2ucxU00Ij0Xy86c4ZbBOBkY/9cEJQUtqHe8ZKZ1jE4FSXYeXOIpWiV8gmQYxCT2A9GL9BapKztlg/4iSwIvpGDz0kqly0Wd+29RuooZA5ICqvZoE2NG7b34TDoaVqKsfvUoe+hTkMXINPls5zoOf/RmArQl9cF2bTYMUUOMAf3pw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Xb/bNxr5qDDU+4/yXYImJYFMcP2Sz2XQqYzvM23C2LE=; b=coOSJRjMAJKLMV7nE3FyIftZimQoO0TnvhQMqHHe9TQq6WKA4Pn0EulkOjtZAFd8R295IxsqV8DNUbUmouLJkmIkFY5hMAWUgqKojvbZOW7DRqH3xjMINMsiWDwn9rQkcRdlXkKoSWz9XFkYD53nDozoWVhFLKhJF1Sw0LGxpbQ= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM0PR04MB6452.eurprd04.prod.outlook.com (2603:10a6:208:16d::21) by AM8PR04MB7314.eurprd04.prod.outlook.com (2603:10a6:20b:1df::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6521.26; Tue, 27 Jun 2023 16:31:30 +0000 Received: from AM0PR04MB6452.eurprd04.prod.outlook.com ([fe80::c40e:d76:fd88:f460]) by AM0PR04MB6452.eurprd04.prod.outlook.com ([fe80::c40e:d76:fd88:f460%5]) with mapi id 15.20.6521.026; Tue, 27 Jun 2023 16:31:30 +0000 From: Vladimir Oltean To: netdev@vger.kernel.org Cc: Andrew Lunn , Florian Fainelli , "David S. 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The driver supports different RX filters (L2, L4) and kinds of TX timestamping (one-step, two-step) on its ports, but it saves all configuration in a single struct hwtstamp_config that is global to the switch. So, the latest timestamping configuration on one port (including a request to disable timestamping) affects what gets reported for all ports, even though the configuration itself is still individual to each port. The port timestamping configurations are only coupled because of the common structure, so replace the hwtstamp_config with a mask of trapped protocols saved per port. We also have the ptp_cmd to distinguish between one-step and two-step PTP timestamping, so with those 2 bits of information we can fully reconstruct a descriptive struct hwtstamp_config for each port, during the SIOCGHWTSTAMP ioctl. Fixes: 4e3b0468e6d7 ("net: mscc: PTP Hardware Clock (PHC) support") Fixes: 96ca08c05838 ("net: mscc: ocelot: set up traps for PTP packets") Signed-off-by: Vladimir Oltean --- v1->v2: replace the ocelot_port->ptp_rx_filters (bit mask of UAPI enum hwtstamp_rx_filters) with the hardware-specific trap_proto (bit mask of enum ocelot_proto). This makes it easier for the next patch to distinguish between L2 and L4 PTP (not easy when saving the UAPI format). drivers/net/ethernet/mscc/ocelot.c | 1 - drivers/net/ethernet/mscc/ocelot_ptp.c | 61 +++++++++++++++++--------- include/soc/mscc/ocelot.h | 10 +++-- 3 files changed, 48 insertions(+), 24 deletions(-) diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c index 1f5f00b30441..2fa833d041ba 100644 --- a/drivers/net/ethernet/mscc/ocelot.c +++ b/drivers/net/ethernet/mscc/ocelot.c @@ -2925,7 +2925,6 @@ int ocelot_init(struct ocelot *ocelot) } } - mutex_init(&ocelot->ptp_lock); mutex_init(&ocelot->mact_lock); mutex_init(&ocelot->fwd_domain_lock); mutex_init(&ocelot->tas_lock); diff --git a/drivers/net/ethernet/mscc/ocelot_ptp.c b/drivers/net/ethernet/mscc/ocelot_ptp.c index 673bfd70867a..cb32234a5bf1 100644 --- a/drivers/net/ethernet/mscc/ocelot_ptp.c +++ b/drivers/net/ethernet/mscc/ocelot_ptp.c @@ -439,8 +439,12 @@ static int ocelot_ipv6_ptp_trap_del(struct ocelot *ocelot, int port) static int ocelot_setup_ptp_traps(struct ocelot *ocelot, int port, bool l2, bool l4) { + struct ocelot_port *ocelot_port = ocelot->ports[port]; int err; + ocelot_port->trap_proto &= ~(OCELOT_PROTO_PTP_L2 | + OCELOT_PROTO_PTP_L4); + if (l2) err = ocelot_l2_ptp_trap_add(ocelot, port); else @@ -464,6 +468,11 @@ static int ocelot_setup_ptp_traps(struct ocelot *ocelot, int port, if (err) return err; + if (l2) + ocelot_port->trap_proto |= OCELOT_PROTO_PTP_L2; + if (l4) + ocelot_port->trap_proto |= OCELOT_PROTO_PTP_L4; + return 0; err_ipv6: @@ -474,10 +483,38 @@ static int ocelot_setup_ptp_traps(struct ocelot *ocelot, int port, return err; } +static int ocelot_traps_to_ptp_rx_filter(unsigned int proto) +{ + if ((proto & OCELOT_PROTO_PTP_L2) && (proto & OCELOT_PROTO_PTP_L4)) + return HWTSTAMP_FILTER_PTP_V2_EVENT; + else if (proto & OCELOT_PROTO_PTP_L2) + return HWTSTAMP_FILTER_PTP_V2_L2_EVENT; + else if (proto & OCELOT_PROTO_PTP_L4) + return HWTSTAMP_FILTER_PTP_V2_L4_EVENT; + + return HWTSTAMP_FILTER_NONE; +} + int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) { - return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, - sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; + struct ocelot_port *ocelot_port = ocelot->ports[port]; + struct hwtstamp_config cfg = {}; + + switch (ocelot_port->ptp_cmd) { + case IFH_REW_OP_TWO_STEP_PTP: + cfg.tx_type = HWTSTAMP_TX_ON; + break; + case IFH_REW_OP_ORIGIN_PTP: + cfg.tx_type = HWTSTAMP_TX_ONESTEP_SYNC; + break; + default: + cfg.tx_type = HWTSTAMP_TX_OFF; + break; + } + + cfg.rx_filter = ocelot_traps_to_ptp_rx_filter(ocelot_port->trap_proto); + + return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; } EXPORT_SYMBOL(ocelot_hwstamp_get); @@ -509,8 +546,6 @@ int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) return -ERANGE; } - mutex_lock(&ocelot->ptp_lock); - switch (cfg.rx_filter) { case HWTSTAMP_FILTER_NONE: break; @@ -531,28 +566,14 @@ int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) l4 = true; break; default: - mutex_unlock(&ocelot->ptp_lock); return -ERANGE; } err = ocelot_setup_ptp_traps(ocelot, port, l2, l4); - if (err) { - mutex_unlock(&ocelot->ptp_lock); + if (err) return err; - } - - if (l2 && l4) - cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; - else if (l2) - cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; - else if (l4) - cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; - else - cfg.rx_filter = HWTSTAMP_FILTER_NONE; - /* Commit back the result & save it */ - memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); - mutex_unlock(&ocelot->ptp_lock); + cfg.rx_filter = ocelot_traps_to_ptp_rx_filter(ocelot_port->trap_proto); return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; } diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h index cb8fbb241879..22aae505c813 100644 --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h @@ -730,6 +730,11 @@ enum macaccess_entry_type { ENTRYTYPE_MACv6, }; +enum ocelot_proto { + OCELOT_PROTO_PTP_L2 = BIT(0), + OCELOT_PROTO_PTP_L4 = BIT(1), +}; + #define OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION BIT(0) #define OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP BIT(1) @@ -775,6 +780,8 @@ struct ocelot_port { unsigned int ptp_skbs_in_flight; struct sk_buff_head tx_skbs; + unsigned int trap_proto; + u16 mrp_ring_id; u8 ptp_cmd; @@ -868,12 +875,9 @@ struct ocelot { u8 mm_supported:1; struct ptp_clock *ptp_clock; struct ptp_clock_info ptp_info; - struct hwtstamp_config hwtstamp_config; unsigned int ptp_skbs_in_flight; /* Protects the 2-step TX timestamp ID logic */ spinlock_t ts_id_lock; - /* Protects the PTP interface state */ - struct mutex ptp_lock; /* Protects the PTP clock */ spinlock_t ptp_clock_lock; struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM]; From patchwork Tue Jun 27 16:31:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vladimir Oltean X-Patchwork-Id: 13294803 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BCC31DDCB for ; Tue, 27 Jun 2023 16:31:38 +0000 (UTC) Received: from EUR02-DB5-obe.outbound.protection.outlook.com (mail-db5eur02on2086.outbound.protection.outlook.com [40.107.249.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0C513AB7; Tue, 27 Jun 2023 09:31:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lJTno22RrgP1c4aEqqKmZ+axVuFTmf4KNiGAzpYzZky0SbEcRF7NsvtwaT7amiN+IsjXDjRq/L4bwIh6qTP2R/qH+FmpEZ0bAbpyPl08ZfiR05uQ2MTwCrJxJECiMAXM0dUrsTmn3CHkJLCb1SL0syJI1dRnXKNOUzYJqs+1j78WMfoC2mRE99FMfpj6YwFLC2MxM22Y3DWD6XoEZp2Rpn4SL9MvW8Ecnh3ylv8WaRlrhpJHSge+u0eagxsYQNLYqQbW9dv0qKHXRkA7wUaS7UR0IqmbO1Oovtyh6W1QhMOsdd50Fr9m7UxZWp9Accy+Ft04HeQKlhsoOtyF36041g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zzsh9DezhFnr46zoqNwvG2xkkkAQf05VNJB7IfbkEmc=; b=F9gYKWY19R5Kj20Df2B+4YWmKUiwOb8pNv5V8m/oQuvRBWQC5eE7ldEdcH6qLAHdiIiI4UfmCEM+JQlnRcmVUmUNGWhRJRjnml6Z6T4ZcsKSpH+dinWBRG7EISfImOB7p+ueMWa2aWp7M1Ku9qt+7OEaHoIELB7qCe2uDwnJ4gfj/AbXL+Tb2FAC4JHSEc4JdmS3vSPICf4YjUTTJZHUl8uofT4Wh2oF9QrHMzT+S2UeVtssjWlB+awx0IghCkgSwNT3IfzL+Gog6SrvgAkuNC7ECRaqWGfy1kFWmapZRt4XoIbu42lYLERFLgFYds3DiQAsE0B7u+5qPLY6Zpq2cA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zzsh9DezhFnr46zoqNwvG2xkkkAQf05VNJB7IfbkEmc=; b=QQfqcmXWJaTea9FiaS4G64o+Jc/ulPZkas+kiuXPg45T5LyByCp6OUJHqOYODuRKn59pul3ge4dkf7yT5z18C/Z0g88RoOxYt3hluJT+cTfrnoKFEfxM+Rgykx2c8f7B40vhvwbiyByIBvsu8aX6Ce7l66QLIo50d+yFrWANLuI= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM0PR04MB6452.eurprd04.prod.outlook.com (2603:10a6:208:16d::21) by AM8PR04MB7314.eurprd04.prod.outlook.com (2603:10a6:20b:1df::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6521.26; Tue, 27 Jun 2023 16:31:32 +0000 Received: from AM0PR04MB6452.eurprd04.prod.outlook.com ([fe80::c40e:d76:fd88:f460]) by AM0PR04MB6452.eurprd04.prod.outlook.com ([fe80::c40e:d76:fd88:f460%5]) with mapi id 15.20.6521.026; Tue, 27 Jun 2023 16:31:32 +0000 From: Vladimir Oltean To: netdev@vger.kernel.org Cc: Andrew Lunn , Florian Fainelli , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Claudiu Manoil , Alexandre Belloni , UNGLinuxDriver@microchip.com, Xiaoliang Yang , Richard Cochran , Antoine Tenart , linux-kernel@vger.kernel.org Subject: [PATCH v2 net 3/3] net: dsa: felix: don't drop PTP frames with tag_8021q when RX timestamping is disabled Date: Tue, 27 Jun 2023 19:31:14 +0300 Message-Id: <20230627163114.3561597-4-vladimir.oltean@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230627163114.3561597-1-vladimir.oltean@nxp.com> References: <20230627163114.3561597-1-vladimir.oltean@nxp.com> X-ClientProxiedBy: FR3P281CA0078.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:1f::19) To AM0PR04MB6452.eurprd04.prod.outlook.com (2603:10a6:208:16d::21) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM0PR04MB6452:EE_|AM8PR04MB7314:EE_ X-MS-Office365-Filtering-Correlation-Id: ffcf2c18-e482-417d-708b-08db772bf737 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KkLbsVZXS1PZHAvS4lM4uUpcnTxJJmEFE8FilFhtkmNKvCdHImYJdIAW0u+I8McGkwl1VGNpUtDngMYxDYMnx6G9gYuxkxA2/5dlWjPOhlASQUY20OTXeHR9JgdLImgygPdJtRaRVUZa55H9WnyddxJtGRqN8fHvVI32jJLIA/OUpNcgFuq/s6KQwAez6Uht+21MY4AmOqiUhrc8Ue0YXNZ5c/ITJCno0UfktEdIGuLGTXnUK6gNqV+SgJdlRsp724SCqe7UFDBLI15dXud3hrvbrq4BYJDRwYeWVpngGUvKSvychTOB/HBitGGOUpaPTxbB72/JRVdFdFN9Pt0IpS5nVVlKQm63i/57bFJI5G3or8Qubo3aOUh49/WfPCL2bxLOqrLptearftr7P2+FTIPjP3rbxzSs4pKXympN15xHj/A79le2vTIMyBht+r+sgVg85D9JwBjss7/5LBMEn3+xzxLxkg+jxkXI4+oG0PZdzRXuQ7gNJNKcijH5rep3PU2G7D84iP78OyRCn9VzPaCG88DgjuIJAsQ1h1IWXvwWR/5VMyaUD4pJBzluWS4i7gviD+V+J2q1Fmfi6+vcZIZX43n5/3ga9A1v/69p+Ehutx/fFCNxHwfJgH7btIYX1PoxRe4K0fUNINT5p/oCs/GPH40DPMcDBvv/NxRt/hj6SlP/rXVPpBUv7ARzJDKXEBdIJlyyxwR8GGh/MW9lJNz30tKZVl9Uhka/Z6GmMQRo1Rz13O9IMGGWMEwjsGXiGt7g9vd79EGumzbNJdfweh6ZEhySYzNqkjH0a4d2FKmD83vP9HI7hu+9c9F3O05arZL+2ZoOTOW4RHYcL6t2FUQuwoiUWHtX2W16Ubp+7Dire7Bpn6GeujCXQi6RUXaqx5CNmC9LiVRaUXgfUiMiLVfuST3J4Gw15hNYjctCnlSg3oXUp8WIcWIpsRHWcB3YCilE5/2HfuooZjuNTlGXhfOU7e4qUa8RLtPGm6NxU4GL1kyEgvTZ8vWmRR27uxJfShzoXabBqgcFcTJ44/F5+eDi44f/oeDwozDo86uWZfi75u78HZ8vz7dfBgLfK1qpXrteZ1AJTpC/6rb85/NZYhPrSQ85jZDSM5b8v4SsO4cfrj7ib1EYl6sfAnIHaApKRGFyxOsBhT59Pi2exXlOABgTGO80BkpNh8hA1aPVHlk4d9DZcns2CtiphrNU6aKGtfiLS6mcYlNJO18eQDgGOumgKBsrmipMH/YYYuzY813Ry1UKGYHUItg82X6wFshIMaQX8iAR2HZuKhhU478jsDfYaB1EP31Sg5PfhE+ayx6orK5n4KZE/YqlrfQS4HUtu48mrFSx++ygVuQiQCvTxROULTSeSVgryuSuJmbebdmuNefkAdHk4qNdoi2ir/c7GG6+D7QDzPa0WGJWRox4w7sF9lsY8e8wLuXCToT6O7rpflVx1Rke54989Rw3tqjhODmsHbSoIgWBYzeD98GGK/CfkkGnp2BJTMMhBDX2EcumyE+Rrtm4KULavNPoRsN87qhdV5vzYpgTNLazNFgyvxwZM/6onERWq6VVW7D56P66JLBDbZorrFn7A+6mNJN2Vq5lrE9B5GlamUcz8/zdgQ== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ffcf2c18-e482-417d-708b-08db772bf737 X-MS-Exchange-CrossTenant-AuthSource: AM0PR04MB6452.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2023 16:31:31.9752 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZVPY/0B2djrLaqR2iROpazcwEuX3a+E7Is3ACY2Bo25TVn/L7LWIZuKn075AsFYwmunLiCeMye1amc8sJ/rk7g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR04MB7314 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org The driver implements a workaround for the fact that it doesn't have an IRQ source to tell it whether PTP frames are available through the extraction registers, for those frames to be processed and passed towards the network stack. That workaround is to configure the switch, through felix_hwtstamp_set() -> felix_update_trapping_destinations(), to create two copies of PTP packets: one sent over Ethernet to the DSA master, and one to be consumed through the aforementioned CPU extraction queue registers. The reason why we want PTP packets to be consumed through the CPU extraction registers in the first place is because we want to see their hardware RX timestamp. With tag_8021q, that is only visible that way, and it isn't visible with the copy of the packet that's transmitted over Ethernet. The problem with the workaround implementation is that it drops the packet received over Ethernet, in expectation of its copy being present in the CPU extraction registers. However, if felix_hwtstamp_set() hasn't run (aka PTP RX timestamping is disabled), the driver will drop the original PTP frame and there will be no copy of it in the CPU extraction registers. So, the network stack will simply not see any PTP frame. Look at the port's trapping configuration to see whether the driver has previously enabled the CPU extraction registers. If it hasn't, just don't RX timestamp the frame and let it be passed up the stack by DSA, which is perfectly fine. Fixes: 0a6f17c6ae21 ("net: dsa: tag_ocelot_8021q: add support for PTP timestamping") Signed-off-by: Vladimir Oltean --- v1->v2: distinguish between L2 and L4 PTP packets drivers/net/dsa/ocelot/felix.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c index 80861ac090ae..70c0e2b1936b 100644 --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c @@ -1725,6 +1725,18 @@ static bool felix_rxtstamp(struct dsa_switch *ds, int port, u32 tstamp_hi; u64 tstamp; + switch (type & PTP_CLASS_PMASK) { + case PTP_CLASS_L2: + if (!(ocelot->ports[port]->trap_proto & OCELOT_PROTO_PTP_L2)) + return false; + break; + case PTP_CLASS_IPV4: + case PTP_CLASS_IPV6: + if (!(ocelot->ports[port]->trap_proto & OCELOT_PROTO_PTP_L4)) + return false; + break; + } + /* If the "no XTR IRQ" workaround is in use, tell DSA to defer this skb * for RX timestamping. Then free it, and poll for its copy through * MMIO in the CPU port module, and inject that into the stack from