From patchwork Thu Jun 29 15:26:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13297108 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39144EB64DC for ; Thu, 29 Jun 2023 15:27:24 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.556910.869801 (Exim 4.92) (envelope-from ) id 1qEtY2-0001JK-Bv; Thu, 29 Jun 2023 15:27:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 556910.869801; Thu, 29 Jun 2023 15:27:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qEtY2-0001JC-88; Thu, 29 Jun 2023 15:27:06 +0000 Received: by outflank-mailman (input) for mailman id 556910; Thu, 29 Jun 2023 15:27:04 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qEtY0-0000oy-7V for xen-devel@lists.xenproject.org; Thu, 29 Jun 2023 15:27:04 +0000 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [2a00:1450:4864:20::62d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 63d5655e-1691-11ee-8611-37d641c3527e; Thu, 29 Jun 2023 17:26:59 +0200 (CEST) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-991f956fb5aso90980366b.0 for ; Thu, 29 Jun 2023 08:26:59 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id v11-20020a170906564b00b00992c4103cb5sm307727ejr.129.2023.06.29.08.26.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jun 2023 08:26:59 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 63d5655e-1691-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1688052419; x=1690644419; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3EWwSePGbgOG6UY76hDXOxd7acKLKdGC7PoIoBrzZDo=; b=JlSEVxkZwiGyQiUexPBvtX53E+gwluHtldrfzFeXh/3nHThOh/coT5DSmpfZuQC5o+ 6E6meTDvO7+6fFBxtWDT3OSXAzx0SzyiKNpboFjciaN0y/F9XRgE3NO0L7mUOgw02ej8 vHhTCOtPKb4CpxAx9pRLMd/5FrgxLwsgqzW9E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688052419; x=1690644419; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3EWwSePGbgOG6UY76hDXOxd7acKLKdGC7PoIoBrzZDo=; b=eggLBw0Y8tS/ondSSeaOOPMqrus8S7S0+TQBbTKWMKkfLcNu5NHPKV7WxIYCDHllfJ 4aXJezLsZcU00jyoKSb+96enooNw4/P6bvgVuUbiXVcqnKXUTiqa8j6a+8Y90zLSVX1g IqOAYODFVeeX/BQWCDEXU/g/wszqPBK3drKHulKWtigLL4j36KfylOyN0knYZ+vxACcc 3zNu8DKN9yeyc8qRdT9AoQgxc8sOSYhIQxOSi6TOD/sWjThsu4/T4okDcDHuGMtrJ6jI 8r/dzyg6FjEGs6tX5hjDy7NXR5+DHjiE6Kx5KJJc0VVHZSvWYBrWsdweWKoFt2L+159u rHEQ== X-Gm-Message-State: AC+VfDzArszms/4scbX8r8GI6MaOh5YEV0xbKc3JjTOUimaqCW9dFQ1I ik+aRJhMfFWh3+uAlwS/TGqzS4XJFFZN5rUlncY= X-Google-Smtp-Source: ACHHUZ4Ovlt5oS29GhdsnB2LHodJwMHMIoAaON3wMB8LDLBOql7BWiGNIREyPpS4qm8jlLUeH7y3Ag== X-Received: by 2002:a17:907:980e:b0:992:33ba:2eb4 with SMTP id ji14-20020a170907980e00b0099233ba2eb4mr6354747ejc.71.1688052419215; Thu, 29 Jun 2023 08:26:59 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v5 1/4] x86/microcode: Allow reading microcode revision even if it can't be updated Date: Thu, 29 Jun 2023 16:26:53 +0100 Message-Id: <20230629152656.12655-2-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230629152656.12655-1-alejandro.vallejo@cloud.com> References: <20230629152656.12655-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 microcode_update_one() currently assumes all microcode handlers are set or none are. That won't be the case in a future patch, as apply_microcode() may not be set while the others are. Hence, this patch allows reading the microcode revision even if updating it is unavailable. Signed-off-by: Alejandro Vallejo Reviewed-by: Jan Beulich Reviewed-by: Andrew Cooper --- xen/arch/x86/cpu/microcode/core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index c3fee62906..bec8b55db2 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -750,11 +750,12 @@ __initcall(microcode_init); /* Load a cached update to current cpu */ int microcode_update_one(void) { + if ( ucode_ops.collect_cpu_info ) + alternative_vcall(ucode_ops.collect_cpu_info); + if ( !ucode_ops.apply_microcode ) return -EOPNOTSUPP; - alternative_vcall(ucode_ops.collect_cpu_info); - return microcode_update_cpu(NULL); } From patchwork Thu Jun 29 15:26:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13297110 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B886EB64DD for ; Thu, 29 Jun 2023 15:27:30 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.556911.869807 (Exim 4.92) (envelope-from ) id 1qEtY2-0001Mt-Mp; Thu, 29 Jun 2023 15:27:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 556911.869807; Thu, 29 Jun 2023 15:27:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qEtY2-0001MY-H2; Thu, 29 Jun 2023 15:27:06 +0000 Received: by outflank-mailman (input) for mailman id 556911; Thu, 29 Jun 2023 15:27:04 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qEtY0-0000oy-EN for xen-devel@lists.xenproject.org; Thu, 29 Jun 2023 15:27:04 +0000 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [2a00:1450:4864:20::630]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 642da17a-1691-11ee-8611-37d641c3527e; Thu, 29 Jun 2023 17:27:00 +0200 (CEST) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-9920a6a6cb0so97175566b.3 for ; Thu, 29 Jun 2023 08:27:00 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id v11-20020a170906564b00b00992c4103cb5sm307727ejr.129.2023.06.29.08.26.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jun 2023 08:26:59 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 642da17a-1691-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1688052419; x=1690644419; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hW8flEGuUVEa8vCzcK1Csawi7P2txv/CQdLOaV7tNFk=; b=LsP4Q1/sJcGPff1nn5mAs1YGEsVCeeCyjCUXx5n6bjWd+Eh0bR2LM5JnGUcqytdUGi KrKd5hBm0rUMToba1+Sfjhxbm6rXSyW9LbXLetjOVy5q8dmYh/jNJDTKo6Pv8NNi8Z2E dp3Zw6t5KjFhRoWgWTROFn/UJSiPbK2w4N8ro= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688052419; x=1690644419; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hW8flEGuUVEa8vCzcK1Csawi7P2txv/CQdLOaV7tNFk=; b=I5ZIEF7ZyPNxOwYW017kcMf2FACPX/CkZ97nbggPQH6Df827hWyYtE/xzmBYfikAAl KNvzLvXzFxTnHGnfbmcOENpBfxJ6cT6ayPdC3nPJpL1nVqoop45S6VrVYIIcLkj7+gI+ feRRkko37T12kCd1y182vafW1KEVPWgyVkn4jRLTo4BMEN+7cNK/PZu3KJIXWQYoWfJg IQqqKpgEXIERo4Ze7Xo/HIHrw9pPIhvASetmM42iWvuOuZl5Kvtvkw3RcI2TtugNbdMc XGuJ1JVBb+1/AK2bznIOTX7B/c33rq7Kne7cEKYPgnTSi/XqTPRFS9fHz8Towom80qku DYcA== X-Gm-Message-State: AC+VfDzgu67rfrExAWKZjdXN68BThp/jDKD4QaqCwF+c+xc6LIfzJTa5 T3xP4Bhp+ORCgDyf8+crkhOIizirS55psSwZ5JU= X-Google-Smtp-Source: ACHHUZ6dPxjTgEK4ZylFXht3+Dygl3PdD/weoWIMQ8Q8+aOEnfqCLEZ/bEQC801no7kdb25MXeNfkA== X-Received: by 2002:a17:907:d0f:b0:975:942e:81e7 with SMTP id gn15-20020a1709070d0f00b00975942e81e7mr37765200ejc.37.1688052419824; Thu, 29 Jun 2023 08:26:59 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v5 2/4] x86/microcode: Ignore microcode loading interface for revision = -1 Date: Thu, 29 Jun 2023 16:26:54 +0100 Message-Id: <20230629152656.12655-3-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230629152656.12655-1-alejandro.vallejo@cloud.com> References: <20230629152656.12655-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 Some hypervisors report ~0 as the microcode revision to mean "don't issue microcode updates". Ignore the microcode loading interface in that case. Signed-off-by: Alejandro Vallejo Reviewed-by: Jan Beulich --- v5: * Style fix. Brace position. --- xen/arch/x86/cpu/microcode/core.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index bec8b55db2..b620e3bfa6 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -867,10 +867,22 @@ int __init early_microcode_init(unsigned long *module_map, return -ENODEV; } - microcode_grab_module(module_map, mbi); - ucode_ops.collect_cpu_info(); + /* + * Some hypervisors deliberately report a microcode revision of -1 to + * mean that they will not accept microcode updates. We take the hint + * and ignore the microcode interface in that case. + */ + if ( this_cpu(cpu_sig).rev == ~0 ) + { + printk(XENLOG_WARNING "Microcode loading disabled\n"); + ucode_ops.apply_microcode = NULL; + return -ENODEV; + } + + microcode_grab_module(module_map, mbi); + if ( ucode_mod.mod_end || ucode_blob.size ) rc = early_microcode_update_cpu(); From patchwork Thu Jun 29 15:26:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13297107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96FAAEB64DD for ; Thu, 29 Jun 2023 15:27:22 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.556908.869781 (Exim 4.92) (envelope-from ) id 1qEtXz-0000pC-Pp; Thu, 29 Jun 2023 15:27:03 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 556908.869781; Thu, 29 Jun 2023 15:27:03 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qEtXz-0000p5-MY; Thu, 29 Jun 2023 15:27:03 +0000 Received: by outflank-mailman (input) for mailman id 556908; Thu, 29 Jun 2023 15:27:02 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qEtXy-0000oz-LF for xen-devel@lists.xenproject.org; Thu, 29 Jun 2023 15:27:02 +0000 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [2a00:1450:4864:20::62e]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 649225a4-1691-11ee-b237-6b7b168915f2; Thu, 29 Jun 2023 17:27:00 +0200 (CEST) Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-98377c5d53eso96441266b.0 for ; Thu, 29 Jun 2023 08:27:00 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id v11-20020a170906564b00b00992c4103cb5sm307727ejr.129.2023.06.29.08.26.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jun 2023 08:27:00 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 649225a4-1691-11ee-b237-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1688052420; x=1690644420; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UiGulcFZszXEnWg5k92SUya80elYH7/hcO6zRbn6Dxs=; b=GB/HFta4uYcxg4dp/35Q9VmPzYqNQMLFv6wLOhRl1kM9K2zxWO9Pom55IGmswLsXPT 7ZhVGPStTU7403YJKkaAuwTW/JM5/YMpL/obPT0eFEyBFr4lScIPAqs/eLV795U0Mswy 9kCfZAkeVV0BQCuDVek2gdDG1C7ezuA9EgMZs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688052420; x=1690644420; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UiGulcFZszXEnWg5k92SUya80elYH7/hcO6zRbn6Dxs=; b=FLRhYqbn11Na8jdd88jGZ9vbvaca/04PMiBBmrVPKX7ljwN5jDpNYqZh7WDZozTnQu XoqB7layJMQGkb8f91XUQTYU0HOcMmhRWtU56dHLekmD0mggWJ9AXPi0b+5l2nYi+2qi /5IOiiFtdZB0yFQ+pdNemRvuUuH4LoL7qRNM8tUKFV+NbJQMs/PidnB3TSOCTcQVa9ry D5QuQDGFqDYO7LsIWRP46Fy7ID8di4vhocDkc3eeUD88B/XQ4QOz6dyypnJt3FatNklO mAQhm2sDbUzkxb6avDONk6o2+1OyM0g1ZgF3dApMTekSsikzDstFcdzjwPJBtO6zmMTS ykhA== X-Gm-Message-State: AC+VfDzXQey24hmKsHbtBvFchzS7oFxUTqE1TlHnlYqRqcYUuUxYiahC NgM90eR2i5TPv8HazvoOryDkcjwj4b4rsWNkKrs= X-Google-Smtp-Source: ACHHUZ4dqt9NKSpwm7oWRf4SgxZ2HOnbWbRJTj2ORo+3vH0rGavSnlSwWzNbfIADfgOQUkICg9FoWw== X-Received: by 2002:a17:907:7603:b0:991:c566:979 with SMTP id jx3-20020a170907760300b00991c5660979mr8425263ejc.36.1688052420417; Thu, 29 Jun 2023 08:27:00 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v5 3/4] x86: Read MSR_ARCH_CAPS immediately after early_microcode_init() Date: Thu, 29 Jun 2023 16:26:55 +0100 Message-Id: <20230629152656.12655-4-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230629152656.12655-1-alejandro.vallejo@cloud.com> References: <20230629152656.12655-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 Move MSR_ARCH_CAPS read code from tsx_init() to early_cpu_init(). Because microcode updates might make them that MSR to appear/have different values we also must reload it after a microcode update in early_microcode_init(). Signed-off-by: Alejandro Vallejo Reviewed-by: Jan Beulich --- v5: * Re-run early_cpu_init() after early_microcode_init() rather than reloading specific fields * Amended early_cpu_init() so it takes a `verbose` argument in order to skip printing the same information before and after early microcode updates --- xen/arch/x86/cpu/common.c | 23 +++++++++++++++-------- xen/arch/x86/cpu/microcode/core.c | 6 ++++++ xen/arch/x86/setup.c | 2 +- xen/arch/x86/tsx.c | 16 ++++------------ 4 files changed, 26 insertions(+), 21 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index cfcdaace12..a1be0aa4bd 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -303,7 +303,7 @@ static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb) WARNING: this function is only called on the BP. Don't add code here that is supposed to run on all CPUs. */ -void __init early_cpu_init(void) +void __init early_cpu_init(bool verbose) { struct cpuinfo_x86 *c = &boot_cpu_data; u32 eax, ebx, ecx, edx; @@ -324,9 +324,10 @@ void __init early_cpu_init(void) case X86_VENDOR_SHANGHAI: this_cpu = &shanghai_cpu_dev; break; case X86_VENDOR_HYGON: this_cpu = &hygon_cpu_dev; break; default: - printk(XENLOG_ERR - "Unrecognised or unsupported CPU vendor '%.12s'\n", - c->x86_vendor_id); + if (verbose) + printk(XENLOG_ERR + "Unrecognised or unsupported CPU vendor '%.12s'\n", + c->x86_vendor_id); } cpuid(0x00000001, &eax, &ebx, &ecx, &edx); @@ -340,10 +341,11 @@ void __init early_cpu_init(void) c->x86_capability[FEATURESET_1d] = edx; c->x86_capability[FEATURESET_1c] = ecx; - printk(XENLOG_INFO - "CPU Vendor: %s, Family %u (%#x), Model %u (%#x), Stepping %u (raw %08x)\n", - x86_cpuid_vendor_to_str(c->x86_vendor), c->x86, c->x86, - c->x86_model, c->x86_model, c->x86_mask, eax); + if (verbose) + printk(XENLOG_INFO + "CPU Vendor: %s, Family %u (%#x), Model %u (%#x), Stepping %u (raw %08x)\n", + x86_cpuid_vendor_to_str(boot_cpu_data->x86_vendor), c->x86, c->x86, + c->x86_model, c->x86_model, c->x86_mask, eax); if (c->cpuid_level >= 7) { uint32_t max_subleaf; @@ -352,6 +354,11 @@ void __init early_cpu_init(void) &c->x86_capability[FEATURESET_7c0], &c->x86_capability[FEATURESET_7d0]); + if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability)) + rdmsr(MSR_ARCH_CAPABILITIES, + c->x86_capability[FEATURESET_m10Al], + c->x86_capability[FEATURESET_m10Ah]); + if (max_subleaf >= 1) cpuid_count(7, 1, &eax, &ebx, &ecx, &c->x86_capability[FEATURESET_7d1]); diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index b620e3bfa6..98a5aebfe3 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -886,5 +886,11 @@ int __init early_microcode_init(unsigned long *module_map, if ( ucode_mod.mod_end || ucode_blob.size ) rc = early_microcode_update_cpu(); + /* + * MSR_ARCH_CAPS may have appeared after the microcode update. Reload + * boot_cpu_data if so because they are needed in tsx_init(). + */ + early_cpu_init(false); + return rc; } diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 74e3915a4d..bdf66e80ac 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -1211,7 +1211,7 @@ void __init noreturn __start_xen(unsigned long mbi_p) panic("Bootloader provided no memory information\n"); /* This must come before e820 code because it sets paddr_bits. */ - early_cpu_init(); + early_cpu_init(true); /* Choose shadow stack early, to set infrastructure up appropriately. */ if ( !boot_cpu_has(X86_FEATURE_CET_SS) ) diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c index 80c6f4cedd..50d8059f23 100644 --- a/xen/arch/x86/tsx.c +++ b/xen/arch/x86/tsx.c @@ -39,9 +39,10 @@ void tsx_init(void) static bool __read_mostly once; /* - * This function is first called between microcode being loaded, and CPUID - * being scanned generally. Read into boot_cpu_data.x86_capability[] for - * the cpu_has_* bits we care about using here. + * This function is first called between microcode being loaded, and + * CPUID being scanned generally. early_cpu_init() has already prepared + * the feature bits needed here. And early_microcode_init() has ensured + * they are not stale after the microcode update. */ if ( unlikely(!once) ) { @@ -49,15 +50,6 @@ void tsx_init(void) once = true; - if ( boot_cpu_data.cpuid_level >= 7 ) - boot_cpu_data.x86_capability[FEATURESET_7d0] - = cpuid_count_edx(7, 0); - - if ( cpu_has_arch_caps ) - rdmsr(MSR_ARCH_CAPABILITIES, - boot_cpu_data.x86_capability[FEATURESET_m10Al], - boot_cpu_data.x86_capability[FEATURESET_m10Ah]); - has_rtm_always_abort = cpu_has_rtm_always_abort; if ( cpu_has_tsx_ctrl && cpu_has_srbds_ctrl ) From patchwork Thu Jun 29 15:26:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13297109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4D90EB64D9 for ; Thu, 29 Jun 2023 15:27:25 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.556912.869813 (Exim 4.92) (envelope-from ) id 1qEtY3-0001UH-2c; Thu, 29 Jun 2023 15:27:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 556912.869813; Thu, 29 Jun 2023 15:27:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qEtY2-0001S4-Qw; Thu, 29 Jun 2023 15:27:06 +0000 Received: by outflank-mailman (input) for mailman id 556912; Thu, 29 Jun 2023 15:27:05 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qEtY1-0000oy-7c for xen-devel@lists.xenproject.org; Thu, 29 Jun 2023 15:27:05 +0000 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [2a00:1450:4864:20::62f]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 65180cfa-1691-11ee-8611-37d641c3527e; Thu, 29 Jun 2023 17:27:01 +0200 (CEST) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-992b66e5affso74265466b.3 for ; Thu, 29 Jun 2023 08:27:01 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id v11-20020a170906564b00b00992c4103cb5sm307727ejr.129.2023.06.29.08.27.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jun 2023 08:27:00 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 65180cfa-1691-11ee-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1688052421; x=1690644421; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G67gLa/o7/WHSN6dkAdpT425Jo9Uwtlq2X27eVNLdd8=; b=CnuuXj8PwDbeJspOFZNReQGrG/5s3fsRN7gJ8gusWs3LgYeWxowuGqE01VqqK5Pomk sPDbREl9Ktby9eErAH6DkCaGTcAdNwLLjVXDjMWlwAe7BSXKXC/+BjB/XMhqFHGzRkl/ //AbV59CxqU+scRdZkcKJdWsinQzgpf/YlXvU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688052421; x=1690644421; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G67gLa/o7/WHSN6dkAdpT425Jo9Uwtlq2X27eVNLdd8=; b=WGxKl0XHULH0/PIa6QRBp8LdZ0UPhCD7maR7mSuJpWDpGOmvCWrBkr1/7kjrsKE1Bf h6L7pIlmVnAgFGD5pj4lQmOPMzGgeZZSTg0Gn8j07TFAo3w9DTqZMB7fMfsdKnoi2OfT ZP1Ep4ylcJotxUHEfqcJGB0Btt14vmg3Gt3Bx5rMc1ria/wOjFtVhDzpkihhwB5DCeob LpdjLjDVsy3W4yxfoUQTnNLy6hLboMZ8Ptv/s5e3pnKHH38QEBlj7L38tBRRjzZYyxYp PFP2lhD9wtr1d/x+C9DFRzydJuAKlPqfTJvBwtJ4JjoIJVP72NQoqEmWZR0Gko0/TOba 1YKQ== X-Gm-Message-State: AC+VfDxbn4ZMflPsYoOOJTwgh6zFZ7tcIwO4E3USsuGXaUSefWUFQG1b KMY7SkUJBURpAn3u4AjsWkXz3wXsxBxUIjaoJkY= X-Google-Smtp-Source: ACHHUZ4KnEuLzL96joYK2MZR6qliLnOJDmS5URTcsPK4LfoteX6IGLCdTBNlEyaIivECeI2GcUeDzQ== X-Received: by 2002:a17:906:9381:b0:98e:37fe:691b with SMTP id l1-20020a170906938100b0098e37fe691bmr10225842ejx.34.1688052421260; Thu, 29 Jun 2023 08:27:01 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v5 4/4] x86/microcode: Disable microcode update handler if DIS_MCU_UPDATE is set Date: Thu, 29 Jun 2023 16:26:56 +0100 Message-Id: <20230629152656.12655-5-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230629152656.12655-1-alejandro.vallejo@cloud.com> References: <20230629152656.12655-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 If IA32_MSR_MCU_CONTROL exists then it's possible a CPU may be unable to perform microcode updates. This is controlled through the DIS_MCU_LOAD bit and is intended for baremetal clouds where the owner may not trust the tenant to choose the microcode version in use. If we notice that bit being set then simply disable the "apply_microcode" handler so we can't even try to perform update (as it's known to be silently dropped). While at it, remove the Intel family check, as microcode loading is supported on every Intel 64 CPU. Signed-off-by: Alejandro Vallejo Reviewed-by: Jan Beulich --- v5: * Removed __init on declaration * Minor style fix (2 spaces rather than 1 after "return") --- xen/arch/x86/cpu/microcode/core.c | 10 +++++++--- xen/arch/x86/cpu/microcode/intel.c | 13 +++++++++++++ xen/arch/x86/cpu/microcode/private.h | 7 +++++++ xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/include/asm/msr-index.h | 5 +++++ 5 files changed, 33 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index 98a5aebfe3..982b278c9e 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -847,17 +847,21 @@ int __init early_microcode_init(unsigned long *module_map, { const struct cpuinfo_x86 *c = &boot_cpu_data; int rc = 0; + bool can_load = false; switch ( c->x86_vendor ) { case X86_VENDOR_AMD: if ( c->x86 >= 0x10 ) + { ucode_ops = amd_ucode_ops; + can_load = true; + } break; case X86_VENDOR_INTEL: - if ( c->x86 >= 6 ) - ucode_ops = intel_ucode_ops; + ucode_ops = intel_ucode_ops; + can_load = intel_can_load_microcode(); break; } @@ -874,7 +878,7 @@ int __init early_microcode_init(unsigned long *module_map, * mean that they will not accept microcode updates. We take the hint * and ignore the microcode interface in that case. */ - if ( this_cpu(cpu_sig).rev == ~0 ) + if ( this_cpu(cpu_sig).rev == ~0 || !can_load ) { printk(XENLOG_WARNING "Microcode loading disabled\n"); ucode_ops.apply_microcode = NULL; diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcode/intel.c index 8d4d6574aa..060c529a6e 100644 --- a/xen/arch/x86/cpu/microcode/intel.c +++ b/xen/arch/x86/cpu/microcode/intel.c @@ -385,6 +385,19 @@ static struct microcode_patch *cf_check cpu_request_microcode( return patch; } +bool __init intel_can_load_microcode(void) +{ + uint64_t mcu_ctrl; + + if ( !cpu_has_mcu_ctrl ) + return true; + + rdmsrl(MSR_MCU_CONTROL, mcu_ctrl); + + /* If DIS_MCU_LOAD is set applying microcode updates won't work */ + return !(mcu_ctrl & MCU_CONTROL_DIS_MCU_LOAD); +} + const struct microcode_ops __initconst_cf_clobber intel_ucode_ops = { .cpu_request_microcode = cpu_request_microcode, .collect_cpu_info = collect_cpu_info, diff --git a/xen/arch/x86/cpu/microcode/private.h b/xen/arch/x86/cpu/microcode/private.h index 626aeb4d08..d80787205a 100644 --- a/xen/arch/x86/cpu/microcode/private.h +++ b/xen/arch/x86/cpu/microcode/private.h @@ -60,6 +60,13 @@ struct microcode_ops { const struct microcode_patch *new, const struct microcode_patch *old); }; +/** + * Checks whether we can perform microcode updates on this Intel system + * + * @return True iff the microcode update facilities are enabled + */ +bool intel_can_load_microcode(void); + extern const struct microcode_ops amd_ucode_ops, intel_ucode_ops; #endif /* ASM_X86_MICROCODE_PRIVATE_H */ diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index e2cb8f3cc7..608bc4dce0 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -192,6 +192,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_if_pschange_mc_no boot_cpu_has(X86_FEATURE_IF_PSCHANGE_MC_NO) #define cpu_has_tsx_ctrl boot_cpu_has(X86_FEATURE_TSX_CTRL) #define cpu_has_taa_no boot_cpu_has(X86_FEATURE_TAA_NO) +#define cpu_has_mcu_ctrl boot_cpu_has(X86_FEATURE_MCU_CTRL) #define cpu_has_fb_clear boot_cpu_has(X86_FEATURE_FB_CLEAR) #define cpu_has_rrsba boot_cpu_has(X86_FEATURE_RRSBA) diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 2749e433d2..5c1350b5f9 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -165,6 +165,11 @@ #define PASID_PASID_MASK 0x000fffff #define PASID_VALID (_AC(1, ULL) << 31) +#define MSR_MCU_CONTROL 0x00001406 +#define MCU_CONTROL_LOCK (_AC(1, ULL) << 0) +#define MCU_CONTROL_DIS_MCU_LOAD (_AC(1, ULL) << 1) +#define MCU_CONTROL_EN_SMM_BYPASS (_AC(1, ULL) << 2) + #define MSR_UARCH_MISC_CTRL 0x00001b01 #define UARCH_CTRL_DOITM (_AC(1, ULL) << 0)