From patchwork Fri Jun 30 03:55:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 13297552 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14F3FEB64DA for ; Fri, 30 Jun 2023 03:57:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qF5F3-0008JJ-4W; Thu, 29 Jun 2023 23:56:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qF5Ey-0008H8-CT; Thu, 29 Jun 2023 23:56:12 -0400 Received: from mail-oo1-xc2b.google.com ([2607:f8b0:4864:20::c2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qF5Ev-00023x-GR; Thu, 29 Jun 2023 23:56:12 -0400 Received: by mail-oo1-xc2b.google.com with SMTP id 006d021491bc7-5636426c1b3so875588eaf.1; Thu, 29 Jun 2023 20:56:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688097363; x=1690689363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:from:to:cc:subject:date :message-id:reply-to; bh=HdyqwSG21wTwZ4cu1DuC0qeGTIiHIj6/66NCJsv9PoQ=; b=sT/NCZkYPcd1I/coRu0C2DqPVBnmZzxjLSzhT5FBWAQCJ8j5u9TPg5wu/mUct1BWtH qVuUHQPgMmsF+n3YBmHlb1O+FKAQiKV9F7Ysar6rPXn7xMCJkFHWXYehl9g+zvNujmwY tsk2N26FB48ehWjs/sP14fLvzFsEkE85t6u5ec1KGTAcy7Lm2f9HWbbE+p3Hx0QmaxLq 4tj+Ij09+Jvrbra1YaT1UyHQtB5ACs01xpqCsQPNerLK+o3L9InGacHe30H4mRV+Cbi1 IXSss/Tf/0GsUWGt6RO/vC4LNGvX2FodT+fmfVt+fPqudx1mXe14QqYqapriIZN//dEN W5ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688097363; x=1690689363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=HdyqwSG21wTwZ4cu1DuC0qeGTIiHIj6/66NCJsv9PoQ=; b=gtu62ucTy0EEg5qsSY7pNsjC9jNgoX0RfeTf4K2sYttA+A0nbTsIHF+da6HTJ8tPYI 2K0XFLUPfHXaOQ5PrOAss8Rxkbv6B4eaca3XuL1BWQAANrLgFQJUXm8WZsY9vUrTNoZ+ BPApYDFb8yg1pqnwkZ5wIRYRvZCRRGkOu4bN2IFOd36vJGjAHJ0rl4pq6/b51lMNOKE0 ZjaXncD8dl+uw+12SvIF7nLBEbaCls7aRDrIb/WvcxV9sUkjKGn8lgKW2fni3L9GNBzu RmmHVym5irbLjn9cvULEu9EHJYXP/pJJ2NAiZvkm+lhm7IyOOIDbciYkOTm45GTiTXMi J8NQ== X-Gm-Message-State: ABy/qLaeItFOHX3VKFB6JOQzKfhrdvRxMIxTRYgMfz5SbcqrOL0IQmwY 49l2kZ9I0/Wwz5mVcCUJr0KwNlinoMY= X-Google-Smtp-Source: APBJJlHZmjdHfWVdoAk6IURdl1GZnplDdFdflhT0FUjd4ayk/8UoPEBzW9ojNKZsqPgCXaS05+J3vg== X-Received: by 2002:a05:6871:288:b0:1b0:4ee7:a753 with SMTP id i8-20020a056871028800b001b04ee7a753mr2345677oae.37.1688097363354; Thu, 29 Jun 2023 20:56:03 -0700 (PDT) Received: from voyager.lan ([45.124.203.15]) by smtp.gmail.com with ESMTPSA id 29-20020a17090a195d00b0025ef39c0f87sm10639290pjh.0.2023.06.29.20.56.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jun 2023 20:56:02 -0700 (PDT) From: Joel Stanley To: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Nicholas Piggin , =?utf-8?b?RnLDqWTDqXJpYyBCYXJyYXQ=?= Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 1/4] ppc/pnv: quad xscom callbacks are P9 specific Date: Fri, 30 Jun 2023 13:25:44 +0930 Message-Id: <20230630035547.80329-2-joel@jms.id.au> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230630035547.80329-1-joel@jms.id.au> References: <20230630035547.80329-1-joel@jms.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=joel.stan@gmail.com; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Rename the to include P9 in the name in preparation for adding P10 versions. Signed-off-by: Joel Stanley Reviewed-by: Cédric Le Goater --- hw/ppc/pnv_core.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 0bc3ad41c81c..0b1c3cccfebc 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -360,8 +360,8 @@ DEFINE_TYPES(pnv_core_infos) #define P9X_EX_NCU_SPEC_BAR 0x11010 -static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr, - unsigned int width) +static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr, + unsigned int width) { uint32_t offset = addr >> 3; uint64_t val = -1; @@ -379,8 +379,8 @@ static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr, return val; } -static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val, - unsigned int width) +static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int width) { uint32_t offset = addr >> 3; @@ -394,9 +394,9 @@ static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val, } } -static const MemoryRegionOps pnv_quad_xscom_ops = { - .read = pnv_quad_xscom_read, - .write = pnv_quad_xscom_write, +static const MemoryRegionOps pnv_quad_power9_xscom_ops = { + .read = pnv_quad_power9_xscom_read, + .write = pnv_quad_power9_xscom_write, .valid.min_access_size = 8, .valid.max_access_size = 8, .impl.min_access_size = 8, @@ -410,7 +410,8 @@ static void pnv_quad_realize(DeviceState *dev, Error **errp) char name[32]; snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id); - pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops, + pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), + &pnv_quad_power9_xscom_ops, eq, name, PNV9_XSCOM_EQ_SIZE); } From patchwork Fri Jun 30 03:55:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 13297551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0F85EB64D7 for ; Fri, 30 Jun 2023 03:57:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qF5F3-0008JT-9h; Thu, 29 Jun 2023 23:56:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qF5Ez-0008HG-2M; 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Thu, 29 Jun 2023 20:56:05 -0700 (PDT) From: Joel Stanley To: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Nicholas Piggin , =?utf-8?b?RnLDqWTDqXJpYyBCYXJyYXQ=?= Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 2/4] ppc/pnv: Subclass quad xscom callbacks Date: Fri, 30 Jun 2023 13:25:45 +0930 Message-Id: <20230630035547.80329-3-joel@jms.id.au> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230630035547.80329-1-joel@jms.id.au> References: <20230630035547.80329-1-joel@jms.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=joel.stan@gmail.com; helo=mail-ot1-x330.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Make the existing pnv_quad_xscom_read/write be P9 specific, in preparation for a different P10 callback. Signed-off-by: Joel Stanley Reviewed-by: Cédric Le Goater --- include/hw/ppc/pnv_core.h | 12 +++++++++++- hw/ppc/pnv.c | 11 +++++++---- hw/ppc/pnv_core.c | 36 ++++++++++++++++++++++++------------ 3 files changed, 42 insertions(+), 17 deletions(-) diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 3d75706e95da..ab3f6d6c2843 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -60,8 +60,18 @@ static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu) return (PnvCPUState *)cpu->machine_data; } +struct PnvQuadClass { + DeviceClass parent_class; + + const MemoryRegionOps *xscom_ops; +}; + #define TYPE_PNV_QUAD "powernv-cpu-quad" -OBJECT_DECLARE_SIMPLE_TYPE(PnvQuad, PNV_QUAD) + +#define PNV_QUAD_TYPE_SUFFIX "-" TYPE_PNV_QUAD +#define PNV_QUAD_TYPE_NAME(cpu_model) cpu_model PNV_QUAD_TYPE_SUFFIX + +OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD) struct PnvQuad { DeviceState parent_obj; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index fc083173f346..c77fdb6747a4 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1429,14 +1429,15 @@ static void pnv_chip_power9_instance_init(Object *obj) } static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, - PnvCore *pnv_core) + PnvCore *pnv_core, + const char *type) { char eq_name[32]; int core_id = CPU_CORE(pnv_core)->core_id; snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); object_initialize_child_with_props(OBJECT(chip), eq_name, eq, - sizeof(*eq), TYPE_PNV_QUAD, + sizeof(*eq), type, &error_fatal, NULL); object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); @@ -1454,7 +1455,8 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) for (i = 0; i < chip9->nr_quads; i++) { PnvQuad *eq = &chip9->quads[i]; - pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], + PNV_QUAD_TYPE_NAME("power9")); pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), &eq->xscom_regs); @@ -1666,7 +1668,8 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) for (i = 0; i < chip10->nr_quads; i++) { PnvQuad *eq = &chip10->quads[i]; - pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], + PNV_QUAD_TYPE_NAME("power9")); pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), &eq->xscom_regs); diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 0b1c3cccfebc..b9a57463aec4 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -407,11 +407,12 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = { static void pnv_quad_realize(DeviceState *dev, Error **errp) { PnvQuad *eq = PNV_QUAD(dev); + PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq); char name[32]; snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id); pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), - &pnv_quad_power9_xscom_ops, + pqc->xscom_ops, eq, name, PNV9_XSCOM_EQ_SIZE); } @@ -420,6 +421,13 @@ static Property pnv_quad_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static void pnv_quad_power9_class_init(ObjectClass *oc, void *data) +{ + PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); + + pqc->xscom_ops = &pnv_quad_power9_xscom_ops; +} + static void pnv_quad_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -429,16 +437,20 @@ static void pnv_quad_class_init(ObjectClass *oc, void *data) dc->user_creatable = false; } -static const TypeInfo pnv_quad_info = { - .name = TYPE_PNV_QUAD, - .parent = TYPE_DEVICE, - .instance_size = sizeof(PnvQuad), - .class_init = pnv_quad_class_init, +static const TypeInfo pnv_quad_infos[] = { + { + .name = TYPE_PNV_QUAD, + .parent = TYPE_DEVICE, + .instance_size = sizeof(PnvQuad), + .class_size = sizeof(PnvQuadClass), + .class_init = pnv_quad_class_init, + .abstract = true, + }, + { + .parent = TYPE_PNV_QUAD, + .name = PNV_QUAD_TYPE_NAME("power9"), + .class_init = pnv_quad_power9_class_init, + }, }; -static void pnv_core_register_types(void) -{ - type_register_static(&pnv_quad_info); -} - -type_init(pnv_core_register_types) +DEFINE_TYPES(pnv_quad_infos); From patchwork Fri Jun 30 03:55:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 13297550 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A41DEB64DA for ; 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Thu, 29 Jun 2023 20:56:09 -0700 (PDT) Received: from voyager.lan ([45.124.203.15]) by smtp.gmail.com with ESMTPSA id 29-20020a17090a195d00b0025ef39c0f87sm10639290pjh.0.2023.06.29.20.56.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jun 2023 20:56:09 -0700 (PDT) From: Joel Stanley To: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Nicholas Piggin , =?utf-8?b?RnLDqWTDqXJpYyBCYXJyYXQ=?= Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 3/4] ppc/pnv: Add P10 quad ops Date: Fri, 30 Jun 2023 13:25:46 +0930 Message-Id: <20230630035547.80329-4-joel@jms.id.au> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230630035547.80329-1-joel@jms.id.au> References: <20230630035547.80329-1-joel@jms.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::112a; envelope-from=joel.stan@gmail.com; helo=mail-yw1-x112a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add a PnvQuad class for the P10 powernv machine. No xscoms are implemented yet, but this allows them to be added. Signed-off-by: Joel Stanley Reviewed-by: Cédric Le Goater --- hw/ppc/pnv.c | 2 +- hw/ppc/pnv_core.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index c77fdb6747a4..5f25fe985ab2 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1669,7 +1669,7 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) PnvQuad *eq = &chip10->quads[i]; pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], - PNV_QUAD_TYPE_NAME("power9")); + PNV_QUAD_TYPE_NAME("power10")); pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), &eq->xscom_regs); diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index b9a57463aec4..7fff2fd9e298 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -404,6 +404,47 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = { .endianness = DEVICE_BIG_ENDIAN, }; +/* + * POWER10 Quads + */ + +static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, + unsigned int width) +{ + uint32_t offset = addr >> 3; + uint64_t val = -1; + + switch (offset) { + default: + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, + offset); + } + + return val; +} + +static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int width) +{ + uint32_t offset = addr >> 3; + + switch (offset) { + default: + qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, + offset); + } +} + +static const MemoryRegionOps pnv_quad_power10_xscom_ops = { + .read = pnv_quad_power10_xscom_read, + .write = pnv_quad_power10_xscom_write, + .valid.min_access_size = 8, + .valid.max_access_size = 8, + .impl.min_access_size = 8, + .impl.max_access_size = 8, + .endianness = DEVICE_BIG_ENDIAN, +}; + static void pnv_quad_realize(DeviceState *dev, Error **errp) { PnvQuad *eq = PNV_QUAD(dev); @@ -428,6 +469,13 @@ static void pnv_quad_power9_class_init(ObjectClass *oc, void *data) pqc->xscom_ops = &pnv_quad_power9_xscom_ops; } +static void pnv_quad_power10_class_init(ObjectClass *oc, void *data) +{ + PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); + + pqc->xscom_ops = &pnv_quad_power10_xscom_ops; +} + static void pnv_quad_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -451,6 +499,11 @@ static const TypeInfo pnv_quad_infos[] = { .name = PNV_QUAD_TYPE_NAME("power9"), .class_init = pnv_quad_power9_class_init, }, + { + .parent = TYPE_PNV_QUAD, + .name = PNV_QUAD_TYPE_NAME("power10"), + .class_init = pnv_quad_power10_class_init, + }, }; DEFINE_TYPES(pnv_quad_infos); From patchwork Fri Jun 30 03:55:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 13297549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0BD16EB64D7 for ; Fri, 30 Jun 2023 03:57:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qF5F4-0008K8-3M; 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Thu, 29 Jun 2023 20:56:12 -0700 (PDT) From: Joel Stanley To: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Nicholas Piggin , =?utf-8?b?RnLDqWTDqXJpYyBCYXJyYXQ=?= Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 4/4] ppc/pnv: Return zero for core thread state xscom Date: Fri, 30 Jun 2023 13:25:47 +0930 Message-Id: <20230630035547.80329-5-joel@jms.id.au> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230630035547.80329-1-joel@jms.id.au> References: <20230630035547.80329-1-joel@jms.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=joel.stan@gmail.com; helo=mail-ot1-x32e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Firmware now warns if booting in LPAR per core mode (PPC bit 62). So this warning doesn't trigger report the core thread state is 0. Signed-off-by: Joel Stanley Reviewed-by: Cédric Le Goater --- hw/ppc/pnv_core.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 7fff2fd9e298..98356d7f6538 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -116,6 +116,8 @@ static const MemoryRegionOps pnv_core_power8_xscom_ops = { #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a +#define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3 + static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, unsigned int width) { @@ -134,6 +136,9 @@ static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: val = 0x0; break; + case PNV9_XSCOM_EC_CORE_THREAD_STATE: + val = 0; + break; default: qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", addr); @@ -408,6 +413,8 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = { * POWER10 Quads */ +#define PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE 0x28412 + static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, unsigned int width) { @@ -415,6 +422,9 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, uint64_t val = -1; switch (offset) { + case PNV10_XSCOM_EC_PC_PMC_CORE_THREAD_STATE: + val = 0; + break; default: qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, offset);