From patchwork Fri Jun 30 12:25:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Johansson X-Patchwork-Id: 13298123 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE0F9EB64D7 for ; Fri, 30 Jun 2023 12:27:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qFDDA-0007rJ-Fc; Fri, 30 Jun 2023 08:26:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCU-0007gm-75 for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:11 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCR-0007nm-ST for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=5UiQBsLcq7OOik+VH0EC9Ewy2tKMDq/XqQGTeRNa8jE=; b=ZkGMikSoGf27sX2qKaji3k58po FpEhXKP7mQXkGhJnbhR6Qx38/N1zrXhhxJrzCHlsZoFjLFvokAC5MkMTZKnDLQUAWBAfSGaUZmLCo JqlKzu5Ze+MO8iXApr4x5Ovza9PljMC33v6axCfgD6RTb5khLWny+rVt9wAFNfSCAlJQ=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, peter.maydell@linaro.org, wangyanan55@huawei.com Subject: [PATCH 1/9] target/arm: Replace TARGET_PAGE_ENTRY_EXTRA Date: Fri, 30 Jun 2023 14:25:43 +0200 Message-ID: <20230630122551.21766-2-anjo@rev.ng> In-Reply-To: <20230630122551.21766-1-anjo@rev.ng> References: <20230630122551.21766-1-anjo@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson X-Patchwork-Original-From: Anton Johansson via From: Anton Johansson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Anton Johansson <97antjoh@gmail.com> TARGET_PAGE_ENTRY_EXTRA is a macro that allows guests to specify additional fields for caching with the full TLB entry. This macro is replaced with a union in CPUTLBEntryFull, thus making CPUTLB target-agnostic at the cost of slightly inflated CPUTLBEntryFull for non-arm guests. (arm is the only guest actually making use of this feature.) Signed-off-by: Anton Johansson --- include/exec/cpu-defs.h | 18 +++++++++++++++--- target/arm/cpu-param.h | 12 ------------ target/arm/ptw.c | 4 ++-- target/arm/tcg/mte_helper.c | 2 +- target/arm/tcg/sve_helper.c | 2 +- target/arm/tcg/tlb_helper.c | 4 ++-- target/arm/tcg/translate-a64.c | 2 +- 7 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index fb4c8d480f..0a600a312b 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -135,9 +135,21 @@ typedef struct CPUTLBEntryFull { * This may be used to cache items from the guest cpu * page tables for later use by the implementation. */ -#ifdef TARGET_PAGE_ENTRY_EXTRA - TARGET_PAGE_ENTRY_EXTRA -#endif + union { + /* + * Cache the attrs and shareability fields from the page table entry. + * + * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. + * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. + * For shareability and guarded, as in the SH and GP fields respectively + * of the VMSAv8-64 PTEs. + */ + struct { + uint8_t pte_attrs; + uint8_t shareability; + bool guarded; + } arm; + } extra; } CPUTLBEntryFull; #endif /* CONFIG_SOFTMMU */ diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index b3b35f7aa1..f9b462a98f 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -31,18 +31,6 @@ # define TARGET_PAGE_BITS_VARY # define TARGET_PAGE_BITS_MIN 10 -/* - * Cache the attrs and shareability fields from the page table entry. - * - * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. - * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. - * For shareability and guarded, as in the SH and GP fields respectively - * of the VMSAv8-64 PTEs. - */ -# define TARGET_PAGE_ENTRY_EXTRA \ - uint8_t pte_attrs; \ - uint8_t shareability; \ - bool guarded; #endif #endif diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6015121b99..22e02579cb 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -499,7 +499,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, } ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK); ptw->out_rw = full->prot & PAGE_WRITE; - pte_attrs = full->pte_attrs; + pte_attrs = full->extra.arm.pte_attrs; ptw->out_secure = full->attrs.secure; ptw->out_space = full->attrs.space; #else @@ -1933,7 +1933,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. */ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - result->f.guarded = extract64(attrs, 50, 1); /* GP */ + result->f.extra.arm.guarded = extract64(attrs, 50, 1); /* GP */ } } diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 9c64def081..be30c2bb51 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -124,7 +124,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, assert(!(flags & TLB_INVALID_MASK)); /* If the virtual page MemAttr != Tagged, access unchecked. */ - if (full->pte_attrs != 0xf0) { + if (full->extra.arm.pte_attrs != 0xf0) { return NULL; } diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 0097522470..996c04d3d9 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -5373,7 +5373,7 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env, info->tagged = (flags & PAGE_ANON) && (flags & PAGE_MTE); #else info->attrs = full->attrs; - info->tagged = full->pte_attrs == 0xf0; + info->tagged = full->extra.arm.pte_attrs == 0xf0; #endif /* Ensure that info->host[] is relative to addr, not addr + mem_off. */ diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index b22b2a4c6e..59bff8b452 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -334,8 +334,8 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, address &= TARGET_PAGE_MASK; } - res.f.pte_attrs = res.cacheattrs.attrs; - res.f.shareability = res.cacheattrs.shareability; + res.f.extra.arm.pte_attrs = res.cacheattrs.attrs; + res.f.extra.arm.shareability = res.cacheattrs.shareability; tlb_set_page_full(cs, mmu_idx, address, &res.f); return true; diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 3baab6aa60..0c5e275ac8 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -13763,7 +13763,7 @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s) false, &host, &full, 0); assert(!(flags & TLB_INVALID_MASK)); - return full->guarded; + return full->extra.arm.guarded; #endif } From patchwork Fri Jun 30 12:25:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Johansson X-Patchwork-Id: 13298127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10CB5EB64DC for ; Fri, 30 Jun 2023 12:28:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qFDDa-0008Eg-VE; Fri, 30 Jun 2023 08:27:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCV-0007h8-RZ for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:11 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCT-0007o0-1I for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=Y67geBb1lJLvblotNia/7q3c5euFb9gmKUzLtc5us6Q=; b=rucdkmc9j9upnmikoe6UMRJwT4 C0SAM2/RQiOGPmivfzmVfOLl24frt9P3uO3w/pcazCLdaVPURKaHSbJyrSrOmd5nEXrosatAf3oCn KcghAaGNhcsDyJD09zK4iXA5fwOaYZzm4gUdWNyZrcK2PW2i25BJFJgoc3OioR8vDWlU=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, peter.maydell@linaro.org, wangyanan55@huawei.com Subject: [PATCH 2/9] include: Move MMUAccessType to tlb-common.h Date: Fri, 30 Jun 2023 14:25:44 +0200 Message-ID: <20230630122551.21766-3-anjo@rev.ng> In-Reply-To: <20230630122551.21766-1-anjo@rev.ng> References: <20230630122551.21766-1-anjo@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson X-Patchwork-Original-From: Anton Johansson via From: Anton Johansson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This commit sets up and avoids circular inclusion in following commits. CPUTLB and friends will be moved from cpu-defs.h to tlb-common.h and depends on MMU_ACCESS_COUNT defined in hw/core/cpu.h, and hw/core/cpu.h will in turn need to include tlb-common.h once the CPUTLB field has been moved to CPUState. Signed-off-by: Anton Johansson --- include/exec/tlb-common.h | 7 ++++++- include/hw/core/cpu.h | 8 +------- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/include/exec/tlb-common.h b/include/exec/tlb-common.h index dc5a5faa0b..d1203354b4 100644 --- a/include/exec/tlb-common.h +++ b/include/exec/tlb-common.h @@ -19,7 +19,12 @@ #ifndef EXEC_TLB_COMMON_H #define EXEC_TLB_COMMON_H 1 -#define CPU_TLB_ENTRY_BITS 5 +typedef enum MMUAccessType { + MMU_DATA_LOAD = 0, + MMU_DATA_STORE = 1, + MMU_INST_FETCH = 2 +#define MMU_ACCESS_COUNT 3 +} MMUAccessType; /* Minimalized TLB entry for use by TCG fast path. */ typedef union CPUTLBEntry { diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b08f8b7079..c226d7263c 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -25,6 +25,7 @@ #include "exec/cpu-common.h" #include "exec/hwaddr.h" #include "exec/memattrs.h" +#include "exec/tlb-common.h" #include "qapi/qapi-types-run-state.h" #include "qemu/bitmap.h" #include "qemu/rcu_queue.h" @@ -80,13 +81,6 @@ DECLARE_CLASS_CHECKERS(CPUClass, CPU, typedef struct ArchCPU CpuInstanceType; \ OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME); -typedef enum MMUAccessType { - MMU_DATA_LOAD = 0, - MMU_DATA_STORE = 1, - MMU_INST_FETCH = 2 -#define MMU_ACCESS_COUNT 3 -} MMUAccessType; - typedef struct CPUWatchpoint CPUWatchpoint; /* see tcg-cpu-ops.h */ From patchwork Fri Jun 30 12:25:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Johansson X-Patchwork-Id: 13298130 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87715EB64DA for ; Fri, 30 Jun 2023 12:28:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qFDDi-0008TK-1B; Fri, 30 Jun 2023 08:27:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCW-0007i0-Sm for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:13 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCU-0007oL-HS for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=yH2lGkcD6MjDRFSd7GpsAC0EDoMhVP42/0i4heE8u68=; b=NpwZXfD1qghngVlSmz4BSGLA81 YsApToyXdzw+4A5+PRqHGEWrD7vtz40kv6ujH3H5xKmMaulthYd8NELJFYJDM+Xau2hIB5Gcph18v naiSnU/NWAfLuxkWQ9bZrQ99qUObMUgWwIZXGKLZW1BBNKoPPhuBMS292ZWkBST3/bek=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, peter.maydell@linaro.org, wangyanan55@huawei.com Subject: [PATCH 3/9] include/exec: Move CPUTLB and friends to tlb-common.h Date: Fri, 30 Jun 2023 14:25:45 +0200 Message-ID: <20230630122551.21766-4-anjo@rev.ng> In-Reply-To: <20230630122551.21766-1-anjo@rev.ng> References: <20230630122551.21766-1-anjo@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson X-Patchwork-Original-From: Anton Johansson via From: Anton Johansson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org CPUTLB is now target-agnostic and can be moved to a more suitable header. Signed-off-by: Anton Johansson --- include/exec/cpu-defs.h | 145 +------------------------------------ include/exec/tlb-common.h | 148 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 149 insertions(+), 144 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 0a600a312b..dff6c37f6b 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -25,10 +25,7 @@ #include "qemu/host-utils.h" #include "qemu/thread.h" -#ifndef CONFIG_USER_ONLY -#include "exec/hwaddr.h" -#endif -#include "exec/memattrs.h" +#include "exec/tlb-common.h" #include "hw/core/cpu.h" #include "cpu-param.h" @@ -54,17 +51,7 @@ #include "exec/target_long.h" -/* - * Fix the number of mmu modes to 16, which is also the maximum - * supported by the softmmu tlb api. - */ -#define NB_MMU_MODES 16 - #if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG) -#include "exec/tlb-common.h" - -/* use a fully associative victim tlb of 8 entries */ -#define CPU_VTLB_SIZE 8 #define CPU_TLB_DYN_MIN_BITS 6 #define CPU_TLB_DYN_DEFAULT_BITS 8 @@ -91,136 +78,6 @@ #endif /* CONFIG_SOFTMMU && CONFIG_TCG */ -#if defined(CONFIG_SOFTMMU) -/* - * The full TLB entry, which is not accessed by generated TCG code, - * so the layout is not as critical as that of CPUTLBEntry. This is - * also why we don't want to combine the two structs. - */ -typedef struct CPUTLBEntryFull { - /* - * @xlat_section contains: - * - in the lower TARGET_PAGE_BITS, a physical section number - * - with the lower TARGET_PAGE_BITS masked off, an offset which - * must be added to the virtual address to obtain: - * + the ram_addr_t of the target RAM (if the physical section - * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) - * + the offset within the target MemoryRegion (otherwise) - */ - hwaddr xlat_section; - - /* - * @phys_addr contains the physical address in the address space - * given by cpu_asidx_from_attrs(cpu, @attrs). - */ - hwaddr phys_addr; - - /* @attrs contains the memory transaction attributes for the page. */ - MemTxAttrs attrs; - - /* @prot contains the complete protections for the page. */ - uint8_t prot; - - /* @lg_page_size contains the log2 of the page size. */ - uint8_t lg_page_size; - - /* - * Additional tlb flags for use by the slow path. If non-zero, - * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. - */ - uint8_t slow_flags[MMU_ACCESS_COUNT]; - - /* - * Allow target-specific additions to this structure. - * This may be used to cache items from the guest cpu - * page tables for later use by the implementation. - */ - union { - /* - * Cache the attrs and shareability fields from the page table entry. - * - * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. - * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. - * For shareability and guarded, as in the SH and GP fields respectively - * of the VMSAv8-64 PTEs. - */ - struct { - uint8_t pte_attrs; - uint8_t shareability; - bool guarded; - } arm; - } extra; -} CPUTLBEntryFull; -#endif /* CONFIG_SOFTMMU */ - -#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG) -/* - * Data elements that are per MMU mode, minus the bits accessed by - * the TCG fast path. - */ -typedef struct CPUTLBDesc { - /* - * Describe a region covering all of the large pages allocated - * into the tlb. When any page within this region is flushed, - * we must flush the entire tlb. The region is matched if - * (addr & large_page_mask) == large_page_addr. - */ - vaddr large_page_addr; - vaddr large_page_mask; - /* host time (in ns) at the beginning of the time window */ - int64_t window_begin_ns; - /* maximum number of entries observed in the window */ - size_t window_max_entries; - size_t n_used_entries; - /* The next index to use in the tlb victim table. */ - size_t vindex; - /* The tlb victim table, in two parts. */ - CPUTLBEntry vtable[CPU_VTLB_SIZE]; - CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; - CPUTLBEntryFull *fulltlb; -} CPUTLBDesc; - -/* - * Data elements that are shared between all MMU modes. - */ -typedef struct CPUTLBCommon { - /* Serialize updates to f.table and d.vtable, and others as noted. */ - QemuSpin lock; - /* - * Within dirty, for each bit N, modifications have been made to - * mmu_idx N since the last time that mmu_idx was flushed. - * Protected by tlb_c.lock. - */ - uint16_t dirty; - /* - * Statistics. These are not lock protected, but are read and - * written atomically. This allows the monitor to print a snapshot - * of the stats without interfering with the cpu. - */ - size_t full_flush_count; - size_t part_flush_count; - size_t elide_flush_count; -} CPUTLBCommon; - -/* - * The entire softmmu tlb, for all MMU modes. - * The meaning of each of the MMU modes is defined in the target code. - * Since this is placed within CPUNegativeOffsetState, the smallest - * negative offsets are at the end of the struct. - */ - -typedef struct CPUTLB { - CPUTLBCommon c; - CPUTLBDesc d[NB_MMU_MODES]; - CPUTLBDescFast f[NB_MMU_MODES]; -} CPUTLB; - -#else - -typedef struct CPUTLB { } CPUTLB; - -#endif /* CONFIG_SOFTMMU && CONFIG_TCG */ - /* * This structure must be placed in ArchCPU immediately * before CPUArchState, as a field named "neg". diff --git a/include/exec/tlb-common.h b/include/exec/tlb-common.h index d1203354b4..838a1f0d2a 100644 --- a/include/exec/tlb-common.h +++ b/include/exec/tlb-common.h @@ -19,6 +19,17 @@ #ifndef EXEC_TLB_COMMON_H #define EXEC_TLB_COMMON_H 1 +#ifndef CONFIG_USER_ONLY +#include "exec/hwaddr.h" +#endif +#include "exec/memattrs.h" + +/* + * Fix the number of mmu modes to 16, which is also the maximum + * supported by the softmmu tlb api. + */ +#define NB_MMU_MODES 16 + typedef enum MMUAccessType { MMU_DATA_LOAD = 0, MMU_DATA_STORE = 1, @@ -26,6 +37,13 @@ typedef enum MMUAccessType { #define MMU_ACCESS_COUNT 3 } MMUAccessType; +#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG) +/* use a fully associative victim tlb of 8 entries */ +#define CPU_VTLB_SIZE 8 +#endif + +#define CPU_TLB_ENTRY_BITS 5 + /* Minimalized TLB entry for use by TCG fast path. */ typedef union CPUTLBEntry { struct { @@ -58,4 +76,134 @@ typedef struct CPUTLBDescFast { CPUTLBEntry *table; } CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); +#if defined(CONFIG_SOFTMMU) +/* + * The full TLB entry, which is not accessed by generated TCG code, + * so the layout is not as critical as that of CPUTLBEntry. This is + * also why we don't want to combine the two structs. + */ +typedef struct CPUTLBEntryFull { + /* + * @xlat_section contains: + * - in the lower TARGET_PAGE_BITS, a physical section number + * - with the lower TARGET_PAGE_BITS masked off, an offset which + * must be added to the virtual address to obtain: + * + the ram_addr_t of the target RAM (if the physical section + * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) + * + the offset within the target MemoryRegion (otherwise) + */ + hwaddr xlat_section; + + /* + * @phys_addr contains the physical address in the address space + * given by cpu_asidx_from_attrs(cpu, @attrs). + */ + hwaddr phys_addr; + + /* @attrs contains the memory transaction attributes for the page. */ + MemTxAttrs attrs; + + /* @prot contains the complete protections for the page. */ + uint8_t prot; + + /* @lg_page_size contains the log2 of the page size. */ + uint8_t lg_page_size; + + /* + * Additional tlb flags for use by the slow path. If non-zero, + * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. + */ + uint8_t slow_flags[MMU_ACCESS_COUNT]; + + /* + * Allow target-specific additions to this structure. + * This may be used to cache items from the guest cpu + * page tables for later use by the implementation. + */ + union { + /* + * Cache the attrs and shareability fields from the page table entry. + * + * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. + * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. + * For shareability and guarded, as in the SH and GP fields respectively + * of the VMSAv8-64 PTEs. + */ + struct { + uint8_t pte_attrs; + uint8_t shareability; + bool guarded; + } arm; + } extra; +} CPUTLBEntryFull; +#endif /* CONFIG_SOFTMMU */ + +#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG) +/* + * Data elements that are per MMU mode, minus the bits accessed by + * the TCG fast path. + */ +typedef struct CPUTLBDesc { + /* + * Describe a region covering all of the large pages allocated + * into the tlb. When any page within this region is flushed, + * we must flush the entire tlb. The region is matched if + * (addr & large_page_mask) == large_page_addr. + */ + vaddr large_page_addr; + vaddr large_page_mask; + /* host time (in ns) at the beginning of the time window */ + int64_t window_begin_ns; + /* maximum number of entries observed in the window */ + size_t window_max_entries; + size_t n_used_entries; + /* The next index to use in the tlb victim table. */ + size_t vindex; + /* The tlb victim table, in two parts. */ + CPUTLBEntry vtable[CPU_VTLB_SIZE]; + CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; + CPUTLBEntryFull *fulltlb; +} CPUTLBDesc; + +/* + * Data elements that are shared between all MMU modes. + */ +typedef struct CPUTLBCommon { + /* Serialize updates to f.table and d.vtable, and others as noted. */ + QemuSpin lock; + /* + * Within dirty, for each bit N, modifications have been made to + * mmu_idx N since the last time that mmu_idx was flushed. + * Protected by tlb_c.lock. + */ + uint16_t dirty; + /* + * Statistics. These are not lock protected, but are read and + * written atomically. This allows the monitor to print a snapshot + * of the stats without interfering with the cpu. + */ + size_t full_flush_count; + size_t part_flush_count; + size_t elide_flush_count; +} CPUTLBCommon; + +/* + * The entire softmmu tlb, for all MMU modes. + * The meaning of each of the MMU modes is defined in the target code. + * Since this is placed within CPUNegativeOffsetState, the smallest + * negative offsets are at the end of the struct. + */ + +typedef struct CPUTLB { + CPUTLBCommon c; + CPUTLBDesc d[NB_MMU_MODES]; + CPUTLBDescFast f[NB_MMU_MODES]; +} CPUTLB; + +#else + +typedef struct CPUTLB { } CPUTLB; + +#endif /* CONFIG_SOFTMMU && CONFIG_TCG */ + #endif /* EXEC_TLB_COMMON_H */ From patchwork Fri Jun 30 12:25:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Johansson X-Patchwork-Id: 13298128 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BED08EB64DA for ; Fri, 30 Jun 2023 12:28:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qFDDi-00006j-1v; Fri, 30 Jun 2023 08:27:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCY-0007iR-5W for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:14 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCW-0007oe-9O for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=h+/U6vaIirLj+baNgCStDASbBVDN+6AEOutgWw246LE=; b=oDEj5Gf3E+SXwekEnOmKo6xM5s uSRWI6Ff0KhBYWdSMvIT+8/nWxHw4esP6Ud9rRQXL6BXikDzcdwIVhooqdqczQyzn047ESKxXycQi pPB7DDI31I6CCg8SQekyki4XOm2pqNEpsD9dp+AzvLA8P5p/yLIASTq2HqZxR5WQjSKg=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, peter.maydell@linaro.org, wangyanan55@huawei.com Subject: [PATCH 4/9] include/hw: introduce CPU_MAX_NEGATIVE_ENV_OFFSET Date: Fri, 30 Jun 2023 14:25:46 +0200 Message-ID: <20230630122551.21766-5-anjo@rev.ng> In-Reply-To: <20230630122551.21766-1-anjo@rev.ng> References: <20230630122551.21766-1-anjo@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson X-Patchwork-Original-From: Anton Johansson via From: Anton Johansson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org For reasons related to code-generation quality, the offset of CPUTLBDescFast and IcountDecr from CPUArchState needs to fit within 11 bits of displacement (arm[32|64] and riscv addressing modes). This commit introduces a new constant to store the maximum allowed negative offset, so it can be statically asserted to hold later on. Signed-off-by: Anton Johansson --- include/hw/core/cpu.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c226d7263c..0377f74d48 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -259,6 +259,17 @@ struct qemu_work_item; #define CPU_UNSET_NUMA_NODE_ID -1 +/* + * For reasons related to code-generation quality the fast path + * CPUTLBDescFast array and IcountDecr fields need to be located within a + * small negative offset of CPUArchState. This requirement comes from + * host-specific addressing modes of arm[32|64] and riscv which uses 12- + * and 11 bits of displacement respectively. + */ +#define CPU_MIN_DISPLACEMENT_BITS 11 +#define CPU_MAX_NEGATIVE_ENV_OFFSET \ + (-(1 << CPU_MIN_DISPLACEMENT_BITS)) + /** * CPUState: * @cpu_index: CPU index (informative). From patchwork Fri Jun 30 12:25:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Johansson X-Patchwork-Id: 13298126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27C96EB64D7 for ; Fri, 30 Jun 2023 12:28:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qFDDx-0000Y2-Ed; Fri, 30 Jun 2023 08:27:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCZ-0007iU-88 for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:16 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCX-0007p8-G5 for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=YnXHlSzC1uMcM/XOI/M6CEk13EEb81H0iFHshDS1f6w=; b=ZDDm2DrCERZ9AWp1PhNiOCZdbU HPWRB6fJFYf4fcGy0BG1ek5twlIiyF1ce2PJ4DAv2imx54uNlBDhEWUDQoKBaHh6glNDRja6xQ0Wu d3n2qd5zALo3kCsMrvxeo/FioH4g6YSxGw/DcxqSmyXVhnjuVcIfzOtOYDC74GnDB+jA=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, peter.maydell@linaro.org, wangyanan55@huawei.com Subject: [PATCH 5/9] accel: Move CPUTLB to CPUState and assert offset Date: Fri, 30 Jun 2023 14:25:47 +0200 Message-ID: <20230630122551.21766-6-anjo@rev.ng> In-Reply-To: <20230630122551.21766-1-anjo@rev.ng> References: <20230630122551.21766-1-anjo@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson X-Patchwork-Original-From: Anton Johansson via From: Anton Johansson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org As CPUTLB is now target-agnostic it can be moved from CPUNegativeOffsetState to CPUState, and the negative offset from CPUArchState can instead be statically asserted to be greater than CPU_MAX_NEGATIVE_ENV_OFFSET. This also opens up the door for reducing the dependency of common code on CPUArchState. Signed-off-by: Anton Johansson --- include/exec/cpu-all.h | 2 +- include/exec/cpu-defs.h | 2 -- include/exec/tlb-common.h | 4 ++-- include/hw/core/cpu.h | 7 +++++++ accel/tcg/translate-all.c | 13 +++++++++++-- 5 files changed, 21 insertions(+), 7 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 8018ce783e..706daa49ec 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -453,7 +453,7 @@ static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) */ static inline CPUTLB *env_tlb(CPUArchState *env) { - return &env_neg(env)->tlb; + return &env_cpu(env)->tlb; } #endif /* CPU_ALL_H */ diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index dff6c37f6b..add0f3c541 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -25,7 +25,6 @@ #include "qemu/host-utils.h" #include "qemu/thread.h" -#include "exec/tlb-common.h" #include "hw/core/cpu.h" #include "cpu-param.h" @@ -83,7 +82,6 @@ * before CPUArchState, as a field named "neg". */ typedef struct CPUNegativeOffsetState { - CPUTLB tlb; IcountDecr icount_decr; } CPUNegativeOffsetState; diff --git a/include/exec/tlb-common.h b/include/exec/tlb-common.h index 838a1f0d2a..450c0156bf 100644 --- a/include/exec/tlb-common.h +++ b/include/exec/tlb-common.h @@ -190,8 +190,8 @@ typedef struct CPUTLBCommon { /* * The entire softmmu tlb, for all MMU modes. * The meaning of each of the MMU modes is defined in the target code. - * Since this is placed within CPUNegativeOffsetState, the smallest - * negative offsets are at the end of the struct. + * Since this is placed within CPUState, the smallest negative offsets + * are at the end of the struct. */ typedef struct CPUTLB { diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 0377f74d48..adf6158899 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -448,6 +448,13 @@ struct CPUState { /* track IOMMUs whose translations we've cached in the TCG TLB */ GArray *iommu_notifiers; + + /* + * The following fields needs to be within CPU_MAX_NEGATIVE_ENV_OFFSET of + * CPUArchState. As CPUArchState is assumed to follow CPUState in the + * ArchCPU struct these are placed last. This is checked statically. + */ + CPUTLB tlb; }; typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d3d4fbc1a4..5582aaf653 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -339,8 +339,17 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->page_bits = TARGET_PAGE_BITS; tcg_ctx->page_mask = TARGET_PAGE_MASK; tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS; - tcg_ctx->tlb_fast_offset = - (int)offsetof(ArchCPU, neg.tlb.f) - (int)offsetof(ArchCPU, env); + +#define TLB_FAST_OFFSET \ + ((int)offsetof(ArchCPU, parent_obj.tlb.f) - (int)offsetof(ArchCPU, env)) + + QEMU_BUILD_BUG_ON(TLB_FAST_OFFSET < CPU_MAX_NEGATIVE_ENV_OFFSET || + TLB_FAST_OFFSET > 0); + + tcg_ctx->tlb_fast_offset = TLB_FAST_OFFSET; + +#undef TLB_FAST_OFFSET + #endif tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS; #ifdef TCG_GUEST_DEFAULT_MO From patchwork Fri Jun 30 12:25:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Johansson X-Patchwork-Id: 13298122 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21C16EB64D7 for ; Fri, 30 Jun 2023 12:26:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qFDCl-0007m3-M5; Fri, 30 Jun 2023 08:26:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCW-0007i1-TI for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:13 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCU-0007pU-9n for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=p9Wxsfez663U0a0n8CU8dQHR0dYItJ/VYkumGeyDKcU=; b=JExO3pRuptB/w+SY4eivhhy+fA WmMe6m/moQO/X+qtr7Tvytwlzbq5HEq6s8ckd6FRxxtpxaIQjLaPYQAkwUTHm0p9HCoJPLnWtpS+c t74e6XRJauzx0iH375yWZBHCuwB5kEEsVN2qTOHk3qAKSBp4g4lE4njtxiqduCKdafkg=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, peter.maydell@linaro.org, wangyanan55@huawei.com Subject: [PATCH 6/9] Move IcountDecr to CPUState and assert offset Date: Fri, 30 Jun 2023 14:25:48 +0200 Message-ID: <20230630122551.21766-7-anjo@rev.ng> In-Reply-To: <20230630122551.21766-1-anjo@rev.ng> References: <20230630122551.21766-1-anjo@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson X-Patchwork-Original-From: Anton Johansson via From: Anton Johansson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Instead of using CPUNegativeOffsetState to ensure that negative offset between IcountDecr and CPUArchState is small enough, it can be statically asserted to be greater than CPU_MAX_NEGATIVE_ENV_OFFSET. Additionally, moving IcountDecr to CPUState allows for reducing the dependency of common code on CPUArchState (in the future). Signed-off-by: Anton Johansson --- include/exec/cpu-all.h | 2 +- include/exec/cpu-defs.h | 1 - include/exec/exec-all.h | 2 +- include/hw/core/cpu.h | 1 + accel/tcg/cpu-exec.c | 14 +++++++------- accel/tcg/tcg-accel-ops-icount.c | 6 +++--- accel/tcg/tcg-accel-ops.c | 2 +- accel/tcg/translate-all.c | 6 +++--- accel/tcg/translator.c | 15 +++++++++++---- softmmu/icount.c | 2 +- 10 files changed, 29 insertions(+), 22 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 706daa49ec..a31df11770 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -396,7 +396,7 @@ void tcg_exec_unrealizefn(CPUState *cpu); static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) { cpu->parent_obj.env_ptr = &cpu->env; - cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr; + cpu->parent_obj.icount_decr_ptr = &cpu->parent_obj.icount_decr; } /** diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index add0f3c541..429d9525f7 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -82,7 +82,6 @@ * before CPUArchState, as a field named "neg". */ typedef struct CPUNegativeOffsetState { - IcountDecr icount_decr; } CPUNegativeOffsetState; #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 200c27eadf..3bc4e34909 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -71,7 +71,7 @@ G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); */ static inline bool cpu_loop_exit_requested(CPUState *cpu) { - return (int32_t)qatomic_read(&cpu_neg(cpu)->icount_decr.u32) < 0; + return (int32_t)qatomic_read(&cpu->icount_decr.u32) < 0; } #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index adf6158899..c2e78b5fa9 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -455,6 +455,7 @@ struct CPUState { * ArchCPU struct these are placed last. This is checked statically. */ CPUTLB tlb; + IcountDecr icount_decr; }; typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ba1890a373..0a49b6fd7e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -73,7 +73,7 @@ static void align_clocks(SyncClocks *sc, CPUState *cpu) return; } - cpu_icount = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low; + cpu_icount = cpu->icount_extra + cpu->icount_decr.u16.low; sc->diff_clk += icount_to_ns(sc->last_cpu_icount - cpu_icount); sc->last_cpu_icount = cpu_icount; @@ -124,7 +124,7 @@ static void init_delay_params(SyncClocks *sc, CPUState *cpu) sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT); sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock; sc->last_cpu_icount - = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low; + = cpu->icount_extra + cpu->icount_decr.u16.low; if (sc->diff_clk < max_delay) { max_delay = sc->diff_clk; } @@ -689,7 +689,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) if (cpu->exception_index < 0) { #ifndef CONFIG_USER_ONLY if (replay_has_exception() - && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0) { + && cpu->icount_decr.u16.low + cpu->icount_extra == 0) { /* Execute just one insn to trigger exception pending in the log */ cpu->cflags_next_tb = (curr_cflags(cpu) & ~CF_USE_ICOUNT) | CF_NOIRQ | 1; @@ -779,7 +779,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, * Ensure zeroing happens before reading cpu->exit_request or * cpu->interrupt_request (see also smp_wmb in cpu_exit()) */ - qatomic_set_mb(&cpu_neg(cpu)->icount_decr.u16.high, 0); + qatomic_set_mb(&cpu->icount_decr.u16.high, 0); if (unlikely(qatomic_read(&cpu->interrupt_request))) { int interrupt_request; @@ -870,7 +870,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, if (unlikely(qatomic_read(&cpu->exit_request)) || (icount_enabled() && (cpu->cflags_next_tb == -1 || cpu->cflags_next_tb & CF_USE_ICOUNT) - && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0)) { + && cpu->icount_decr.u16.low + cpu->icount_extra == 0)) { qatomic_set(&cpu->exit_request, 0); if (cpu->exception_index == -1) { cpu->exception_index = EXCP_INTERRUPT; @@ -895,7 +895,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, } *last_tb = NULL; - insns_left = qatomic_read(&cpu_neg(cpu)->icount_decr.u32); + insns_left = qatomic_read(&cpu->icount_decr.u32); if (insns_left < 0) { /* Something asked us to stop executing chained TBs; just * continue round the main loop. Whatever requested the exit @@ -914,7 +914,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, icount_update(cpu); /* Refill decrementer and continue execution. */ insns_left = MIN(0xffff, cpu->icount_budget); - cpu_neg(cpu)->icount_decr.u16.low = insns_left; + cpu->icount_decr.u16.low = insns_left; cpu->icount_extra = cpu->icount_budget - insns_left; /* diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c index 3d2cfbbc97..1bb31fed2c 100644 --- a/accel/tcg/tcg-accel-ops-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -111,14 +111,14 @@ void icount_prepare_for_run(CPUState *cpu, int64_t cpu_budget) * each vCPU execution. However u16.high can be raised * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt */ - g_assert(cpu_neg(cpu)->icount_decr.u16.low == 0); + g_assert(cpu->icount_decr.u16.low == 0); g_assert(cpu->icount_extra == 0); replay_mutex_lock(); cpu->icount_budget = MIN(icount_get_limit(), cpu_budget); insns_left = MIN(0xffff, cpu->icount_budget); - cpu_neg(cpu)->icount_decr.u16.low = insns_left; + cpu->icount_decr.u16.low = insns_left; cpu->icount_extra = cpu->icount_budget - insns_left; if (cpu->icount_budget == 0) { @@ -138,7 +138,7 @@ void icount_process_data(CPUState *cpu) icount_update(cpu); /* Reset the counters */ - cpu_neg(cpu)->icount_decr.u16.low = 0; + cpu->icount_decr.u16.low = 0; cpu->icount_extra = 0; cpu->icount_budget = 0; diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 3973591508..1b957eb37b 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -91,7 +91,7 @@ void tcg_handle_interrupt(CPUState *cpu, int mask) if (!qemu_cpu_is_self(cpu)) { qemu_cpu_kick(cpu); } else { - qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); + qatomic_set(&cpu->icount_decr.u16.high, -1); } } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 5582aaf653..6069f6b8ba 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -214,7 +214,7 @@ void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, * Reset the cycle counter to the start of the block and * shift if to the number of actually executed instructions. */ - cpu_neg(cpu)->icount_decr.u16.low += insns_left; + cpu->icount_decr.u16.low += insns_left; } cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data); @@ -598,7 +598,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) cc = CPU_GET_CLASS(cpu); if (cc->tcg_ops->io_recompile_replay_branch && cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) { - cpu_neg(cpu)->icount_decr.u16.low++; + cpu->icount_decr.u16.low++; n = 2; } @@ -754,7 +754,7 @@ void cpu_interrupt(CPUState *cpu, int mask) { g_assert(qemu_mutex_iothread_locked()); cpu->interrupt_request |= mask; - qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); + qatomic_set(&cpu->icount_decr.u16.high, -1); } #endif /* CONFIG_USER_ONLY */ diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 0fd9efceba..7eba58137d 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -52,9 +52,16 @@ static TCGOp *gen_tb_start(uint32_t cflags) TCGv_i32 count = tcg_temp_new_i32(); TCGOp *icount_start_insn = NULL; - tcg_gen_ld_i32(count, cpu_env, - offsetof(ArchCPU, neg.icount_decr.u32) - - offsetof(ArchCPU, env)); +#define ICOUNT_DECR_OFFSET \ + ((int)offsetof(ArchCPU, parent_obj.icount_decr.u32) - \ + (int)offsetof(ArchCPU, env)) + + QEMU_BUILD_BUG_ON(ICOUNT_DECR_OFFSET < CPU_MAX_NEGATIVE_ENV_OFFSET || + ICOUNT_DECR_OFFSET > 0); + + tcg_gen_ld_i32(count, cpu_env, ICOUNT_DECR_OFFSET); + +#undef ICOUNT_DECR_OFFSET if (cflags & CF_USE_ICOUNT) { /* @@ -82,7 +89,7 @@ static TCGOp *gen_tb_start(uint32_t cflags) if (cflags & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, cpu_env, - offsetof(ArchCPU, neg.icount_decr.u16.low) - + offsetof(ArchCPU, parent_obj.icount_decr.u16.low) - offsetof(ArchCPU, env)); /* * cpu->can_do_io is cleared automatically here at the beginning of diff --git a/softmmu/icount.c b/softmmu/icount.c index a5cef9c60a..344af5fc3c 100644 --- a/softmmu/icount.c +++ b/softmmu/icount.c @@ -75,7 +75,7 @@ static void icount_enable_adaptive(void) static int64_t icount_get_executed(CPUState *cpu) { return (cpu->icount_budget - - (cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra)); + (cpu->icount_decr.u16.low + cpu->icount_extra)); } /* From patchwork Fri Jun 30 12:25:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Johansson X-Patchwork-Id: 13298124 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C47DDEB64D7 for ; Fri, 30 Jun 2023 12:27:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qFDDg-0008MV-4Y; Fri, 30 Jun 2023 08:27:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCX-0007i2-2w for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:13 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCV-0007pr-IP for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:12 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=dwQUCZ//6Pj5r8b81wBKPOFHu5aGZ8pFCXigGFaACsU=; b=vJZvHkRBUNoOrIQ0BTQzXqybGo /ja6twQKVrT1SHTVULbie1nvFl8ajzfQfxcA1xzuPN3PL0OBPtiw6SHqpQsxthWHzz4xWd42Cfm2r YexURsgQwJ7FjlISSIL8Kk41nhFTQfqO2C9doPZjGtKpdElkGo+xL8XPbIRxbB74Z1A0=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, peter.maydell@linaro.org, wangyanan55@huawei.com Subject: [PATCH 7/9] include/exec: Remove [cpu|env]_neg() functions Date: Fri, 30 Jun 2023 14:25:49 +0200 Message-ID: <20230630122551.21766-8-anjo@rev.ng> In-Reply-To: <20230630122551.21766-1-anjo@rev.ng> References: <20230630122551.21766-1-anjo@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson X-Patchwork-Original-From: Anton Johansson via From: Anton Johansson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org These functions are no longer used to access CPUTLB or IcountDecr and can be safely removed. Signed-off-by: Anton Johansson --- include/exec/cpu-all.h | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index a31df11770..fee0e7df73 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -421,30 +421,6 @@ static inline CPUState *env_cpu(CPUArchState *env) return &env_archcpu(env)->parent_obj; } -/** - * env_neg(env) - * @env: The architecture environment - * - * Return the CPUNegativeOffsetState associated with the environment. - */ -static inline CPUNegativeOffsetState *env_neg(CPUArchState *env) -{ - ArchCPU *arch_cpu = container_of(env, ArchCPU, env); - return &arch_cpu->neg; -} - -/** - * cpu_neg(cpu) - * @cpu: The generic CPUState - * - * Return the CPUNegativeOffsetState associated with the cpu. - */ -static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) -{ - ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj); - return &arch_cpu->neg; -} - /** * env_tlb(env) * @env: The architecture environment From patchwork Fri Jun 30 12:25:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Johansson X-Patchwork-Id: 13298125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25114EB64DA for ; Fri, 30 Jun 2023 12:27:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qFDDn-0000No-82; Fri, 30 Jun 2023 08:27:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCY-0007iT-Q0 for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:16 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCW-0007qF-By for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=eYAzleHckNSL2bhGy1XrBY7Nysuvs5N/7DTht7w9SGk=; b=WUbd5P61Hug52BM8cT/nkPTY1y fOrdYO2ayszQQHHqdOw9Ra6h7+ltW2gmsyx7awK44AGWbfKQ5j4C1n2fiCnShBC9xEjeJIyreVbEg +VYP6QHo2lefuMODPOPM11G8ThgOtglpHPOw6MUKmXImpz+o84FJO4vOMWxUveoTr+VY=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, peter.maydell@linaro.org, wangyanan55@huawei.com Subject: [PATCH 8/9] target: Remove CPUNegativeOffsetState field from ArchCPU Date: Fri, 30 Jun 2023 14:25:50 +0200 Message-ID: <20230630122551.21766-9-anjo@rev.ng> In-Reply-To: <20230630122551.21766-1-anjo@rev.ng> References: <20230630122551.21766-1-anjo@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson X-Patchwork-Original-From: Anton Johansson via From: Anton Johansson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All fields in CPUNegativeOffsetState have been moved to CPUState. Signed-off-by: Anton Johansson --- target/alpha/cpu.h | 1 - target/arm/cpu.h | 1 - target/avr/cpu.h | 1 - target/cris/cpu.h | 1 - target/hexagon/cpu.h | 1 - target/hppa/cpu.h | 1 - target/i386/cpu.h | 1 - target/loongarch/cpu.h | 1 - target/m68k/cpu.h | 1 - target/microblaze/cpu.h | 1 - target/mips/cpu.h | 3 +-- target/nios2/cpu.h | 1 - target/openrisc/cpu.h | 1 - target/ppc/cpu.h | 1 - target/riscv/cpu.h | 1 - target/rx/cpu.h | 1 - target/s390x/cpu.h | 1 - target/sh4/cpu.h | 1 - target/sparc/cpu.h | 1 - target/tricore/cpu.h | 1 - target/xtensa/cpu.h | 3 +-- 21 files changed, 2 insertions(+), 23 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index fcd20bfd3a..2e4b7cfc53 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -263,7 +263,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUAlphaState env; /* This alarm doesn't exist in real hardware; we wish it did. */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4d6c0f95d5..7bced90c34 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -856,7 +856,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUARMState env; /* Coprocessor information */ diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 7225174668..4ce22d8e4f 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -148,7 +148,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUAVRState env; }; diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 8e37c6e50d..676b8e93ca 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -178,7 +178,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUCRISState env; }; diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index daef5c3f00..b2de6e1d5d 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -141,7 +141,6 @@ struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUHexagonState env; bool lldb_compat; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7373177b55..b36de8f431 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -219,7 +219,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUHPPAState env; QEMUTimer *alarm_timer; }; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 2c9b0d2ebc..3bc215dc5d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1889,7 +1889,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUX86State env; VMChangeStateEntry *vmsentry; diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index ed04027af1..87529c93bf 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -367,7 +367,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPULoongArchState env; QEMUTimer timer; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index cf70282717..20afb0c94d 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -168,7 +168,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUM68KState env; }; diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index a7b040abd4..baf7d979f6 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -352,7 +352,6 @@ struct ArchCPU { bool ns_axi_dc; bool ns_axi_ic; - CPUNegativeOffsetState neg; CPUMBState env; MicroBlazeCPUConfig cfg; }; diff --git a/target/mips/cpu.h b/target/mips/cpu.h index a3bc646976..d118170a62 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1177,9 +1177,8 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - Clock *clock; - CPUNegativeOffsetState neg; CPUMIPSState env; + Clock *clock; }; diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 477a3161fd..70b6377a4f 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -218,7 +218,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUNios2State env; bool diverr_present; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 92c38f54c2..e823858e40 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -305,7 +305,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUOpenRISCState env; }; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index af12c93ebc..c480a1b37f 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1311,7 +1311,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUPPCState env; int vcpu_id; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7adb8706ac..4b9e0f818e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -383,7 +383,6 @@ struct ArchCPU { /* < private > */ CPUState parent_obj; /* < public > */ - CPUNegativeOffsetState neg; CPURISCVState env; char *dyn_csr_xml; diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 7f03ffcfed..f66754eb8a 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -111,7 +111,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPURXState env; }; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index eb5b65b7d3..7592ad53a8 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -168,7 +168,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUS390XState env; S390CPUModel *model; /* needed for live migration */ diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 1399d3840f..f75a235973 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -208,7 +208,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUSH4State env; }; diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 95d2d0da71..9385228a96 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -561,7 +561,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUSPARCState env; }; diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index a50b91cc36..7a48077485 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -192,7 +192,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; CPUTriCoreState env; }; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 87fe992ba6..c6bbef1e5d 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -560,9 +560,8 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ - Clock *clock; - CPUNegativeOffsetState neg; CPUXtensaState env; + Clock *clock; }; From patchwork Fri Jun 30 12:25:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Johansson X-Patchwork-Id: 13298129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4ADA0EB64DC for ; Fri, 30 Jun 2023 12:28:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qFDDm-0000Gt-4R; Fri, 30 Jun 2023 08:27:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCZ-0007iV-9K for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:16 -0400 Received: from rev.ng ([5.9.113.41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFDCX-0007qs-Qq for qemu-devel@nongnu.org; Fri, 30 Jun 2023 08:26:15 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=ZtbhIMnz+9QtgLUafG9TXdTCWqge4fH2sv7NJSgMmiQ=; b=kB2JTb1+enUetGnyy8ly/V/t7u Fo7avBUhxHTW05v7sO5nxDIrVhl/+r9ZcvkpYCdLC1X3fsOVxW1ax823HSlKbq5tecOiI9ZPFkUrm 1M4ygzWeKZpFFer6H40jUSETxrdYuyvEWieNC2zTQI7YZC/3paXzDf2JOpuncb6Tb0Qo=; To: qemu-devel@nongnu.org Cc: ale@rev.ng, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, philmd@linaro.org, marcel.apfelbaum@gmail.com, peter.maydell@linaro.org, wangyanan55@huawei.com Subject: [PATCH 9/9] include/exec: Remove CPUNegativeOffsetState Date: Fri, 30 Jun 2023 14:25:51 +0200 Message-ID: <20230630122551.21766-10-anjo@rev.ng> In-Reply-To: <20230630122551.21766-1-anjo@rev.ng> References: <20230630122551.21766-1-anjo@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson X-Patchwork-Original-From: Anton Johansson via From: Anton Johansson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Anton Johansson --- include/exec/cpu-defs.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 429d9525f7..e5125abc07 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -77,11 +77,4 @@ #endif /* CONFIG_SOFTMMU && CONFIG_TCG */ -/* - * This structure must be placed in ArchCPU immediately - * before CPUArchState, as a field named "neg". - */ -typedef struct CPUNegativeOffsetState { -} CPUNegativeOffsetState; - #endif