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Due to byte counters will count for any event configured, it will overflow more often. And if byte counters overflow that related counters would stop since they share the COUNTER_CNTL. We can speed up cycle counter overflow frequency by setting counter parameter (CP) field of cycle counter. In this way, we can avoid stop counting byte counters when interrupt didn't come and the byte counters can be fetched or updated from each cycle counter overflow interrupt. Signed-off-by: Xu Yang --- drivers/perf/fsl_imx8_ddr_perf.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 5222ba1e79d0..cc7693f49950 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -28,6 +28,8 @@ #define CNTL_CLEAR_MASK 0xFFFFFFFD #define CNTL_OVER_MASK 0xFFFFFFFE +#define CNTL_CP_SHIFT 16 +#define CNTL_CP_MASK (0xFF << CNTL_CP_SHIFT) #define CNTL_CSV_SHIFT 24 #define CNTL_CSV_MASK (0xFFU << CNTL_CSV_SHIFT) @@ -427,6 +429,20 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, writel(0, pmu->base + reg); val = CNTL_EN | CNTL_CLEAR; val |= FIELD_PREP(CNTL_CSV_MASK, config); + + /* + * Workaround for i.MX8MP: + * Common counters and byte counters share the same COUNTER_CNTL, + * and byte counters could overflow before cycle counter. Need set + * counter parameter(CP) of cycle counter to give it initial value + * which can speed up cycle counter overflow frequency. + */ + if ((pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) == + DDR_CAP_AXI_ID_FILTER_ENHANCED) { + if (counter == EVENT_CYCLES_COUNTER) + val |= FIELD_PREP(CNTL_CP_MASK, 0xf0); + } + writel(val, pmu->base + reg); } else { /* Disable counter */ From patchwork Wed Jul 5 10:48:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yang X-Patchwork-Id: 13301947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 814AAEB64DA for ; Wed, 5 Jul 2023 10:45:28 +0000 (UTC) DKIM-Signature: v=1; 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Wed, 5 Jul 2023 10:44:40 +0000 From: Xu Yang To: Frank.li@nxp.com Cc: will@kernel.org, mark.rutland@arm.com, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, xu.yang_2@nxp.com Subject: [PATCH 2/3] perf/imx_ddr: adjust counter result after read cycle counter Date: Wed, 5 Jul 2023 18:48:14 +0800 Message-Id: <20230705104815.511400-2-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230705104815.511400-1-xu.yang_2@nxp.com> References: <20230705104815.511400-1-xu.yang_2@nxp.com> X-ClientProxiedBy: SG3P274CA0004.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:be::16) To DB7PR04MB4505.eurprd04.prod.outlook.com (2603:10a6:5:39::26) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB7PR04MB4505:EE_|AM9PR04MB8698:EE_ X-MS-Office365-Filtering-Correlation-Id: b52de69c-6294-4c5f-9292-08db7d44d56f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 34iANjeiHKVKcuQTRYFDM9uz52EsoREugy6t3DO07uqWST+9sjFql9dGXihQDhcuI+Cp781lf9QizB0VWD6ZQs8NyhAKvaaapyWa5dlN7IusAzulGcGbAM7IpZlK27l8eJ8xJ1ntzLtfUftEq8508SZNkDEOsTEgYtwWzxmyNr1rGXMZkkZP7xsCkJ+Y4I0I+N01wRO0h12hZdiuITTkZtaoZqinsKFkOKmseScCPypwrY0fplBfxrcjvvAlsQXhAWfX0rPG0CCRJ8N7BigB8JdLIzf/5gNIjC4eT4VOER3y3trz87rGILA1ZEVfyKqikhdcvMI75TMO3DwGly16mZ5y3FIqYQhyFtA6NgQvGrQdZsK9jkr8IWIgZDsM5fa5pRwZmU+4F05o2NamVRfqAx9yXSkQruyVO2zPCYbxzFSMnxQDwMTr13tznnNBpdeKOkHIIhH2KagVCuROZYh5mDq4rkp/vl2PkSTFxa3VO9cWsqLVBl9xd+zjdKwOBERb5VkhCeUAQCgp1ffKh9gX94hHF19pmxA2Hhh8CEUsDN5DnuU973UQ677NIO9Rsbd6RVVxVzikzu92ji4bYP5V6cKIpR5Ppq1NsenAngbWy18= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DB7PR04MB4505.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(4636009)(396003)(39860400002)(376002)(366004)(346002)(136003)(451199021)(38100700002)(38350700002)(66476007)(66556008)(4326008)(6636002)(66946007)(2616005)(186003)(86362001)(6486002)(52116002)(6666004)(36756003)(6512007)(26005)(6506007)(478600001)(37006003)(1076003)(34206002)(8936002)(8676002)(4744005)(5660300002)(316002)(2906002)(41300700001)(83380400001);DIR:OUT;SFP:1101; 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We need to remove the base from the result too. Therefore, we could get precise result from cycle counter. Signed-off-by: Xu Yang --- drivers/perf/fsl_imx8_ddr_perf.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index cc7693f49950..4e6cbfc48429 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -482,6 +482,13 @@ static void ddr_perf_event_update(struct perf_event *event) int ret; new_raw_count = ddr_perf_read_counter(pmu, counter); + /* Workaround for i.MXMP */ + if ((pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) == + DDR_CAP_AXI_ID_FILTER_ENHANCED) { + if (counter == EVENT_CYCLES_COUNTER) + new_raw_count -= 0xF0000000; + } + local64_add(new_raw_count, &event->count); /* From patchwork Wed Jul 5 10:48:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yang X-Patchwork-Id: 13301948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5EBF3EB64DA for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: K6RFWzhlXe+tLw+vwwHxNmSQRZURIxLnOOdfek0AwPoMG1ONSQ0JefTkgUS7QCDKQsnUnDYlxVfcBkVSFm9QxKjpQIHVIECQHPa207qnDOg8BZ/H5nyYjFAuD8/huTmfftAFATaKlU2cJQZuyLQ4hMQUEdgHGeOlPvxKtlQz0FyHxKJ71CBHttBUThnOjMreF8kKFJyIgUktbtEeUDG382z1+p+LvI2wKz+qaeQ8LYT0Cb2P2ATPcyhwCvgxzgdadOmEYxaecmQNhLv4A7POIlL4/7tozvMBpdb9vWYYhJYjqtbGh7SZls4ebIWHMOIJ6sl6EvrfahemOC5+egq2O/KWdJA0nG3ERNfTf1ZSLPk13IYvsHBMRiOUSShVh+MbaQ6FD7L2YL4sfe+JqVYZy9fHx69f6b0MmxDOxgrovHf27Pynz7EkdlH5uPAnudShGULhZMwz86N8g5JKqS8Ma3N4mAxAjqGSEXsSVS1qknr4GBfXW0Eq99rlxpUIZw8cqotsJydOeAt7SzQI39VpCG7QyVutgiyZeZN0WSwb7bMInGl7xtEtQ5C+TSVZ6UwFhCLPtePdi8MSvZ0qK3UQCAKJuBJInt9lPdcwquCPhtcEe6EgEsvbs/GLi4Sg0OfpkbKrNj4kMIZTtpK+DEjzySrAhjFWjASHJ0xom1iOjnyc7udFV78TsaumrdV2bLWP917CHbHSdbeR7tPf/4Glxiu1U96gu9WcgooQ1b1gXITp5NZ91LpiKHNXk4ow4bb3hGSFmQd+GSqrZu3JEgYgdnQwX8UZPGi8tCbUc1odrJmm/93wKr2cgCTfmmhuXGyhLFxgT/rzjd88zct8dHn5rBrUmJ1rHBO/Z5AMrvsa5IG4Ys8JFX19KIj8jA2vbQW/mnEMW/iZ2Kp76ZApDEoXwy621WdK6KANJqpnJzDMBSCSv+dm1kwcl/mSYNiAMDNL/SCB5xxrP05z2CbRr8k6WH15yvq3BrdzQ5o5cZEtJQJozEXIH8hj1PeMSX0PyakAP9uyH7tyVwUMmzJUV/wQrruiSCRGKqbthyHlLDgwdbnapSOYZJ2AJZ0XVxW31Rt4uGhuc7tTQDUMpZgUtcbsYuvseootsplyyATaErDWjKsZNsRXwI4TNkxbAchD48ALF+COx0LgXrIOx4+oPN9kGxSn6zRYgzy6gNoJix5fs3MIImHKpMQvj72Zb4KfbfeWE3D65c2VRiyVagdEfq2MCVQt4Pp4Zkf/inn3B80xOyAp84CdOQBe/GBDvwIujhuHxmBH5pjLJPnjCVNNrjbs8jhzsYEH61Zygr1pgBgtHBRp4ATfaiqVrk5eelES6EoGOgoId9dIbAW/D8U/PSEvg7DvNbtrGajkp4j67it1w5iqltPFiJaLtfivcwyo6ozJcb0lsZkyByVK90460Cnm/O7+5gSeH3bvTFaz2G1C/zWC4PeAdlNM2CFd3Ds/yrHm2tPt1fluIQv4RpZftMDAT+fGYfG+pjOiU8V9MD+zzMFvrURQ0fOm4w+GDPDTIR2P6fRzLtC65Jd0V95zMhbOZDWBzNamKi32cp9MNCNUfKTRIs0KydBjVqGFwglulUu/ X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: dd4e6359-cbd2-4bc2-abc2-08db7d44d779 X-MS-Exchange-CrossTenant-AuthSource: DB7PR04MB4505.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2023 10:44:43.2078 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: w9IDEuNs/vPjGcpZ/W0LnrMh8d3Jtl7RdUbuudz2AodSnCTt3T3QkgfbtotjtGOslG+/4Wi0HsNp8MYN/Syjmw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR04MB8698 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230705_034450_527568_37C552EC X-CRM114-Status: GOOD ( 13.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In current driver, counter0 will be enabled after ddr_perf_pmu_enable() is called even though none of the 4 counters are used. This will cause counter0 continue to count until ddr_perf_pmu_disabled() is called. If pmu is not disabled all the time, the pmu interrupt will be asserted from time to time due to counter0 will overflow and irq handler will clear it. It's not an expected behavior. This patch will not enable counter0 if none of 4 counters are used. Fixes: 9a66d36cc7ac ("drivers/perf: imx_ddr: Add DDR performance counter support to perf") Signed-off-by: Xu Yang --- drivers/perf/fsl_imx8_ddr_perf.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 4e6cbfc48429..f7c832611713 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -591,7 +591,9 @@ static void ddr_perf_pmu_enable(struct pmu *pmu) struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); /* enable cycle counter if cycle is not active event list */ - if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL) + if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL && + (ddr_pmu->events[0] || ddr_pmu->events[1] || + ddr_pmu->events[2] || ddr_pmu->events[3])) ddr_perf_counter_enable(ddr_pmu, EVENT_CYCLES_ID, EVENT_CYCLES_COUNTER, @@ -602,7 +604,9 @@ static void ddr_perf_pmu_disable(struct pmu *pmu) { struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); - if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL) + if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL && + (ddr_pmu->events[0] || ddr_pmu->events[1] || + ddr_pmu->events[2] || ddr_pmu->events[3])) ddr_perf_counter_enable(ddr_pmu, EVENT_CYCLES_ID, EVENT_CYCLES_COUNTER,