From patchwork Mon Jul 10 21:13:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 13307675 X-Patchwork-Delegate: kuba@kernel.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E34FD154B2 for ; Mon, 10 Jul 2023 21:13:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0084AC433C8; Mon, 10 Jul 2023 21:13:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689023612; bh=SNGuXVhNbivoJOCwUC7uHYjtrHDLc0B9i+ZJR9cwZpU=; h=From:To:Cc:Subject:Date:From; b=EwUyesZZeyufHpoNx9N/EUT74OlHUjWDIOWBlNSte/ul2Z3Vdl2i5Z7SNCsnJq3C4 Ic5EyQRcXdwt9qaGZVuLrvvnftBcLPSBdB/fF4e5pjKzhfbGOrV25IK8sKXOL0i9AG t3+SkSZJCdrhqDYUHrkamzr1e7vS9XW2IIRISAIRAJxiloSH3D+Q8t4J/MenejQiuT 3J8mRF+qXL8BfiFUBO0/R/DweffdeLsC963zB52/IqjWr3pTZHsboRLmR/h0PeZ4pZ LWdoNcu/YliyDoiwVY3ahtzCgMtmMaNwRt8W+VhGBMTYtxQfylq+5kK4psArZ7NXQQ ZIDqjd5ObSdnA== From: Dinh Nguyen To: netdev@vger.kernel.org Cc: dinguyen@kernel.org, kuba@kernel.org, davem@davemloft.net, edumazet@google.com, joabreu@synopsys.com, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowskii+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/2] arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb" Date: Mon, 10 Jul 2023 16:13:12 -0500 Message-Id: <20230710211313.567761-1-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The "stmmaceth-ocp" reset line on the SoCFPGA stmmac ethernet driver is the same as the "abh" reset on a standard stmmac ethernet. commit ("843f603762a5 dt-bindings: net: snps,dwmac: Add 'ahb' reset/reset-name") documented the second reset signal as 'ahb' instead of 'stmmaceth-ocp'. Change the reset-names of the SoCFPGA DWMAC driver to 'ahb'. This also fixes the dtbs_check warning: ethernet@ff802000: reset-names:1: 'ahb' was expected Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 6 +++--- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 6 +++--- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 72c55e5187ca..f36063c57c7f 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -440,7 +440,7 @@ gmac0: ethernet@ff800000 { clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -460,7 +460,7 @@ gmac1: ethernet@ff802000 { clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -480,7 +480,7 @@ gmac2: ethernet@ff804000 { clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 1c846f13539c..439497ab967d 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -153,7 +153,7 @@ gmac0: ethernet@ff800000 { interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; @@ -171,7 +171,7 @@ gmac1: ethernet@ff802000 { interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; @@ -189,7 +189,7 @@ gmac2: ethernet@ff804000 { interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index fc047aef4911..d3adb6a130ae 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -158,7 +158,7 @@ gmac0: ethernet@ff800000 { interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; @@ -176,7 +176,7 @@ gmac1: ethernet@ff802000 { interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; @@ -194,7 +194,7 @@ gmac2: ethernet@ff804000 { interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; From patchwork Mon Jul 10 21:13:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 13307676 X-Patchwork-Delegate: kuba@kernel.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DAAF156D7 for ; Mon, 10 Jul 2023 21:13:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DD4A4C433C7; Mon, 10 Jul 2023 21:13:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689023614; bh=WRBYobPoSiX9Bs9tPTqxJ6CgeX9ttbxvGsZ4Eo0kj2w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X2gHDp89fMENCKrtuZPoAtfzhJqofBFRw0Ja2rYcaHjyIzvUqJepLHftRWejhTCi7 7mYjL4x6/UKqtObX8vFne7UyeUsxwmH9kMiLaiytuLcU7SAD6A57bGjjRAnm/zkCYV E5AiIDdcwHh9/neDAvVdKZRjWYv+bOyr5fzq2HnsrYfz53nBesSsTtOeppxEcP7I92 NEL/SmFm7I9lIC2pAqQHbLZLV1bpcxXBi9Me1fhbWTCzZ4Lg5gipR+H4hloN67vUFa elazlXFWW9NRXMqfdunTtuoUv49POvb4WBCrslzIUAMM8IfyFf6XhPZFDERn3ZHBOK kAZ7DFE7et2gA== From: Dinh Nguyen To: netdev@vger.kernel.org Cc: dinguyen@kernel.org, kuba@kernel.org, davem@davemloft.net, edumazet@google.com, joabreu@synopsys.com, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowskii+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/2] net: dwmac_socfpga: use the standard "ahb" reset Date: Mon, 10 Jul 2023 16:13:13 -0500 Message-Id: <20230710211313.567761-2-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230710211313.567761-1-dinguyen@kernel.org> References: <20230710211313.567761-1-dinguyen@kernel.org> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org The "stmmaceth-ocp" reset line of stmmac controller on the SoCFPGA platform is essentially the "ahb" reset on the standard stmmac controller. Because of commit ("e67f325e9cd6 net: stmmac: explicitly deassert GMAC_AHB_RESET") adds the support for getting the 'ahb' reset, the SoCFPGA dwmac driver no longer need to get the stmmaceth-ocp reset. Signed-off-by: Dinh Nguyen --- .../ethernet/stmicro/stmmac/dwmac-socfpga.c | 20 ++++++------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 6267bcb60206..a4b8b86129f4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -52,7 +52,7 @@ struct socfpga_dwmac { struct device *dev; struct regmap *sys_mgr_base_addr; struct reset_control *stmmac_rst; - struct reset_control *stmmac_ocp_rst; + struct reset_control *stmmac_ahb_rst; void __iomem *splitter_base; void __iomem *tse_pcs_base; void __iomem *sgmii_adapter_base; @@ -290,7 +290,7 @@ static int socfpga_gen5_set_phy_mode(struct socfpga_dwmac *dwmac) val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; /* Assert reset to the enet controller before changing the phy mode */ - reset_control_assert(dwmac->stmmac_ocp_rst); + reset_control_assert(dwmac->stmmac_ahb_rst); reset_control_assert(dwmac->stmmac_rst); regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); @@ -319,7 +319,7 @@ static int socfpga_gen5_set_phy_mode(struct socfpga_dwmac *dwmac) /* Deassert reset for the phy configuration to be sampled by * the enet controller, and operation to start in requested mode */ - reset_control_deassert(dwmac->stmmac_ocp_rst); + reset_control_deassert(dwmac->stmmac_ahb_rst); reset_control_deassert(dwmac->stmmac_rst); if (phymode == PHY_INTERFACE_MODE_SGMII) socfpga_sgmii_config(dwmac, true); @@ -346,7 +346,7 @@ static int socfpga_gen10_set_phy_mode(struct socfpga_dwmac *dwmac) val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; /* Assert reset to the enet controller before changing the phy mode */ - reset_control_assert(dwmac->stmmac_ocp_rst); + reset_control_assert(dwmac->stmmac_ahb_rst); reset_control_assert(dwmac->stmmac_rst); regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); @@ -372,7 +372,7 @@ static int socfpga_gen10_set_phy_mode(struct socfpga_dwmac *dwmac) /* Deassert reset for the phy configuration to be sampled by * the enet controller, and operation to start in requested mode */ - reset_control_deassert(dwmac->stmmac_ocp_rst); + reset_control_deassert(dwmac->stmmac_ahb_rst); reset_control_deassert(dwmac->stmmac_rst); if (phymode == PHY_INTERFACE_MODE_SGMII) socfpga_sgmii_config(dwmac, true); @@ -410,15 +410,6 @@ static int socfpga_dwmac_probe(struct platform_device *pdev) goto err_remove_config_dt; } - dwmac->stmmac_ocp_rst = devm_reset_control_get_optional(dev, "stmmaceth-ocp"); - if (IS_ERR(dwmac->stmmac_ocp_rst)) { - ret = PTR_ERR(dwmac->stmmac_ocp_rst); - dev_err(dev, "error getting reset control of ocp %d\n", ret); - goto err_remove_config_dt; - } - - reset_control_deassert(dwmac->stmmac_ocp_rst); - ret = socfpga_dwmac_parse_data(dwmac, dev); if (ret) { dev_err(dev, "Unable to parse OF data\n"); @@ -441,6 +432,7 @@ static int socfpga_dwmac_probe(struct platform_device *pdev) * the driver later. */ dwmac->stmmac_rst = stpriv->plat->stmmac_rst; + dwmac->stmmac_ahb_rst = stpriv->plat->stmmac_ahb_rst; ret = ops->set_phy_mode(dwmac); if (ret)