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Wysocki" , Bjorn Helgaas CC: , , Len Brown , , Mario Limonciello , Mika Westerberg Subject: [PATCH v7 1/2] PCI: Refactor pci_bridge_d3_possible() Date: Mon, 10 Jul 2023 19:53:24 -0500 Message-ID: <20230711005325.1499-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230711005325.1499-1-mario.limonciello@amd.com> References: <20230711005325.1499-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT091:EE_|PH7PR12MB9065:EE_ X-MS-Office365-Filtering-Correlation-Id: 2806e301-b4b2-4407-b758-08db81af8301 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nLJlllrtw+PoIBVOvL9gtXpSwYwqAt3yS0CZpBnDotDU5UJRTnX5Xr0SJO172f5mzZWH7qQ/x4swdaalzEmmlC/EMlhxeLji4t3v9V3sgXZgm+iKMQ7ObChJvxq01jf76JkhdfReUO2VVMqd3Ij3zv9iWo4zTSGzZlpEFT9lIpwpTm3TwZk4gL/7096YP72w0n7qc/NHQojqcMYAVI3M9fww++b09zfnhYDWM0rh9q7K0HJZx69vyHX3NSyKnckPmVIAzJAJATmU/R8NdLvo1BKbVIvjF/Kf1OIMjw0aMGqNT29G++IMFdNS6wdXAxD0x5n1g909dyhgDA7LA4cB+FMtxeXH1u6pI2d3iHFXBujcXNacA1Avm5IWBvzyi3CDIEAMbQaCu3zz7WM9IdAEGqLkEViRZ/WhvbxAd7EIQjMJ5FULPgXfUd2zM2db2D1RqL0La8eGkDfjoO90QuaGYyUfKzrJazeFZbWX/2pZUfW5k2ksNKJ2tarde9MhSI7p9TljiVvlbhtQp+Ym6ZMBUjRy+DZksiEJsrQ6QFhDKeezJTfn8k5TGGvXj782yRd4ukIfbGLSpAo/NvEy9OsIA2AflaDSxrbTOrsx03jjeb3nJ9y1zkqf8P8V2Uo0+imYCOsuOcmJeIvOEyX/FCpclx8El19yyQSDJbKiAg1hgGTP/5LzADyQHW7Vwq2Nx9oNx3kW/T3V//Eo9tnPi66DBfK5lnYMWAHcB4ML90BWLbdkwv230y3sjOA4nYOdpGyAgtJeUEH27Erk2bVSZBj18Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(136003)(376002)(396003)(39860400002)(451199021)(46966006)(40470700004)(36840700001)(82310400005)(86362001)(82740400003)(40460700003)(40480700001)(36756003)(7696005)(110136005)(54906003)(70586007)(70206006)(81166007)(356005)(478600001)(36860700001)(26005)(1076003)(186003)(2616005)(16526019)(44832011)(316002)(2906002)(5660300002)(8936002)(8676002)(426003)(336012)(83380400001)(4326008)(41300700001)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jul 2023 01:38:21.8526 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2806e301-b4b2-4407-b758-08db81af8301 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT091.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9065 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org All of the cases handled by pci_bridge_d3_possible() are specific to these branches: ``` case PCI_EXP_TYPE_ROOT_PORT: case PCI_EXP_TYPE_UPSTREAM: case PCI_EXP_TYPE_DOWNSTREAM: ``` Drop a level of indentation by returning false in the default case instead. No intended functional changes. Acked-by: Rafael J. Wysocki Reviewed-by: Mika Westerberg Signed-off-by: Mario Limonciello --- drivers/pci/pci.c | 68 +++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 60230da957e0c..f916fd76eba79 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3004,48 +3004,48 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge) case PCI_EXP_TYPE_ROOT_PORT: case PCI_EXP_TYPE_UPSTREAM: case PCI_EXP_TYPE_DOWNSTREAM: - if (pci_bridge_d3_disable) - return false; + break; + default: + return false; + } - /* - * Hotplug ports handled by firmware in System Management Mode - * may not be put into D3 by the OS (Thunderbolt on non-Macs). - */ - if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) - return false; + if (pci_bridge_d3_disable) + return false; - if (pci_bridge_d3_force) - return true; + /* + * Hotplug ports handled by firmware in System Management Mode + * may not be put into D3 by the OS (Thunderbolt on non-Macs). + */ + if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) + return false; - /* Even the oldest 2010 Thunderbolt controller supports D3. */ - if (bridge->is_thunderbolt) - return true; + if (pci_bridge_d3_force) + return true; - /* Platform might know better if the bridge supports D3 */ - if (platform_pci_bridge_d3(bridge)) - return true; + /* Even the oldest 2010 Thunderbolt controller supports D3. */ + if (bridge->is_thunderbolt) + return true; - /* - * Hotplug ports handled natively by the OS were not validated - * by vendors for runtime D3 at least until 2018 because there - * was no OS support. - */ - if (bridge->is_hotplug_bridge) - return false; + /* Platform might know better if the bridge supports D3 */ + if (platform_pci_bridge_d3(bridge)) + return true; - if (dmi_check_system(bridge_d3_blacklist)) - return false; + /* + * Hotplug ports handled natively by the OS were not validated + * by vendors for runtime D3 at least until 2018 because there + * was no OS support. + */ + if (bridge->is_hotplug_bridge) + return false; - /* - * It should be safe to put PCIe ports from 2015 or newer - * to D3. - */ - if (dmi_get_bios_year() >= 2015) - return true; - break; - } + if (dmi_check_system(bridge_d3_blacklist)) + return false; - return false; + /* + * It should be safe to put PCIe ports from 2015 or newer + * to D3. + */ + return dmi_get_bios_year() >= 2015; } static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) From patchwork Tue Jul 11 00:53:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13307941 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45F5EC001DF for ; Tue, 11 Jul 2023 01:38:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230421AbjGKBi2 (ORCPT ); Mon, 10 Jul 2023 21:38:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230311AbjGKBi0 (ORCPT ); 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Mon, 10 Jul 2023 20:38:21 -0500 From: Mario Limonciello To: "Rafael J . Wysocki" , Bjorn Helgaas CC: , , Len Brown , , Mario Limonciello , Iain Lane , "Kuppuswamy Sathyanarayanan" , Mika Westerberg Subject: [PATCH v7 2/2] PCI: Don't put non-power manageable PCIe root ports into D3 Date: Mon, 10 Jul 2023 19:53:25 -0500 Message-ID: <20230711005325.1499-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230711005325.1499-1-mario.limonciello@amd.com> References: <20230711005325.1499-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT091:EE_|CY5PR12MB6035:EE_ X-MS-Office365-Filtering-Correlation-Id: 5aa9c40c-0637-49db-111b-08db81af8380 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mCdjBFgUZLGYswVaPHe2ZHQZbl3MRpYU2rKZmm48nggnmAZnGQdQ+CKaWKp6k4bSdJsEyClI4j79SJMdwQPf7IADkmyrwPCiEVuqnAMc16eTMqO1RwGiUFwuGMjwQAJEJUogoZe2yPoDVCG6IbX2IItc7yxGXjGylDKF3+zMCFsxgQG5JNoFupRFEGOp8qk/NI1sFalN8KIAtKl+IiZUFJAuX+7aQpB8U07sJUgepJEwOmHzGzS1AL2gktVP82DAssvKc0+kNVQO6ozZa5Uq7oUO+6xGS5IqTLMRYu/lND02a+XQB+RKBGnCpC2i99WpqgIibCfn2jxCwOK1bb2TRr9j0/gO1pA+YavXBxny+LVAKf1UP9XDfVH74IMiJsU0Vcq3vSl1YSIHRVKXaFUZmlSoyO7kWfEGw4+rGnOzE5OtSZVPNZAoNFdZNVMyuDdxUy39TZoWcRaJnvjYzS3ZYjk2zrM3cjtMZXLy5NeKrKtrAjh2LU511Tuee0+CkeF1LUG3MB1tx06WhDZSEUuaZmfVNSJuzd/dpPm3Am6g4+qfHskA+fdYk2HqS5+9EHo8CnibGXo27tmFsp+ZyB7hmqQjC0XavtPhqkmrdANnkL6jpkoE5xbMfGtotdJoiBs2XQdfUKEENXof5Gp0wEm12xrPtfsOUfipvYvmgCSd/4h0j88S2jkGWJCXGK/03dH28I5osVVlqj1t/DwqUQWJawmVWohMDrYv8USK9vD3LPquqqjdSp1RblDEwsIQsOC+aITOE167YlVRe7JtFvs0xvNsZXScrsMnT1G6Um3a51w= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(346002)(136003)(396003)(376002)(451199021)(36840700001)(40470700004)(46966006)(336012)(426003)(2616005)(41300700001)(26005)(1076003)(83380400001)(16526019)(186003)(36860700001)(966005)(47076005)(478600001)(81166007)(82740400003)(356005)(110136005)(54906003)(7696005)(40460700003)(4326008)(44832011)(70206006)(70586007)(40480700001)(316002)(86362001)(8936002)(82310400005)(5660300002)(8676002)(2906002)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jul 2023 01:38:22.6806 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5aa9c40c-0637-49db-111b-08db81af8380 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT091.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6035 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Since commit 9d26d3a8f1b0 ("PCI: Put PCIe ports into D3 during suspend") PCIe ports from modern machines (>2015) are allowed to be put into D3 by storing a flag in the `struct pci_dev` structure. pci_power_manageable() uses this flag to indicate a PCIe port can enter D3. pci_pm_suspend_noirq() uses the return from pci_power_manageable() to decide whether to try to put a device into its target state for a sleep cycle via pci_prepare_to_sleep(). For devices that support D3, the target state is selected by this policy: 1. If platform_pci_power_manageable(): Use platform_pci_choose_state() 2. If the device is armed for wakeup: Select the deepest D-state that supports a PME. 3. Else: Use D3hot. Devices are considered power manageable by the platform when they have one or more objects described in the table in section 7.3 of the ACPI 6.4 specification. At suspend Linux puts PCIe root ports that are not power manageable by the platform into D3hot. Windows only puts PCIe root ports into D3 when they are power manageable by the platform. The policy selected for Linux to put non-power manageable PCIe root ports into D3hot at system suspend doesn't match anything in the PCIe or ACPI specs. Linux shouldn't assume PCIe root ports support D3 just because they're on a machine newer than 2015, the ports should also be considered power manageable by the platform. Add an extra check for PCIe root ports to ensure D3 isn't selected for them if they are not power-manageable through platform firmware. This will avoid pci_pm_suspend_noirq() changing the power state via pci_prepare_to_sleep(). The check is focused on PCIe root ports because they are part of the platform. Other PCIe bridges may be connected externally and thus cannot impose platform specific limitations. Link: https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/07_Power_and_Performance_Mgmt/device-power-management-objects.html [1] Fixes: 9d26d3a8f1b0 ("PCI: Put PCIe ports into D3 during suspend") Reported-by: Iain Lane Closes: https://forums.lenovo.com/t5/Ubuntu/Z13-can-t-resume-from-suspend-with-external-USB-keyboard/m-p/5217121 Acked-by: Rafael J. Wysocki Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Mika Westerberg Signed-off-by: Mario Limonciello --- v6->v7: * revert back to v5 code, rewrite commit message to specific examples and be more generic --- drivers/pci/pci.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index f916fd76eba79..4be8c6f8f4ebe 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3041,6 +3041,14 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge) if (dmi_check_system(bridge_d3_blacklist)) return false; + /* + * It's not safe to put root ports that aren't power manageable + * by the platform into D3. + */ + if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT && + !platform_pci_power_manageable(bridge)) + return false; + /* * It should be safe to put PCIe ports from 2015 or newer * to D3.