From patchwork Thu Jul 13 10:33:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311806 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBE32EB64DD for ; Thu, 13 Jul 2023 10:37:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C680910E6AF; Thu, 13 Jul 2023 10:37:47 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5836A10E671; Thu, 13 Jul 2023 10:37:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689244663; x=1720780663; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gAm7qtEcVUgh1v1EtJHa+WeaqH979a+0/Nu49FDccGo=; b=jFJcpdKpj7MA98Dj5FeJ2HUoDkOTkRtKdULXcIRRx2pwVsiwOBiZgf7k Zlt+wm5uv6W2xOmvz7jDkWZvNca6x0KMGOj7Y1ykfuBGV3c89o8j88uHC id6j4Scy8ej9jE/kxb8xIwy9RGkbrQSdGWv3q9fDhpMPaUxsmQ8oviL/w LJDA2ii0V8O/3iEe9JobVSlUyR4P2EqVnZ09mHlywWb6ySH+/j5E8qKFZ Y8ZbYc454DyaaeZa0V4q7Ki5RlFBroYJJlR1ni5sNDqpRVNSv67A3NtWY 99gVybvCdzITZRP1DWKEXURHzmkmY8BivWm1z5/0shocMmQhqYg42zdHP w==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="428897524" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="428897524" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="895965296" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="895965296" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:29 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:28 +0530 Message-Id: <20230713103346.1163315-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 01/19] drm/i915/dp: Consider output_format while computing dsc bpp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" While using DSC the compressed bpp is computed assuming RGB output format. Consider the output_format and compute the compressed bpp during mode valid and compute config steps. For DP-MST we currently use RGB output format only, so continue using RGB while computing compressed bpp for MST case. v2: Use output_bpp instead for pipe_bpp to clamp compressed_bpp. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++++++++-- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 + 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 03675620e3ea..e0d9618fccab 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -744,6 +744,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, u32 link_clock, u32 lane_count, u32 mode_clock, u32 mode_hdisplay, bool bigjoiner, + enum intel_output_format output_format, u32 pipe_bpp, u32 timeslots) { @@ -768,6 +769,10 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, bits_per_pixel = ((link_clock * lane_count) * timeslots) / (intel_dp_mode_to_fec_clock(mode_clock) * 8); + /* Bandwidth required for 420 is half, that of 444 format */ + if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + bits_per_pixel *= 2; + drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots " "total bw %u pixel clock %u\n", bits_per_pixel, timeslots, @@ -1161,11 +1166,16 @@ intel_dp_mode_valid(struct drm_connector *_connector, if (HAS_DSC(dev_priv) && drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { + enum intel_output_format sink_format, output_format; + int pipe_bpp; + + sink_format = intel_dp_sink_format(connector, mode); + output_format = intel_dp_output_format(connector, sink_format); /* * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ - int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); /* * Output bpp is stored in 6.4 format so right shift by 4 to get the @@ -1185,6 +1195,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, target_clock, mode->hdisplay, bigjoiner, + output_format, pipe_bpp, 64) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, @@ -1724,6 +1735,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay, pipe_config->bigjoiner_pipes, + pipe_config->output_format, pipe_bpp, timeslots); /* @@ -1759,9 +1771,12 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, * calculation procedure is bit different for MST case. */ if (compute_pipe_bpp) { + u16 output_bpp = intel_dp_output_bpp(pipe_config->output_format, + pipe_config->pipe_bpp); + pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_output_bpp >> 4, - pipe_config->pipe_bpp); + output_bpp); } pipe_config->dsc.slice_count = dsc_dp_slice_count; drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n", diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 22099de3ca45..bb4f976af296 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -111,6 +111,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, u32 link_clock, u32 lane_count, u32 mode_clock, u32 mode_hdisplay, bool bigjoiner, + enum intel_output_format output_format, u32 pipe_bpp, u32 timeslots); u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index e3f176a093d2..aa8d9d570626 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -973,6 +973,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, target_clock, mode->hdisplay, bigjoiner, + INTEL_OUTPUT_FORMAT_RGB, pipe_bpp, 64) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, From patchwork Thu Jul 13 10:33:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3033C001B0 for ; Thu, 13 Jul 2023 10:37:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AF23A10E671; Thu, 13 Jul 2023 10:37:44 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7C55E10E673; Thu, 13 Jul 2023 10:37:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689244663; x=1720780663; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hHyRzVf8s0BAw3MEe4d3E+IpaKFQGvcOeDiaqthYbRk=; b=PraBaeA6G7ieTM7v9yYnM/R4YapDI7YgRsnl56IRyiNLbllOmpBzaz5S 5tLCX7ecSSDkmXD5ZbM9sn1Qqh8Jtk//y51TEvdyHmydNuNanfUZtxI19 /PtUDWkg61cAE+8OldbOJSWUrGKr5tFydDn+X6IVwNh+girRCkwBKHzu+ MovyqqpUlJquyF61cPNXP5s1inYo7/MNjlBc0fxR9MxdMQwEI9D6phMVQ kyiYwS12oO2Qow/1t8t8MZt2ZD97P7Yt8GPfV+NuQ5Z+FxaruswB8lfN2 dxOqiL8lD6BcTZp9BBsD9bEJHRKdnM3sJhu0EBr+7E11u3Uc50EQ+dCLt w==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="428897528" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="428897528" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="895965310" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="895965310" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:38 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:29 +0530 Message-Id: <20230713103346.1163315-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 02/19] drm/i915/dp: Move compressed bpp check with 420 format inside the helper X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Move the check for limiting compressed bite_per_pixel for 420,422 formats in the helper to compute bits_per_pixel. Signed-off-by: Ankit Nautiyal Reviewed-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e0d9618fccab..d1db457fb17c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -773,6 +773,15 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) bits_per_pixel *= 2; + /* + * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum + * supported PPS value can be 63.9375 and with the further + * mention that for 420, 422 formats, bpp should be programmed double + * the target bpp restricting our target bpp to be 31.9375 at max. + */ + if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + bits_per_pixel = min_t(u32, bits_per_pixel, 31); + drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots " "total bw %u pixel clock %u\n", bits_per_pixel, timeslots, @@ -1738,15 +1747,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->output_format, pipe_bpp, timeslots); - /* - * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum - * supported PPS value can be 63.9375 and with the further - * mention that bpp should be programmed double the target bpp - * restricting our target bpp to be 31.9375 at max - */ - if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) - dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4); - if (!dsc_max_output_bpp) { drm_dbg_kms(&dev_priv->drm, "Compressed BPP not supported\n"); From patchwork Thu Jul 13 10:33:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E7B09EB64DD for ; Thu, 13 Jul 2023 10:37:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BF59A10E676; Thu, 13 Jul 2023 10:37:44 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id A506B10E671; Thu, 13 Jul 2023 10:37:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689244663; x=1720780663; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=05mZfvDfdESJ1FctS1zOndWuOZnJUrQz9bb6DlJD3gQ=; b=Q79PKdj+3mw6A6sM0D280dU2lALVNIyzATwikzM5wUKgNWL67+YQEpKJ nlFQUFf7zVSIws+vZtZ9jC838TLWG2Lw5Qn6e1jGj8J6gJNHF+KyRiE0Q CXftDXuMsbFEfWhHScuYVBAXRM3XDHAiZvLPtWaznLcRTiuKqX2Ccoj3F diivbUV0+7yQh9KUTUyGZl70J8ZFpIqee5quIu4v4C3wGU/yyc3Y4mvgT k79P/Qmz9hyxP71D1W6ZZff8B/uPdjHMHexEUqC9NM3UtdCXOMqG+L5wp wsKuKOwVe/pfhgetvw9ChUbN5IUA41Gwv8XZUpTLJhv2mZYMIglL1bLUz w==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="428897532" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="428897532" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="895965314" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="895965314" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:40 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:30 +0530 Message-Id: <20230713103346.1163315-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 03/19] drm/i915/dp_mst: Use output_format to get the final link bpp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The final link bpp used to calculate the m_n values depend on the output_format. Though the output_format is set to RGB for MST case and the link bpp will be same as the pipe bpp, for the sake of semantics, lets calculate the m_n values with the link bpp, instead of pipe_bpp. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d1db457fb17c..eb158efdb414 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -965,7 +965,7 @@ int intel_dp_min_bpp(enum intel_output_format output_format) return 8 * 3; } -static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) +int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) { /* * bpp value was assumed to RGB format. And YCbCr 4:2:0 output diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index bb4f976af296..7dd015385054 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -144,5 +144,6 @@ void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, void intel_dp_phy_test(struct intel_encoder *encoder); void intel_dp_wait_source_oui(struct intel_dp *intel_dp); +int intel_dp_output_bpp(enum intel_output_format output_format, int bpp); #endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index aa8d9d570626..ef5375eb923e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -155,6 +155,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; int slots = -EINVAL; + int link_bpp; slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp, limits->min_bpp, limits, @@ -163,7 +164,9 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, if (slots < 0) return slots; - intel_link_compute_m_n(crtc_state->pipe_bpp, + link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp); + + intel_link_compute_m_n(link_bpp, crtc_state->lane_count, adjusted_mode->crtc_clock, crtc_state->port_clock, From patchwork Thu Jul 13 10:33:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBA6FC001DC for ; Thu, 13 Jul 2023 10:37:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D41110E67D; Thu, 13 Jul 2023 10:37:49 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3C73B10E685; Thu, 13 Jul 2023 10:37:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689244666; x=1720780666; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=d/0MC6zDiLevdZJRraAyFKklsZ9aB+BTtPb6XTTXF6g=; b=mLI17ODFKbNH2H9xXe73IKPwy2rey/kCjPPFRKWq1ObbIk7OlM6a9sGW wmmCgex/7CXj1qQMHcHHwAJ8kpiGaWnK54HtKvCnWK1auiHXFiftiTv5E DC6+XBpkzJ2Xvu3n42Zq5uO9NOgNcMBYIshmRmDTEbf/25rTjNNpGi4ec 00prLE8CtjpEbMrHRahAx5Wid2sENmNMvOi+wVruqYc6lZcdLzJ1V1Np8 H1MUkLWgA5k8tVnJNYax5dtbT8HrEo/uwopjt2LRnx5Rspp0lNy4oatzK IrdjDuwor25+bgAGRfMLc0N/8b7f+/M8VkQ8mQwjEePBloT661pit2x6o A==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="428897543" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="428897543" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="895965322" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="895965322" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:43 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:31 +0530 Message-Id: <20230713103346.1163315-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 04/19] drm/i915/dp: Use consistent name for link bpp and compressed bpp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently there are many places where we use output_bpp for link bpp and compressed bpp. Lets use consistent naming: output_bpp : The intermediate value taking into account the output_format chroma subsampling. compressed_bpp : target bpp for the DSC encoder. link_bpp : final bpp used in the link. For 444 sampling without DSC: link_bpp = output_bpp = pipe_bpp For 420 sampling without DSC: output_bpp = pipe_bpp / 2 link_bpp = output_bpp For 444 sampling with DSC: output_bpp = pipe_bpp link_bpp = compressed_bpp, computed with output_bpp (i.e. pipe_bpp in this case) For 420 sampling with DSC: output_bpp = pipe_bpp/2 link_bpp = compressed_bpp, computed with output_bpp Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 84 ++++++++++----------- drivers/gpu/drm/i915/display/intel_dp.h | 14 ++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++--- 3 files changed, 60 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index eb158efdb414..19768ac658ba 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -740,13 +740,13 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p return bits_per_pixel; } -u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, - u32 link_clock, u32 lane_count, - u32 mode_clock, u32 mode_hdisplay, - bool bigjoiner, - enum intel_output_format output_format, - u32 pipe_bpp, - u32 timeslots) +u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + enum intel_output_format output_format, + u32 pipe_bpp, + u32 timeslots) { u32 bits_per_pixel, max_bpp_small_joiner_ram; @@ -1136,7 +1136,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, int target_clock = mode->clock; int max_rate, mode_rate, max_lanes, max_link_clock; int max_dotclk = dev_priv->max_dotclk_freq; - u16 dsc_max_output_bpp = 0; + u16 dsc_max_compressed_bpp = 0; u8 dsc_slice_count = 0; enum drm_mode_status status; bool dsc = false, bigjoiner = false; @@ -1191,21 +1191,21 @@ intel_dp_mode_valid(struct drm_connector *_connector, * integer value since we support only integer values of bpp. */ if (intel_dp_is_edp(intel_dp)) { - dsc_max_output_bpp = + dsc_max_compressed_bpp = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; dsc_slice_count = drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, true); } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { - dsc_max_output_bpp = - intel_dp_dsc_get_output_bpp(dev_priv, - max_link_clock, - max_lanes, - target_clock, - mode->hdisplay, - bigjoiner, - output_format, - pipe_bpp, 64) >> 4; + dsc_max_compressed_bpp = + intel_dp_dsc_get_max_compressed_bpp(dev_priv, + max_link_clock, + max_lanes, + target_clock, + mode->hdisplay, + bigjoiner, + output_format, + pipe_bpp, 64) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -1213,7 +1213,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, bigjoiner); } - dsc = dsc_max_output_bpp && dsc_slice_count; + dsc = dsc_max_compressed_bpp && dsc_slice_count; } /* @@ -1502,9 +1502,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, int mode_rate, link_rate, link_avail; for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { - int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); + int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); - mode_rate = intel_dp_link_required(clock, output_bpp); + mode_rate = intel_dp_link_required(clock, link_bpp); for (i = 0; i < intel_dp->num_common_rates; i++) { link_rate = intel_dp_common_rate(intel_dp, i); @@ -1733,21 +1733,21 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return -EINVAL; } } else { - u16 dsc_max_output_bpp = 0; + u16 dsc_max_compressed_bpp = 0; u8 dsc_dp_slice_count; if (compute_pipe_bpp) { - dsc_max_output_bpp = - intel_dp_dsc_get_output_bpp(dev_priv, - pipe_config->port_clock, - pipe_config->lane_count, - adjusted_mode->crtc_clock, - adjusted_mode->crtc_hdisplay, - pipe_config->bigjoiner_pipes, - pipe_config->output_format, - pipe_bpp, - timeslots); - if (!dsc_max_output_bpp) { + dsc_max_compressed_bpp = + intel_dp_dsc_get_max_compressed_bpp(dev_priv, + pipe_config->port_clock, + pipe_config->lane_count, + adjusted_mode->crtc_clock, + adjusted_mode->crtc_hdisplay, + pipe_config->bigjoiner_pipes, + pipe_config->output_format, + pipe_bpp, + timeslots); + if (!dsc_max_compressed_bpp) { drm_dbg_kms(&dev_priv->drm, "Compressed BPP not supported\n"); return -EINVAL; @@ -1775,7 +1775,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->pipe_bpp); pipe_config->dsc.compressed_bpp = min_t(u16, - dsc_max_output_bpp >> 4, + dsc_max_compressed_bpp >> 4, output_bpp); } pipe_config->dsc.slice_count = dsc_dp_slice_count; @@ -2151,7 +2151,7 @@ static bool can_enable_drrs(struct intel_connector *connector, static void intel_dp_drrs_compute_config(struct intel_connector *connector, struct intel_crtc_state *pipe_config, - int output_bpp) + int link_bpp) { struct drm_i915_private *i915 = to_i915(connector->base.dev); const struct drm_display_mode *downclock_mode = @@ -2176,7 +2176,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, if (pipe_config->splitter.enable) pixel_clock /= pipe_config->splitter.link_count; - intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock, + intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock, pipe_config->port_clock, &pipe_config->dp_m2_n2, pipe_config->fec_enable); @@ -2274,7 +2274,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); const struct drm_display_mode *fixed_mode; struct intel_connector *connector = intel_dp->attached_connector; - int ret = 0, output_bpp; + int ret = 0, link_bpp; if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A) pipe_config->has_pch_encoder = true; @@ -2324,10 +2324,10 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_dp_limited_color_range(pipe_config, conn_state); if (pipe_config->dsc.compression_enable) - output_bpp = pipe_config->dsc.compressed_bpp; + link_bpp = pipe_config->dsc.compressed_bpp; else - output_bpp = intel_dp_output_bpp(pipe_config->output_format, - pipe_config->pipe_bpp); + link_bpp = intel_dp_output_bpp(pipe_config->output_format, + pipe_config->pipe_bpp); if (intel_dp->mso_link_count) { int n = intel_dp->mso_link_count; @@ -2351,7 +2351,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_dp_audio_compute_config(encoder, pipe_config, conn_state); - intel_link_compute_m_n(output_bpp, + intel_link_compute_m_n(link_bpp, pipe_config->lane_count, adjusted_mode->crtc_clock, pipe_config->port_clock, @@ -2367,7 +2367,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_vrr_compute_config(pipe_config, conn_state); intel_psr_compute_config(intel_dp, pipe_config, conn_state); - intel_dp_drrs_compute_config(connector, pipe_config, output_bpp); + intel_dp_drrs_compute_config(connector, pipe_config, link_bpp); intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 7dd015385054..6fd423463f5c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -107,13 +107,13 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); -u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, - u32 link_clock, u32 lane_count, - u32 mode_clock, u32 mode_hdisplay, - bool bigjoiner, - enum intel_output_format output_format, - u32 pipe_bpp, - u32 timeslots); +u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + enum intel_output_format output_format, + u32 pipe_bpp, + u32 timeslots); u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, int mode_hdisplay, bool bigjoiner); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index ef5375eb923e..1f00713fb1ad 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -915,7 +915,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, int max_rate, mode_rate, max_lanes, max_link_clock; int ret; bool dsc = false, bigjoiner = false; - u16 dsc_max_output_bpp = 0; + u16 dsc_max_compressed_bpp = 0; u8 dsc_slice_count = 0; int target_clock = mode->clock; @@ -969,15 +969,15 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { - dsc_max_output_bpp = - intel_dp_dsc_get_output_bpp(dev_priv, - max_link_clock, - max_lanes, - target_clock, - mode->hdisplay, - bigjoiner, - INTEL_OUTPUT_FORMAT_RGB, - pipe_bpp, 64) >> 4; + dsc_max_compressed_bpp = + intel_dp_dsc_get_max_compressed_bpp(dev_priv, + max_link_clock, + max_lanes, + target_clock, + mode->hdisplay, + bigjoiner, + INTEL_OUTPUT_FORMAT_RGB, + pipe_bpp, 64) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -985,7 +985,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, bigjoiner); } - dsc = dsc_max_output_bpp && dsc_slice_count; + dsc = dsc_max_compressed_bpp && dsc_slice_count; } /* From patchwork Thu Jul 13 10:33:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B6655C001DF for ; Thu, 13 Jul 2023 10:37:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7ECD310E684; Thu, 13 Jul 2023 10:37:50 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id BC42410E683; Thu, 13 Jul 2023 10:37:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; 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13 Jul 2023 03:37:46 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:32 +0530 Message-Id: <20230713103346.1163315-6-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 05/19] drm/i915/dp: Update Bigjoiner interface bits for computing compressed bpp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In Bigjoiner check for DSC, bigjoiner interface bits for DP for DISPLAY > 13 is 36 (Bspec: 49259). v2: Corrected Display ver to 13. v3: Follow convention for conditional statement. (Ville) v4: Fix check for display ver. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_dp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 19768ac658ba..c1fd448d80e1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -802,8 +802,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram); if (bigjoiner) { + int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; u32 max_bpp_bigjoiner = - i915->display.cdclk.max_cdclk_freq * 48 / + i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits / intel_dp_mode_to_fec_clock(mode_clock); bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner); From patchwork Thu Jul 13 10:33:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311809 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8AFABC001DF for ; Thu, 13 Jul 2023 10:38:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 567AB10E66F; Thu, 13 Jul 2023 10:37:53 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3BF1810E670; Thu, 13 Jul 2023 10:37:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689244671; x=1720780671; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YpmARCwuN53B3jIy4gFtICG4aT6P2+HaC3plxhjoIX8=; b=EtjZrXIkJgzJjy84o0scaBFFH8sBCwh1UDKnnj7L9mh19fUxH5Lnx+hH 40fI9PfPq/BUam5MPB8sDL3OaZpP9nq9IIQ1VokW/AhAfLjX/OZ9le9Nz 9kseHrVt7cKt5mxYiwe5WV/O94jmsEvAhthmFXiEyIsfFXUc86YYLOkGE sHFIIjMas3w5EbR8x/Q3zeDbN/XEEjBBTHYbfwel6kr9vHBFzo5cqj5s2 loY+wVRY41oJDts359H18+8/R32WU2PUVThquRkKBk58ZJExvmuhXJoxc +YwwNPM0ONikwWjLYVAuRJd9qyn71sgaxBAdrq1+m5/l8S38uJ0HOmChn g==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="428897573" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="428897573" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="895965343" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="895965343" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:48 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:33 +0530 Message-Id: <20230713103346.1163315-7-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 06/19] drm/i915/display: Account for DSC not split case while computing cdclk X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we assume 2 Pixels Per Clock (PPC) while computing plane cdclk and min_cdlck. In cases where DSC single engine is used the throughput is 1 PPC. So account for the above case, while computing cdclk. v2: Use helper to get the adjusted pixel rate. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 12 ++++++++++++ drivers/gpu/drm/i915/display/intel_vdsc.h | 2 ++ drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++-- 4 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index dcc1f6941b60..701909966545 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2508,7 +2508,7 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) int pixel_rate = crtc_state->pixel_rate; if (DISPLAY_VER(dev_priv) >= 10) - return DIV_ROUND_UP(pixel_rate, 2); + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate); else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) return pixel_rate; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 9d76c2756784..bbfdbf06da68 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -1038,3 +1038,15 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) out: intel_display_power_put(dev_priv, power_domain, wakeref); } + +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate) +{ + /* + * If single VDSC engine is used, it uses one pixel per clock + * otherwise we use two pixels per clock. + */ + if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split) + return pixel_rate; + + return DIV_ROUND_UP(pixel_rate, 2); +} diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h index 2cc41ff08909..3bb4b1980b6b 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h @@ -28,4 +28,6 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, void intel_dsc_dp_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); +int intel_dsc_get_adjusted_pixel_rate(const struct intel_crtc_state *crtc_state, int pixel_rate); + #endif /* __INTEL_VDSC_H__ */ diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 6b01a0b68b97..9eeb25ec4be9 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -17,6 +17,7 @@ #include "intel_fb.h" #include "intel_fbc.h" #include "intel_psr.h" +#include "intel_vdsc.h" #include "skl_scaler.h" #include "skl_universal_plane.h" #include "skl_watermark.h" @@ -263,8 +264,7 @@ static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, { unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); - /* two pixels per clock */ - return DIV_ROUND_UP(pixel_rate, 2); + return intel_dsc_get_adjusted_pixel_rate(crtc_state, pixel_rate); } static void From patchwork Thu Jul 13 10:33:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CCE28C001DC for ; Thu, 13 Jul 2023 10:38:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B185410E67E; Thu, 13 Jul 2023 10:38:03 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id ACEBF10E675; Thu, 13 Jul 2023 10:37:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689244673; x=1720780673; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zCvPJcuYrlbe/kOgQGAbZPcrvTrPzWLfWa4jtGAg69s=; b=RlXdtLwJG+91eRaaxpVZTMUHpfgdU/75MKbBxVkYW6XIoE6ZhQDbEJ+Z wdjwcXCKh5W18jLFLJHWKnItG30TR2PRVhkXro0IniC/W70G+X0Pl7rO/ 4rWbKY+yblS9/D5GE+LbACUtw0xQ2fRR5nB0ByazdXbvo+J5fW+SDN+Pm lk5miqf+pwfJJIzH3KemsoVuq3Mlyw4dSle12YhytSWSc7ZnsnbkZvCWa P2usFfXInw+O+MRnBJ3Lh7kSMyZyA9VQPfawwhJLl4WYaN6EftpJjzFO0 yFtTbIDWqh0NCx3xdNmY9XdwxaSky0S5wK8S+c997gXrlQ5y1ZlpVcGNT Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="428897591" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="428897591" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="895965363" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="895965363" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:51 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:34 +0530 Message-Id: <20230713103346.1163315-8-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 07/19] drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlck X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" As per Bsepc:49259, Bigjoiner BW check puts restriction on the compressed bpp for a given CDCLK, pixelclock in cases where Bigjoiner + DSC are used. Currently compressed bpp is computed first, and it is ensured that the bpp will work at least with the max CDCLK freq. Since the CDCLK is computed later, lets account for Bigjoiner BW check while calculating Min CDCLK. v2: Use pixel clock in the bw calculations. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_cdclk.c | 61 +++++++++++++++++----- 1 file changed, 47 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 701909966545..788dba576294 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2533,6 +2533,51 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) return min_cdclk; } +static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); + int min_cdclk = 0; + + /* + * When we decide to use only one VDSC engine, since + * each VDSC operates with 1 ppc throughput, pixel clock + * cannot be higher than the VDSC clock (cdclk) + * If there 2 VDSC engines, then pixel clock can't be higher than + * VDSC clock(cdclk) * 2 and so on. + */ + min_cdclk = max_t(int, min_cdclk, + DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances)); + + if (crtc_state->bigjoiner_pipes) { + int pixel_clock = crtc_state->hw.adjusted_mode.clock; + + /* + * According to Bigjoiner bw check: + * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock + * + * We have already computed compressed_bpp, so now compute the min CDCLK that + * is required to support this compressed_bpp. + * + * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits) + * + * Since PPC = 2 with bigjoiner + * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits + * + * #TODO Bspec mentions to account for FEC overhead while using pixel clock. + * Check if we need to use FEC overhead in the above calculations. + */ + int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24; + int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) / + (2 * bigjoiner_interface_bits); + + min_cdclk = max(min_cdclk, min_cdclk_bj); + } + + return min_cdclk; +} + int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = @@ -2604,20 +2649,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) /* Account for additional needs from the planes */ min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); - /* - * When we decide to use only one VDSC engine, since - * each VDSC operates with 1 ppc throughput, pixel clock - * cannot be higher than the VDSC clock (cdclk) - * If there 2 VDSC engines, then pixel clock can't be higher than - * VDSC clock(cdclk) * 2 and so on. - */ - if (crtc_state->dsc.compression_enable) { - int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); - - min_cdclk = max_t(int, min_cdclk, - DIV_ROUND_UP(crtc_state->pixel_rate, - num_vdsc_instances)); - } + if (crtc_state->dsc.compression_enable) + min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); /* * HACK. Currently for TGL/DG2 platforms we calculate From patchwork Thu Jul 13 10:33:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311811 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2CB6C001DF for ; Thu, 13 Jul 2023 10:38:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 282FE10E687; Thu, 13 Jul 2023 10:38:04 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1632910E683; Thu, 13 Jul 2023 10:37:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689244676; x=1720780676; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gUfpFpc/luPElWH1FzjfFkFIB8EVuqvB5v+u0sS1Z/A=; b=JD6BtTV5Op1iRX48A+i+jPxo8YdfW8yDmKowtj6vO7YixEayxdtM6soJ QjYi/GW5/PguL+diItreVzoxgn1QGpa6kZhf0U4qorNmKhfYoupjBxS2j 0F8rcrMxMgVV3Kk6ON8r2o9cCCY74UurakouZg/CE9FFK8gdzGfcIjXaR 9/wrA/eM5UHC65bwZy8q7qyzemN6gErU6zkaDVUuIrxw4i7V5VDPrGP54 cfGhVSlPQ7hlU+iRhkIVNGGq/fgNUQZ6hjSDzc4MC0pDa0cEZ+ESrjJa8 oHwbzTQC8T4Z6vTune0pbkSsGe6vzMNmmk4NHru7m26ZgPoxyyMoR9TkU A==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="428897603" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="428897603" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="895965373" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="895965373" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:53 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:35 +0530 Message-Id: <20230713103346.1163315-9-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 08/19] drm/i915/dp: Remove extra logs for printing DSC info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DSC compressed bpp and slice counts are already getting printed at the end of dsc compute config. Remove extra logs. Signed-off-by: Ankit Nautiyal Reviewed-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_dp.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c1fd448d80e1..23ede846202c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1780,9 +1780,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, output_bpp); } pipe_config->dsc.slice_count = dsc_dp_slice_count; - drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n", - pipe_config->dsc.compressed_bpp, - pipe_config->dsc.slice_count); } /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate From patchwork Thu Jul 13 10:33:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311813 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28D0BC001B0 for ; Thu, 13 Jul 2023 10:38:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0EFB310E679; Thu, 13 Jul 2023 10:38:05 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id F34AB10E679; Thu, 13 Jul 2023 10:37:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689244679; x=1720780679; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4y42pTh9XibSH+4YiOHfWb5JVrl2VSe96evi/Hs1YUE=; b=P0JwSnyx+T5H9SlCHek4p++6j+HjMso2lYhMnj0lHefZnuXwIymB2YIR oCGYUEXoxY+bM6BiRlSfkA9u4gOji6tECQqwPtKFfXac7EMJ5eHVSiru2 0sJfkXT4w6Vwd2QgT6uoAsO21GfL3a42Yn3RcGj9G3Q1br9zKPiPhsAVH kHIdpDlqMzpyJyj77UGlc18aG9GB7iZFWHUfKHgTvV1zbLjov9bmz/2P2 9PRGqaqHJY2IUcOXd2JqDptLL4DHkn1ufnKwQ+WE898bl/+hpFTQw9R0Y 1VF2g1dJrVDsG6DtkoknFU0NXFlAneb/OPeLjvkxmizTO8oCB662UE/Wz Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="428897614" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="428897614" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="895965387" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="895965387" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:56 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:36 +0530 Message-Id: <20230713103346.1163315-10-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 09/19] drm/display/dp: Fix the DP DSC Receiver cap size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DP DSC Receiver Capabilities are exposed via DPCD 60h-6Fh. Fix the DSC RECEIVER CAP SIZE accordingly. Fixes: ffddc4363c28 ("drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT") Cc: Anusha Srivatsa Cc: Manasi Navare Cc: # v5.0+ Signed-off-by: Ankit Nautiyal --- include/drm/display/drm_dp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 02f2ac4dd2df..e69cece404b3 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -1537,7 +1537,7 @@ enum drm_dp_phy { #define DP_BRANCH_OUI_HEADER_SIZE 0xc #define DP_RECEIVER_CAP_SIZE 0xf -#define DP_DSC_RECEIVER_CAP_SIZE 0xf +#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */ #define EDP_PSR_RECEIVER_CAP_SIZE 2 #define EDP_DISPLAY_CTL_CAP_SIZE 3 #define DP_LTTPR_COMMON_CAP_SIZE 8 From patchwork Thu Jul 13 10:33:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311812 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F592EB64DD for ; Thu, 13 Jul 2023 10:38:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CDA3910E67C; Thu, 13 Jul 2023 10:38:04 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id EFA7010E679; Thu, 13 Jul 2023 10:38:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689244681; x=1720780681; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wttXTVZ5s3SuZbsKGAYTRw0dipll03nAt1UlylnnYY8=; b=FMjWsuOHYsk8IN/uMR+1WUl71vuA/NX1kREAVmxsQQPeJ+b4AoCA5HHa s/wJQtFqk8BovfoMAwyIMivmzLMoGsCyi6ktL/jvxrMsDYVZmkDOcCTT3 ulZx5c3WNZFaPh2jRhwWOv+EcihmCYpbJIEHn4iTwDemu+QVR9E0OpOVr 2imMCh9M6/v22poueTdA3YdjkijZeu6Gu8miPrLBb0AzTuM3JNpjHmqk1 7sqzReJPhJW74dAwrsMUSSbR6/vzZQmhf88kNiSysxMwUdVYVQhEjTJF0 XuvKkeLkEdD5z33hAPpOeDM81DM8kFq1bFDVKkmMyXLI06MLBWiNYU9dG g==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="428897626" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="428897626" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="895965399" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="895965399" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:37:58 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:37 +0530 Message-Id: <20230713103346.1163315-11-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 10/19] drm/i915/dp: Avoid forcing DSC BPC for MST case X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For MST the bpc is hardcoded to 8, and pipe bpp to 24. So avoid forcing DSC bpc for MST case. v2: Warn and ignore the debug flag than to bail out. (Jani) v3: Fix dbg message to mention forced bpc instead of bpp. v4: Fix checkpatch longline warning. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------ drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 +++++ 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 23ede846202c..11e54e6ee985 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1695,14 +1695,14 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format)) return -EINVAL; - if (compute_pipe_bpp) + if (intel_dp->force_dsc_bpc && compute_pipe_bpp) { + pipe_bpp = intel_dp->force_dsc_bpc * 3; + drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n", + intel_dp->force_dsc_bpc); + } else if (compute_pipe_bpp) { pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); - else + } else { pipe_bpp = pipe_config->pipe_bpp; - - if (intel_dp->force_dsc_bpc) { - pipe_bpp = intel_dp->force_dsc_bpc * 3; - drm_dbg_kms(&dev_priv->drm, "Input DSC BPP forced to %d", pipe_bpp); } /* Min Input BPC for ICL+ is 8 */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 1f00713fb1ad..dff4717edbd0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -361,6 +361,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, /* enable compression if the mode doesn't fit available BW */ drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); if (ret || intel_dp->force_dsc_en) { + /* + * FIXME: As bpc is hardcoded to 8, as mentioned above, + * WARN and ignore the debug flag force_dsc_bpc for now. + */ + drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n"); /* * Try to get at least some timeslots and then see, if * we can fit there with DSC. From patchwork Thu Jul 13 10:33:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311814 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12674C001DC for ; Thu, 13 Jul 2023 10:38:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9753F10E68B; Thu, 13 Jul 2023 10:38:08 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5B72510E687; Thu, 13 Jul 2023 10:38:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689244683; x=1720780683; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OWl1L2olCbxTBWDD7gAvupa/FqaGLrQfc9l7lN1r8dY=; b=aL4j1g6IPRBrXhtTl1wE+0ijFZEXreinZzoK5ok+xqPUavDKaTyjlKFZ UlmY79WIUJ2GT4y1kjVOl8PVblKH3yjrbWYg24rfzcCCjfuVAe1gRk86O YjJkX9kJeCm1mMnmA25PHY0/hkEj2K1cUvRnfcHwa3r2/vkC+idQ/s/y4 fYQ/5kiNOaShcm/Mmb92xjEMkYtLLLPk3K0yI3YXvZ8WKIIgBlV4ovegR 6QLDQjO6kvV3k9UJq/3ciPiYN2msjY0dqQpnMQ+at4PfL52Lu/NWd0pd6 yBksorn7mSZL+QTn1q4D4Uqo2oM4tB0zipZVc6hCwT5LQTa3tW3jqYcpP g==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="428897641" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="428897641" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="895965415" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="895965415" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:00 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:38 +0530 Message-Id: <20230713103346.1163315-12-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 11/19] drm/i915/dp: Add functions to get min/max src input bpc with DSC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Separate out functions for getting maximum and minimum input BPC based on platforms, when DSC is used. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 38 +++++++++++++++++++------ 1 file changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 11e54e6ee985..5cc62c51372d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1533,6 +1533,18 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, return -EINVAL; } +static +u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915) +{ + /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ + if (DISPLAY_VER(i915) >= 12) + return 12; + if (DISPLAY_VER(i915) == 11) + return 10; + + return 0; +} + int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -1540,11 +1552,12 @@ int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) u8 dsc_bpc[3] = {0}; u8 dsc_max_bpc; - /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ - if (DISPLAY_VER(i915) >= 12) - dsc_max_bpc = min_t(u8, 12, max_req_bpc); - else - dsc_max_bpc = min_t(u8, 10, max_req_bpc); + dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915); + + if (!dsc_max_bpc) + return dsc_max_bpc; + + dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc); num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, dsc_bpc); @@ -1672,6 +1685,16 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format); } +static +u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) +{ + /* Min DSC Input BPC for ICL+ is 8 */ + if (DISPLAY_VER(i915) >= 11) + return 8; + + return 0; +} + int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, @@ -1705,10 +1728,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_bpp = pipe_config->pipe_bpp; } - /* Min Input BPC for ICL+ is 8 */ - if (pipe_bpp < 8 * 3) { + if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) { drm_dbg_kms(&dev_priv->drm, - "No DSC support for less than 8bpc\n"); + "Computed BPC less than min supported by source for DSC\n"); return -EINVAL; } From patchwork Thu Jul 13 10:33:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9AEA9EB64DD for ; Thu, 13 Jul 2023 10:38:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8720610E68D; Thu, 13 Jul 2023 10:38:09 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2E33110E688; Thu, 13 Jul 2023 10:38:06 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="895965428" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:03 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:39 +0530 Message-Id: <20230713103346.1163315-13-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 12/19] drm/i915/dp: Check min bpc DSC limits for dsc_force_bpc also X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For DSC the min BPC is 8 for ICL+ and so the min pipe_bpp is 24. Check this condition for cases where bpc is forced by debugfs flag dsc_force_bpc. If the check fails, then WARN and ignore the debugfs flag. For MST case the pipe_bpp is already computed (hardcoded to be 24), and this check is not required. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 48 ++++++++++++++++--------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5cc62c51372d..9d2d05da594b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1695,6 +1695,12 @@ u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) return 0; } +static +bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp) +{ + return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3; +} + int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, @@ -1706,7 +1712,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; - int pipe_bpp; int ret; pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && @@ -1718,28 +1723,37 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format)) return -EINVAL; - if (intel_dp->force_dsc_bpc && compute_pipe_bpp) { - pipe_bpp = intel_dp->force_dsc_bpc * 3; - drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n", - intel_dp->force_dsc_bpc); - } else if (compute_pipe_bpp) { - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); - } else { - pipe_bpp = pipe_config->pipe_bpp; - } + if (compute_pipe_bpp) { + int pipe_bpp; + int forced_bpp = intel_dp->force_dsc_bpc * 3; - if (pipe_bpp < intel_dp_dsc_min_src_input_bpc(dev_priv) * 3) { - drm_dbg_kms(&dev_priv->drm, - "Computed BPC less than min supported by source for DSC\n"); - return -EINVAL; + if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp)) { + pipe_bpp = forced_bpp; + drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n", + intel_dp->force_dsc_bpc); + } else { + drm_WARN(&dev_priv->drm, forced_bpp, + "Cannot force DSC BPC:%d, due to DSC BPC limits\n", + intel_dp->force_dsc_bpc); + + pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, + conn_state->max_requested_bpc); + + if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) { + drm_dbg_kms(&dev_priv->drm, + "Computed BPC less than min supported by source for DSC\n"); + return -EINVAL; + } + } + + pipe_config->pipe_bpp = pipe_bpp; } /* - * For now enable DSC for max bpp, max link rate, max lane count. + * For now enable DSC for max link rate, max lane count. * Optimize this later for the minimum possible link rate/lane count * with DSC enabled for the requested mode. */ - pipe_config->pipe_bpp = pipe_bpp; pipe_config->port_clock = limits->max_rate; pipe_config->lane_count = limits->max_lane_count; @@ -1768,7 +1782,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_hdisplay, pipe_config->bigjoiner_pipes, pipe_config->output_format, - pipe_bpp, + pipe_config->pipe_bpp, timeslots); if (!dsc_max_compressed_bpp) { drm_dbg_kms(&dev_priv->drm, From patchwork Thu Jul 13 10:33:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0328FEB64DD for ; Thu, 13 Jul 2023 10:38:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7B4E810E688; Thu, 13 Jul 2023 10:38:15 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8E9FA10E688; Thu, 13 Jul 2023 10:38:08 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="895965438" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:06 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:40 +0530 Message-Id: <20230713103346.1163315-14-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 13/19] drm/i915/dp: Avoid left shift of DSC output bpp by 4 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To make way for fractional bpp support, avoid left shifting the output_bpp by 4 in helper intel_dp_dsc_get_output_bpp. Signed-off-by: Ankit Nautiyal Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_dp.c | 10 +++------- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9d2d05da594b..a7d58eb914c6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -812,11 +812,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp); - /* - * Compressed BPP in U6.4 format so multiply by 16, for Gen 11, - * fractional part is 0 - */ - return bits_per_pixel << 4; + return bits_per_pixel; } u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, @@ -1206,7 +1202,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, mode->hdisplay, bigjoiner, output_format, - pipe_bpp, 64) >> 4; + pipe_bpp, 64); dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -1812,7 +1808,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->pipe_bpp); pipe_config->dsc.compressed_bpp = min_t(u16, - dsc_max_compressed_bpp >> 4, + dsc_max_compressed_bpp, output_bpp); } pipe_config->dsc.slice_count = dsc_dp_slice_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index dff4717edbd0..4895d6242915 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -982,7 +982,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, mode->hdisplay, bigjoiner, INTEL_OUTPUT_FORMAT_RGB, - pipe_bpp, 64) >> 4; + pipe_bpp, 64); dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, From patchwork Thu Jul 13 10:33:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 58EAEEB64DD for ; Thu, 13 Jul 2023 10:38:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1864610E694; Thu, 13 Jul 2023 10:38:18 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 97C9510E678; Thu, 13 Jul 2023 10:38:11 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="895965446" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:08 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:41 +0530 Message-Id: <20230713103346.1163315-15-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 14/19] drm/i915/dp: Rename helper to get DSC max pipe_bpp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The helper intel_dp_dsc_compute_bpp gives the maximum pipe bpp that is allowed with DSC. Rename the this to reflect that it returns max pipe bpp supported with DSC. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_dp.h | 2 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a7d58eb914c6..c437ec23698a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1181,7 +1181,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX); /* * Output bpp is stored in 6.4 format so right shift by 4 to get the @@ -1541,7 +1541,7 @@ u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915) return 0; } -int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) +int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int i, num_bpc; @@ -1732,8 +1732,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, "Cannot force DSC BPC:%d, due to DSC BPC limits\n", intel_dp->force_dsc_bpc); - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, - conn_state->max_requested_bpc); + pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, + conn_state->max_requested_bpc); if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) { drm_dbg_kms(&dev_priv->drm, diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 6fd423463f5c..788a577ebe16 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -106,7 +106,7 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); -int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, u32 link_clock, u32 lane_count, u32 mode_clock, u32 mode_hdisplay, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 4895d6242915..3eb085fbc7c8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -971,7 +971,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ - int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX); if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { dsc_max_compressed_bpp = From patchwork Thu Jul 13 10:33:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A42A4EB64DD for ; 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a="428897684" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="428897684" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="895965453" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="895965453" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:11 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:42 +0530 Message-Id: <20230713103346.1163315-16-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 15/19] drm/i915/dp: Separate out functions for edp/DP for computing DSC bpp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Refactor code to separate functions for eDP and DP for computing pipe_bpp/compressed bpp when DSC is involved. This will help to optimize the link configuration for DP later. v2: Fix checkpatch warning. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 191 ++++++++++++++++-------- 1 file changed, 126 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c437ec23698a..c925cae40c49 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1697,6 +1697,115 @@ bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp) return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3; } +static +int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + int forced_bpp; + + if (!intel_dp->force_dsc_bpc) + return 0; + + forced_bpp = intel_dp->force_dsc_bpc * 3; + + if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) { + drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc); + return forced_bpp; + } + + drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n", + intel_dp->force_dsc_bpc); + + return 0; +} + +static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int timeslots) +{ + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + u16 output_bpp, dsc_max_compressed_bpp = 0; + int forced_bpp, pipe_bpp; + + forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp); + + if (forced_bpp) { + pipe_bpp = forced_bpp; + } else { + pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc); + + if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) { + drm_dbg_kms(&i915->drm, + "Computed BPC less than min supported by source for DSC\n"); + return -EINVAL; + } + } + /* + * For now enable DSC for max link rate, max lane count. + * Optimize this later for the minimum possible link rate/lane count + * with DSC enabled for the requested mode. + */ + pipe_config->port_clock = limits->max_rate; + pipe_config->lane_count = limits->max_lane_count; + dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915, + pipe_config->port_clock, + pipe_config->lane_count, + adjusted_mode->crtc_clock, + adjusted_mode->crtc_hdisplay, + pipe_config->bigjoiner_pipes, + pipe_config->output_format, + pipe_bpp, + timeslots); + if (!dsc_max_compressed_bpp) { + drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n"); + return -EINVAL; + } + + output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); + + pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp, output_bpp); + + pipe_config->pipe_bpp = pipe_bpp; + + return 0; +} + +static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + int pipe_bpp, forced_bpp; + + forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp); + + if (forced_bpp) { + pipe_bpp = forced_bpp; + } else { + /* For eDP use max bpp that can be supported with DSC. */ + pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, + conn_state->max_requested_bpc); + if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) { + drm_dbg_kms(&i915->drm, + "Computed BPC less than min supported by source for DSC\n"); + return -EINVAL; + } + } + pipe_config->port_clock = limits->max_rate; + pipe_config->lane_count = limits->max_lane_count; + pipe_config->dsc.compressed_bpp = + min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, + pipe_bpp); + + pipe_config->pipe_bpp = pipe_bpp; + + return 0; +} + int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, @@ -1719,44 +1828,28 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format)) return -EINVAL; + /* + * compute pipe bpp is set to false for DP MST DSC case + * and compressed_bpp is calculated same time once + * vpci timeslots are allocated, because overall bpp + * calculation procedure is bit different for MST case. + */ if (compute_pipe_bpp) { - int pipe_bpp; - int forced_bpp = intel_dp->force_dsc_bpc * 3; - - if (forced_bpp && is_dsc_pipe_bpp_sufficient(dev_priv, forced_bpp)) { - pipe_bpp = forced_bpp; - drm_dbg_kms(&dev_priv->drm, "Input DSC BPC forced to %d\n", - intel_dp->force_dsc_bpc); - } else { - drm_WARN(&dev_priv->drm, forced_bpp, - "Cannot force DSC BPC:%d, due to DSC BPC limits\n", - intel_dp->force_dsc_bpc); - - pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, - conn_state->max_requested_bpc); - - if (!is_dsc_pipe_bpp_sufficient(dev_priv, pipe_bpp)) { - drm_dbg_kms(&dev_priv->drm, - "Computed BPC less than min supported by source for DSC\n"); - return -EINVAL; - } + if (intel_dp_is_edp(intel_dp)) + ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config, + conn_state, limits); + else + ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config, + conn_state, limits, timeslots); + if (ret) { + drm_dbg_kms(&dev_priv->drm, + "No Valid pipe bpp for given mode ret = %d\n", ret); + return ret; } - - pipe_config->pipe_bpp = pipe_bpp; } - /* - * For now enable DSC for max link rate, max lane count. - * Optimize this later for the minimum possible link rate/lane count - * with DSC enabled for the requested mode. - */ - pipe_config->port_clock = limits->max_rate; - pipe_config->lane_count = limits->max_lane_count; - + /* Calculate Slice count */ if (intel_dp_is_edp(intel_dp)) { - pipe_config->dsc.compressed_bpp = - min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, - pipe_config->pipe_bpp); pipe_config->dsc.slice_count = drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, true); @@ -1766,26 +1859,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return -EINVAL; } } else { - u16 dsc_max_compressed_bpp = 0; u8 dsc_dp_slice_count; - if (compute_pipe_bpp) { - dsc_max_compressed_bpp = - intel_dp_dsc_get_max_compressed_bpp(dev_priv, - pipe_config->port_clock, - pipe_config->lane_count, - adjusted_mode->crtc_clock, - adjusted_mode->crtc_hdisplay, - pipe_config->bigjoiner_pipes, - pipe_config->output_format, - pipe_config->pipe_bpp, - timeslots); - if (!dsc_max_compressed_bpp) { - drm_dbg_kms(&dev_priv->drm, - "Compressed BPP not supported\n"); - return -EINVAL; - } - } dsc_dp_slice_count = intel_dp_dsc_get_slice_count(intel_dp, adjusted_mode->crtc_clock, @@ -1797,20 +1872,6 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return -EINVAL; } - /* - * compute pipe bpp is set to false for DP MST DSC case - * and compressed_bpp is calculated same time once - * vpci timeslots are allocated, because overall bpp - * calculation procedure is bit different for MST case. - */ - if (compute_pipe_bpp) { - u16 output_bpp = intel_dp_output_bpp(pipe_config->output_format, - pipe_config->pipe_bpp); - - pipe_config->dsc.compressed_bpp = min_t(u16, - dsc_max_compressed_bpp, - output_bpp); - } pipe_config->dsc.slice_count = dsc_dp_slice_count; } /* From patchwork Thu Jul 13 10:33:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E583EC001B0 for ; Thu, 13 Jul 2023 10:38:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0334110E68E; Thu, 13 Jul 2023 10:38:20 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 720FE10E68E; Thu, 13 Jul 2023 10:38:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689244696; x=1720780696; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RJlnSwN1Sg4zfGeSO1RQz4PZJmI3uZF/wC1+S6FREW4=; b=Fh9LV7DHo0BaUqE3tWUjDIfSleh1uxg4zira2p77Rx9yECRD+Vw74Tyv +h057Gr3I7toz/GN877WuEfZxTicb6q22CSoSOyKZWevHJcSnJBl1NoSF FuQH7fQ9mSsxltwTPT2CQY7/0PgqIXhMOQ5obuhxBEmCqCuXZNdOPs2nJ XYGUlvz5rUNIKZjUbNk7JYV+DRGVq9WR5DBUBop0TF9482zshfstzrsIV bf86AjgN+U0STdiXp1cgfoKofgaaDvargKvYoqhHtLN6kNvVnoLztnl4f +jcskPRQISlmaMkeK0B68MQiqlya068vFp3oKppyh5tnGkEWxQ3KMDuoS Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="428897692" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="428897692" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="895965458" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="895965458" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:14 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:43 +0530 Message-Id: <20230713103346.1163315-17-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 16/19] drm/i915/dp: Add DSC BPC/BPP constraints while selecting pipe bpp with DSC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we check if the pipe_bpp selected is >= the min DSC bpc/bpp requirement. We do not check if it is <= the max DSC bpc/bpp requirement. Add checks for max DSC BPC/BPP constraints while computing the pipe_bpp when DSC is in use. v2: Fix the commit message. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 34 +++++++++++++++++-------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c925cae40c49..c39039e214ff 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1692,13 +1692,27 @@ u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) } static -bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, int pipe_bpp) +bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int pipe_bpp) { - return pipe_bpp >= intel_dp_dsc_min_src_input_bpc(i915) * 3; + u8 dsc_max_bpc, dsc_min_bpc, dsc_max_pipe_bpp, dsc_min_pipe_bpp; + + dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc); + dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915); + + dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->max_bpp); + dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->min_bpp); + + return pipe_bpp >= dsc_min_pipe_bpp && + pipe_bpp <= dsc_max_pipe_bpp; } static -int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp) +int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp, + struct drm_connector_state *conn_state, + struct link_config_limits *limits) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int forced_bpp; @@ -1708,7 +1722,7 @@ int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp) forced_bpp = intel_dp->force_dsc_bpc * 3; - if (is_dsc_pipe_bpp_sufficient(i915, forced_bpp)) { + if (is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, forced_bpp)) { drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc); return forced_bpp; } @@ -1730,16 +1744,16 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, u16 output_bpp, dsc_max_compressed_bpp = 0; int forced_bpp, pipe_bpp; - forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp); + forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits); if (forced_bpp) { pipe_bpp = forced_bpp; } else { pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc); - if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) { + if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) { drm_dbg_kms(&i915->drm, - "Computed BPC less than min supported by source for DSC\n"); + "Computed BPC is not in DSC BPC limits\n"); return -EINVAL; } } @@ -1781,7 +1795,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, struct drm_i915_private *i915 = dp_to_i915(intel_dp); int pipe_bpp, forced_bpp; - forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp); + forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits); if (forced_bpp) { pipe_bpp = forced_bpp; @@ -1789,9 +1803,9 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, /* For eDP use max bpp that can be supported with DSC. */ pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc); - if (!is_dsc_pipe_bpp_sufficient(i915, pipe_bpp)) { + if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) { drm_dbg_kms(&i915->drm, - "Computed BPC less than min supported by source for DSC\n"); + "Computed BPC is not in DSC BPC limits\n"); return -EINVAL; } } From patchwork Thu Jul 13 10:33:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50D37C001DF for ; Thu, 13 Jul 2023 10:38:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 98A3910E67A; Thu, 13 Jul 2023 10:38:24 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id D74CD10E68E; Thu, 13 Jul 2023 10:38:18 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="895965461" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:16 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:44 +0530 Message-Id: <20230713103346.1163315-18-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 17/19] drm/i915/dp: Separate out function to get compressed bpp with joiner X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Pull the code to get joiner constraints on maximum compressed bpp into separate function. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 49 ++++++++++++++----------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c39039e214ff..54fc60eb94a0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -740,6 +740,30 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p return bits_per_pixel; } +static +u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner) +{ + u32 max_bpp_small_joiner_ram; + + /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ + max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay; + + if (bigjoiner) { + int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; + u32 max_bpp_bigjoiner = + i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits / + intel_dp_mode_to_fec_clock(mode_clock); + + max_bpp_small_joiner_ram *= 2; + + return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner); + } + + return max_bpp_small_joiner_ram; +} + u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, u32 link_clock, u32 lane_count, u32 mode_clock, u32 mode_hdisplay, @@ -748,7 +772,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, u32 pipe_bpp, u32 timeslots) { - u32 bits_per_pixel, max_bpp_small_joiner_ram; + u32 bits_per_pixel, joiner_max_bpp; /* * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* @@ -788,27 +812,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, (link_clock * lane_count * 8), intel_dp_mode_to_fec_clock(mode_clock)); - /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ - max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / - mode_hdisplay; - - if (bigjoiner) - max_bpp_small_joiner_ram *= 2; - - /* - * Greatest allowed DSC BPP = MIN (output BPP from available Link BW - * check, output bpp from small joiner RAM check) - */ - bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram); + joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock, + mode_hdisplay, bigjoiner); - if (bigjoiner) { - int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; - u32 max_bpp_bigjoiner = - i915->display.cdclk.max_cdclk_freq * 2 * bigjoiner_interface_bits / - intel_dp_mode_to_fec_clock(mode_clock); - - bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner); - } + bits_per_pixel = min(bits_per_pixel, joiner_max_bpp); bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp); From patchwork Thu Jul 13 10:33:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4CACAC001DC for ; Thu, 13 Jul 2023 10:38:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 98E4410E69C; Thu, 13 Jul 2023 10:38:25 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8F21710E690; Thu, 13 Jul 2023 10:38:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689244701; x=1720780701; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2Kfon+yBCDR9TqvRgmL2Cbr8sZ/l3oox5nG+7vNsKwg=; b=RYAsoW+xvF/t2HeUz4FrDOiTpPEGuVZ5wf1s+bQmzyJLLWJWxBc7+hh5 l3yhyCSVns+aYWPd6B4mevVKzH7CQKfHHVOrM5K6FStW1RxGyLfS3EXom qLR4BBJJxZCj8rBRp0mq/SxrGQrMkIWPMxD7qGg6tHvnb4uJNec8hfPgH gYnPUJzU8PQy6zc9nMIvYfmFfyOChkztJbAFdTm/+l9uTgCXElHgaEWfO ekqpo+XEbDVNNpDZOPr9ioq4CsrXLTzOEyP7bELRgGsh/ngKCFWPaLgH2 N4Y4rL0os6qDzJEbw//nha7H5WyXJOB6uaXjP+xynbFj+KOf2w8/a6h03 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="428897708" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="428897708" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="895965468" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="895965468" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:18 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:45 +0530 Message-Id: <20230713103346.1163315-19-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 18/19] drm/i915/dp: Get optimal link config to have best compressed bpp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently, we take the max lane, rate and pipe bpp, to get the maximum compressed bpp possible. We then set the output bpp to this value. This patch provides support to have max bpp, min rate and min lanes, that can support the min compressed bpp. v2: -Avoid ending up with compressed bpp, same as pipe bpp. (Stan) -Fix the checks for limits->max/min_bpp while iterating over list of valid DSC bpcs. (Stan) v3: -Refactor the code to have pipe bpp/compressed bpp computation and slice count calculation separately for different cases. v4: -Separate the pipe_bpp calculation for eDP and DP. v5: -Get rid of magic numbers for max and min bpp, and improve documentation. (Stan). -Use functions for {src_sink}_{min_max}_compressed_bpp (Ville). v6: -Remove lines to set link config to max. v7: -Split the part to separate edp and dp functions for computing DSC BPP into separate patch. v8: -Separate mechanism to get compressed bpp for ICL,TGL and XELPD+. Signed-off-by: Ankit Nautiyal Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_dp.c | 294 +++++++++++++++++++++--- 1 file changed, 261 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 54fc60eb94a0..25a6c162332f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1688,6 +1688,231 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format); } +static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock, + u32 lane_count, u32 mode_clock, + enum intel_output_format output_format, + int timeslots) +{ + u32 available_bw, required_bw; + + available_bw = (link_clock * lane_count * timeslots) / 8; + required_bw = compressed_bpp * (intel_dp_mode_to_fec_clock(mode_clock)); + + return available_bw > required_bw; +} + +static int dsc_compute_link_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct link_config_limits *limits, + u16 compressed_bpp, + int timeslots) +{ + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; + int link_rate, lane_count; + int i; + + for (i = 0; i < intel_dp->num_common_rates; i++) { + link_rate = intel_dp_common_rate(intel_dp, i); + if (link_rate < limits->min_rate || link_rate > limits->max_rate) + continue; + + for (lane_count = limits->min_lane_count; + lane_count <= limits->max_lane_count; + lane_count <<= 1) { + if (!is_bw_sufficient_for_dsc_config(compressed_bpp, link_rate, lane_count, + adjusted_mode->clock, + pipe_config->output_format, + timeslots)) + continue; + + pipe_config->lane_count = lane_count; + pipe_config->port_clock = link_rate; + + return 0; + } + } + + return -EINVAL; +} + +static +u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + int bpc) +{ + u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd); + + if (max_bppx16) + return max_bppx16; + /* + * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate + * values as given in spec Table 2-157 DP v2.0 + */ + switch (pipe_config->output_format) { + case INTEL_OUTPUT_FORMAT_RGB: + case INTEL_OUTPUT_FORMAT_YCBCR444: + return (3 * bpc) << 4; + case INTEL_OUTPUT_FORMAT_YCBCR420: + return (3 * (bpc / 2)) << 4; + default: + MISSING_CASE(pipe_config->output_format); + break; + } + + return 0; +} + +static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) +{ + /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ + switch (pipe_config->output_format) { + case INTEL_OUTPUT_FORMAT_RGB: + case INTEL_OUTPUT_FORMAT_YCBCR444: + return 8; + case INTEL_OUTPUT_FORMAT_YCBCR420: + return 6; + default: + MISSING_CASE(pipe_config->output_format); + break; + } + + return 0; +} + +static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + int bpc) +{ + return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp, + pipe_config, bpc) >> 4; +} + +static int dsc_src_min_compressed_bpp(void) +{ + /* Min Compressed bpp supported by source is 8 */ + return 8; +} + +static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + /* + * Max Compressed bpp for Gen 13+ is 27bpp. + * For earlier platform is 23bpp. (Bspec:49259). + */ + if (DISPLAY_VER(i915) <= 12) + return 23; + else + return 27; +} + +/* + * From a list of valid compressed bpps try different compressed bpp and find a + * suitable link configuration that can support it. + */ +static int +icl_dsc_compute_link_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct link_config_limits *limits, + int dsc_max_bpp, + int dsc_min_bpp, + int pipe_bpp, + int timeslots) +{ + int i, ret; + + /* Compressed BPP should be less than the Input DSC bpp */ + dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); + + for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { + if (valid_dsc_bpp[i] < dsc_min_bpp || + valid_dsc_bpp[i] > dsc_max_bpp) + break; + + ret = dsc_compute_link_config(intel_dp, + pipe_config, + limits, + valid_dsc_bpp[i], + timeslots); + if (ret == 0) { + pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i]; + return 0; + } + } + + return -EINVAL; +} + +/* + * From XE_LPD onwards we supports compression bpps in steps of 1 up to + * uncompressed bpp-1. So we start from max compressed bpp and see if any + * link configuration is able to support that compressed bpp, if not we + * step down and check for lower compressed bpp. + */ +static int +xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct link_config_limits *limits, + int dsc_max_bpp, + int dsc_min_bpp, + int pipe_bpp, + int timeslots) +{ + u16 compressed_bpp; + int ret; + + /* Compressed BPP should be less than the Input DSC bpp */ + dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); + + for (compressed_bpp = dsc_max_bpp; + compressed_bpp >= dsc_min_bpp; + compressed_bpp--) { + ret = dsc_compute_link_config(intel_dp, + pipe_config, + limits, + compressed_bpp, + timeslots); + if (ret == 0) { + pipe_config->dsc.compressed_bpp = compressed_bpp; + return 0; + } + } + return -EINVAL; +} + +static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct link_config_limits *limits, + int pipe_bpp, + int timeslots) +{ + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; + int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; + int dsc_joiner_max_bpp; + + dsc_src_min_bpp = dsc_src_min_compressed_bpp(); + dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config); + dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); + + dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); + dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3); + dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; + + dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock, + adjusted_mode->hdisplay, + pipe_config->bigjoiner_pipes); + dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp); + + if (DISPLAY_VER(i915) >= 13) + return xelpd_dsc_compute_link_config(intel_dp, pipe_config, limits, + dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots); + return icl_dsc_compute_link_config(intel_dp, pipe_config, limits, + dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots); +} + static u8 intel_dp_dsc_min_src_input_bpc(struct drm_i915_private *i915) { @@ -1746,52 +1971,55 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, struct link_config_limits *limits, int timeslots) { - const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; struct drm_i915_private *i915 = dp_to_i915(intel_dp); - u16 output_bpp, dsc_max_compressed_bpp = 0; + u8 max_req_bpc = conn_state->max_requested_bpc; + u8 dsc_max_bpc, dsc_max_bpp; + u8 dsc_min_bpc, dsc_min_bpp; + u8 dsc_bpc[3] = {0}; int forced_bpp, pipe_bpp; + int num_bpc, i, ret; forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits); if (forced_bpp) { - pipe_bpp = forced_bpp; - } else { - pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, conn_state->max_requested_bpc); - - if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) { - drm_dbg_kms(&i915->drm, - "Computed BPC is not in DSC BPC limits\n"); - return -EINVAL; + ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, + limits, forced_bpp, timeslots); + if (ret == 0) { + pipe_config->pipe_bpp = forced_bpp; + return 0; } } - /* - * For now enable DSC for max link rate, max lane count. - * Optimize this later for the minimum possible link rate/lane count - * with DSC enabled for the requested mode. - */ - pipe_config->port_clock = limits->max_rate; - pipe_config->lane_count = limits->max_lane_count; - dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(i915, - pipe_config->port_clock, - pipe_config->lane_count, - adjusted_mode->crtc_clock, - adjusted_mode->crtc_hdisplay, - pipe_config->bigjoiner_pipes, - pipe_config->output_format, - pipe_bpp, - timeslots); - if (!dsc_max_compressed_bpp) { - drm_dbg_kms(&i915->drm, "Compressed BPP not supported\n"); + + dsc_max_bpc = intel_dp_dsc_min_src_input_bpc(i915); + if (!dsc_max_bpc) return -EINVAL; - } - output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); + dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc); + dsc_max_bpp = min(dsc_max_bpc * 3, limits->max_bpp); - pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_compressed_bpp, output_bpp); + dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915); + dsc_min_bpp = max(dsc_min_bpc * 3, limits->min_bpp); - pipe_config->pipe_bpp = pipe_bpp; + /* + * Get the maximum DSC bpc that will be supported by any valid + * link configuration and compressed bpp. + */ + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, dsc_bpc); + for (i = 0; i < num_bpc; i++) { + pipe_bpp = dsc_bpc[i] * 3; + if (pipe_bpp < dsc_min_bpp) + break; + if (pipe_bpp > dsc_max_bpp) + continue; + ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, + limits, pipe_bpp, timeslots); + if (ret == 0) { + pipe_config->pipe_bpp = pipe_bpp; + return 0; + } + } - return 0; + return -EINVAL; } static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, From patchwork Thu Jul 13 10:33:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13311822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13FE2C001DF for ; Thu, 13 Jul 2023 10:38:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C95310E6A9; Thu, 13 Jul 2023 10:38:27 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1A7A610E67A; Thu, 13 Jul 2023 10:38:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689244704; x=1720780704; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FcjoDEWwnVeuXUGgAC0tOnfbEoJMCLWciJ1Nglcj43c=; b=YpazkcOUDLfhxUA+8N0Me3zqzauuHqc3uJokn4d1pcKUh8AoDgJ7KBrz b8tURJz3d8GQe5QfAMUfqYj4l7oP2JSWwWXiY0LL3+PVdx1ojqOITkprs zbYSXHGljMlzO/kgLDgqEo5vemOHhY6fBmq3UO7CeZkXpZAgtynBvPhJM ZkUAYklNTvQCTuZr9gGodDxN9oxTzPtjQelNoeiJq+Gw547dhtmrIIsfx V8PE1mUNHxA+nsKsjDmc9nYQn7KicUllUXEawseza8bhvyke6GBA7C4hy YXPHIVQxphHGR9dDGMNLSOJ3SfetxDTE4kFjDfmKkwAwz05BJNMlLY64Q A==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="428897718" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="428897718" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="895965473" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="895965473" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 03:38:21 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Thu, 13 Jul 2023 16:03:46 +0530 Message-Id: <20230713103346.1163315-20-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> References: <20230713103346.1163315-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 19/19] drm/i915: Query compressed bpp properly using correct DPCD and DP Spec info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Stanislav Lisovskiy Currently we seem to be using wrong DPCD register for reading compressed bpps, reading min/max input bpc instead of compressed bpp. Fix that, so that we now apply min/max compressed bpp limitations we get from DP Spec Table 2-157 DP v2.0 and/or correspondent DPCD register DP_DSC_MAX_BITS_PER_PIXEL_LOW/HIGH. This might also allow us to get rid of an ugly compressed bpp recalculation, which we had to add to make some MST hubs usable. v2: - Fix operator precedence v3: - Added debug info about compressed bpps v4: - Don't try to intersect Sink input bpp and compressed bpps. v5: - Decrease step while looking for suitable compressed bpp to accommodate. v6: - Use helper for getting min and max compressed_bpp (Ankit) v7: - Fix checkpatch warning (Ankit) Signed-off-by: Stanislav Lisovskiy Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 14 +++--- drivers/gpu/drm/i915/display/intel_dp.h | 4 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 47 +++++++++------------ 3 files changed, 32 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 25a6c162332f..ce8b28ca1cfa 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1762,7 +1762,7 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp, return 0; } -static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) +int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) { /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ switch (pipe_config->output_format) { @@ -1779,9 +1779,9 @@ static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) return 0; } -static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config, - int bpc) +int intel_dp_dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + int bpc) { return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp, pipe_config, bpc) >> 4; @@ -1894,11 +1894,13 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, int dsc_joiner_max_bpp; dsc_src_min_bpp = dsc_src_min_compressed_bpp(); - dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config); + dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config); dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); - dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3); + dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp, + pipe_config, + pipe_bpp / 3); dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock, diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 788a577ebe16..f29e48028f39 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -114,6 +114,10 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, enum intel_output_format output_format, u32 pipe_bpp, u32 timeslots); +int intel_dp_dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config); +int intel_dp_dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + int bpc); u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, int mode_hdisplay, bool bigjoiner); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 3eb085fbc7c8..06a456517383 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -101,6 +101,9 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, crtc_state->lane_count); } + drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n", + min_bpp, max_bpp); + for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) { drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); @@ -194,8 +197,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, u8 dsc_bpc[3] = {0}; int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp; u8 dsc_max_bpc; - bool need_timeslot_recalc = false; - u32 last_compressed_bpp; + int min_compressed_bpp, max_compressed_bpp; /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ if (DISPLAY_VER(i915) >= 12) @@ -231,34 +233,25 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, if (max_bpp > sink_max_bpp) max_bpp = sink_max_bpp; - slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp, - min_bpp, limits, - conn_state, 2 * 3, true); - - if (slots < 0) - return slots; - - last_compressed_bpp = crtc_state->dsc.compressed_bpp; + max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(intel_dp, + crtc_state, + max_bpp / 3); + min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state); + drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n", + min_compressed_bpp, max_compressed_bpp); - crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, - last_compressed_bpp, - crtc_state->pipe_bpp); + /* Align compressed bpps according to our own constraints */ + max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp, + crtc_state->pipe_bpp); + min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp, + crtc_state->pipe_bpp); - if (crtc_state->dsc.compressed_bpp != last_compressed_bpp) - need_timeslot_recalc = true; + slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp, + min_compressed_bpp, limits, + conn_state, 1, true); - /* - * Apparently some MST hubs dislike if vcpi slots are not matching precisely - * the actual compressed bpp we use. - */ - if (need_timeslot_recalc) { - slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, - crtc_state->dsc.compressed_bpp, - crtc_state->dsc.compressed_bpp, - limits, conn_state, 2 * 3, true); - if (slots < 0) - return slots; - } + if (slots < 0) + return slots; intel_link_compute_m_n(crtc_state->dsc.compressed_bpp, crtc_state->lane_count,