From patchwork Thu Jul 13 12:45:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13311980 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99D54C001DF for ; Thu, 13 Jul 2023 12:46:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233910AbjGMMqw (ORCPT ); Thu, 13 Jul 2023 08:46:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233560AbjGMMqu (ORCPT ); Thu, 13 Jul 2023 08:46:50 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5206926B1; Thu, 13 Jul 2023 05:46:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689252386; x=1720788386; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=32kRKfdMgDzPzA7zG83cMwuqvw0HkhDshGCOND8kKRk=; b=fxSIoaW67HJ4JXON+sFsfRe3SAj+egnPB3bO2NSP58lcVmRfsFqHc5g+ MMusC4bspqOJ9p3mQOj4hRoaZkCxPFEGGJYHaW36oCaBXPHJAKbc64R8d J3elUik7h1YyO6xnpfOljW59k6rTzMFJijA1cA5H+LlofdSYvxNwOaNM3 8Bj9YxFW2D/LcCMh0C2YiPl3x9ahohnd7VzUwhsek73WpvHG1kRYSDIVZ 09IE4BWc2wM5yFNlNnfuF426g4Va9BO2ZzjkB6Gp45SWDQnjM0DNn/RuH NaEce348aD8uayEU3GzZ2Hs7U/dtn8FpAhEJh3nhcCwtvjtojJ2w0cd+G Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10770"; a="367796963" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="367796963" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 05:46:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10770"; a="757144480" X-IronPort-AV: E=Sophos;i="6.01,202,1684825200"; d="scan'208";a="757144480" Received: from ijarvine-mobl2.ger.corp.intel.com ([10.251.222.39]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2023 05:46:07 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Emmanuel Grumbach , "Rafael J . Wysocki" , Heiner Kallweit , Lukas Wunner , Saeed Mahameed , Leon Romanovsky , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Moshe Shemesh , netdev@vger.kernel.org, linux-rdma@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Dean Luick , Andy Shevchenko , =?utf-8?q?Jonas_Dre?= =?utf-8?q?=C3=9Fler?= , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Moshe Shemesh , Simon Horman , stable@vger.kernel.org Subject: [PATCH v4 07/11] net/mlx5: Use RMW accessors for changing LNKCTL Date: Thu, 13 Jul 2023 15:45:01 +0300 Message-Id: <20230713124505.94866-8-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230713124505.94866-1-ilpo.jarvinen@linux.intel.com> References: <20230713124505.94866-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org Don't assume that only the driver would be accessing LNKCTL of the upstream bridge. ASPM policy changes can trigger write to LNKCTL outside of driver's control. Use RMW capability accessors which do proper locking to avoid losing concurrent updates to the register value. Fixes: eabe8e5e88f5 ("net/mlx5: Handle sync reset now event") Suggested-by: Lukas Wunner Signed-off-by: Ilpo Järvinen Reviewed-by: Moshe Shemesh Reviewed-by: Simon Horman Cc: stable@vger.kernel.org --- drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c index 4804990b7f22..99dcbd006357 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c @@ -384,16 +384,11 @@ static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev) pci_cfg_access_lock(sdev); } /* PCI link toggle */ - err = pci_read_config_word(bridge, cap + PCI_EXP_LNKCTL, ®16); - if (err) - return err; - reg16 |= PCI_EXP_LNKCTL_LD; - err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16); + err = pcie_capability_set_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD); if (err) return err; msleep(500); - reg16 &= ~PCI_EXP_LNKCTL_LD; - err = pci_write_config_word(bridge, cap + PCI_EXP_LNKCTL, reg16); + err = pcie_capability_clear_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD); if (err) return err;