From patchwork Sun Jul 16 14:14:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13314815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CF91C0015E for ; Sun, 16 Jul 2023 14:14:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230070AbjGPOOq (ORCPT ); Sun, 16 Jul 2023 10:14:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229516AbjGPOOp (ORCPT ); Sun, 16 Jul 2023 10:14:45 -0400 Received: from h1.cmg1.smtp.forpsi.com (h1.cmg1.smtp.forpsi.com [81.2.195.162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4A4910C8 for ; Sun, 16 Jul 2023 07:14:43 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id L2WGqBW0BPm6CL2WHqIO7k; Sun, 16 Jul 2023 16:14:42 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1689516882; bh=Kb0mBdIxKMCU55eZrjc378rG9a3QsYq/13BrO+TSaSM=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=WeKuOlaqZQka1kjz4bu7/HOp3zsNgGsDQF3S3y76u+WDe+sdPmhiqM4C3hItB92Nl P3456Pi+0z+FlfQ7CRzVD/SHEhC34QL8iJpgeJmKDsmE5ewU7DEwn7pYlrx7dH6nqb qNJSTSmPXsN62CS2BKBLB3hRdDfNCRm6O5NOpaD7Ekrcmw3JS0nzEUxG9MTp27qv1x tlHHSSDpsmrzkBLzHe505ys2UmSwMMcIaWA1bEUR5HJcvrQE6a9AktG/cC1Aqcz2zT ED7chGk1Auiw6U9Sr0vjrg5CCfd4U0K6ANLHGifnLzi5qIo/ObAfq5YoPJYDpOt7K9 UaHCIZE+TTIiA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1689516882; bh=Kb0mBdIxKMCU55eZrjc378rG9a3QsYq/13BrO+TSaSM=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=WeKuOlaqZQka1kjz4bu7/HOp3zsNgGsDQF3S3y76u+WDe+sdPmhiqM4C3hItB92Nl P3456Pi+0z+FlfQ7CRzVD/SHEhC34QL8iJpgeJmKDsmE5ewU7DEwn7pYlrx7dH6nqb qNJSTSmPXsN62CS2BKBLB3hRdDfNCRm6O5NOpaD7Ekrcmw3JS0nzEUxG9MTp27qv1x tlHHSSDpsmrzkBLzHe505ys2UmSwMMcIaWA1bEUR5HJcvrQE6a9AktG/cC1Aqcz2zT ED7chGk1Auiw6U9Sr0vjrg5CCfd4U0K6ANLHGifnLzi5qIo/ObAfq5YoPJYDpOt7K9 UaHCIZE+TTIiA== Date: Sun, 16 Jul 2023 16:14:40 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v4 1/6] usb: dwc3: dwc3-octeon: Convert to glue driver Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfOx5menqH+89737dpJMGT9P1M+k2b2qk5TezGOUNcK0wBcQiKAWuC9htjbLr9IXYQjK8nDEYWC7gtH/1cMY7AuGbpy0p0DUk8uY+EjrcMh6h4SdTv4yP BPLmMeJmGprRvlpR6eVd/AQNZ7TvwbeVFA9w1MoA7l/dLItaz+O3EYq5bd8M5dpHjVwlR2M5UMjudvZQh20q8oOaAz6sdm/iDLIRK81VgBjW0HGn+nbxs1np gVS7i8EOiWKQOUhQJT457FGsd8Um6ieK2VIDDEqzrspfbuNDX+A5wfuzPrK7lEGPrWHjXG14ojK47iG9fohn9aLbDueqZs26LSioGo7odCZ3iZxGZlQkuleT vjvffJpS Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl DWC3 as implemented in Cavium SoC is using UCTL bridge unit between I/O interconnect and USB controller. Currently there is no bond with dwc3 core code, so if anything goes wrong in UCTL setup dwc3 is left in reset, which leads to bus error while trying to read any device register. Thus any failure in UCTL initialization ends with kernel panic. To avoid this move Octeon DWC3 glue code from arch/mips and make it proper glue driver which is used instead of dwc3-of-simple. Signed-off-by: Ladislav Michl Acked-by: Thomas Bogendoerfer Acked-by: Thinh Nguyen --- CHANGES: - v2: squashed move and glue conversion patch, fixed sparse warning and formatting issue. Set private data at the end of probe. Clear drvdata on remove. Added host mode only notice. Collected ack for move from arch/mips. - v3: more descriptive commit message, dropped unrelated changes - v4: rename dwc3_data to dwc3_octeon, collect Thinh's ack. arch/mips/cavium-octeon/Makefile | 1 - arch/mips/cavium-octeon/octeon-platform.c | 1 - drivers/usb/dwc3/Kconfig | 10 ++ drivers/usb/dwc3/Makefile | 1 + .../usb/dwc3/dwc3-octeon.c | 105 ++++++++++-------- drivers/usb/dwc3/dwc3-of-simple.c | 1 - 6 files changed, 68 insertions(+), 51 deletions(-) rename arch/mips/cavium-octeon/octeon-usb.c => drivers/usb/dwc3/dwc3-octeon.c (91%) diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 7c02e542959a..2a5926578841 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -18,4 +18,3 @@ obj-y += crypto/ obj-$(CONFIG_MTD) += flash_setup.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o -obj-$(CONFIG_USB) += octeon-usb.o diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index ce05c0dd3acd..235c77ce7b18 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -450,7 +450,6 @@ static const struct of_device_id octeon_ids[] __initconst = { { .compatible = "cavium,octeon-3860-bootbus", }, { .compatible = "cavium,mdio-mux", }, { .compatible = "gpio-leds", }, - { .compatible = "cavium,octeon-7130-usb-uctl", }, {}, }; diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index be954a9abbe0..98efcbb76c88 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -168,4 +168,14 @@ config USB_DWC3_AM62 The Designware Core USB3 IP is programmed to operate in in USB 2.0 mode only. Say 'Y' or 'M' here if you have one such device + +config USB_DWC3_OCTEON + tristate "Cavium Octeon Platforms" + depends on CAVIUM_OCTEON_SOC || COMPILE_TEST + default USB_DWC3 + help + Support Cavium Octeon platforms with DesignWare Core USB3 IP. + Only the host mode is currently supported. + Say 'Y' or 'M' here if you have one such device. + endif diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 9f66bd82b639..fe1493d4bbe5 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -54,3 +54,4 @@ obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o +obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/drivers/usb/dwc3/dwc3-octeon.c similarity index 91% rename from arch/mips/cavium-octeon/octeon-usb.c rename to drivers/usb/dwc3/dwc3-octeon.c index 2add435ad038..7134cdfc0fb6 100644 --- a/arch/mips/cavium-octeon/octeon-usb.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -187,7 +187,10 @@ #define USBDRD_UCTL_ECC 0xf0 #define USBDRD_UCTL_SPARE1 0xf8 -static DEFINE_MUTEX(dwc3_octeon_clocks_mutex); +struct dwc3_octeon { + struct device *dev; + void __iomem *base; +}; #ifdef CONFIG_CAVIUM_OCTEON_SOC #include @@ -233,6 +236,11 @@ static inline uint64_t dwc3_octeon_readq(void __iomem *addr) static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) { } static inline void dwc3_octeon_config_gpio(int index, int gpio) { } + +static uint64_t octeon_get_io_clock_rate(void) +{ + return 150000000; +} #endif static int dwc3_octeon_get_divider(void) @@ -494,58 +502,59 @@ static void __init dwc3_octeon_phy_reset(void __iomem *base) dwc3_octeon_writeq(uctl_ctl_reg, val); } -static int __init dwc3_octeon_device_init(void) +static int dwc3_octeon_probe(struct platform_device *pdev) { - const char compat_node_name[] = "cavium,octeon-7130-usb-uctl"; - struct platform_device *pdev; - struct device_node *node; - struct resource *res; - void __iomem *base; + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct dwc3_octeon *octeon; + int err; - /* - * There should only be three universal controllers, "uctl" - * in the device tree. Two USB and a SATA, which we ignore. - */ - node = NULL; - do { - node = of_find_node_by_name(node, "uctl"); - if (!node) - return -ENODEV; - - if (of_device_is_compatible(node, compat_node_name)) { - pdev = of_find_device_by_node(node); - if (!pdev) - return -ENODEV; - - /* - * The code below maps in the registers necessary for - * setting up the clocks and reseting PHYs. We must - * release the resources so the dwc3 subsystem doesn't - * know the difference. - */ - base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (IS_ERR(base)) { - put_device(&pdev->dev); - return PTR_ERR(base); - } + octeon = devm_kzalloc(dev, sizeof(*octeon), GFP_KERNEL); + if (!octeon) + return -ENOMEM; - mutex_lock(&dwc3_octeon_clocks_mutex); - if (dwc3_octeon_clocks_start(&pdev->dev, base) == 0) - dev_info(&pdev->dev, "clocks initialized.\n"); - dwc3_octeon_set_endian_mode(base); - dwc3_octeon_phy_reset(base); - mutex_unlock(&dwc3_octeon_clocks_mutex); - devm_iounmap(&pdev->dev, base); - devm_release_mem_region(&pdev->dev, res->start, - resource_size(res)); - put_device(&pdev->dev); - } - } while (node != NULL); + octeon->dev = dev; + octeon->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(octeon->base)) + return PTR_ERR(octeon->base); - return 0; + err = dwc3_octeon_clocks_start(dev, octeon->base); + if (err) + return err; + + dwc3_octeon_set_endian_mode(octeon->base); + dwc3_octeon_phy_reset(octeon->base); + + platform_set_drvdata(pdev, octeon); + + return of_platform_populate(node, NULL, NULL, dev); +} + +static void dwc3_octeon_remove(struct platform_device *pdev) +{ + struct dwc3_octeon *octeon = platform_get_drvdata(pdev); + + of_platform_depopulate(octeon->dev); + platform_set_drvdata(pdev, NULL); } -device_initcall(dwc3_octeon_device_init); +static const struct of_device_id dwc3_octeon_of_match[] = { + { .compatible = "cavium,octeon-7130-usb-uctl" }, + { }, +}; +MODULE_DEVICE_TABLE(of, dwc3_octeon_of_match); + +static struct platform_driver dwc3_octeon_driver = { + .probe = dwc3_octeon_probe, + .remove_new = dwc3_octeon_remove, + .driver = { + .name = "dwc3-octeon", + .of_match_table = dwc3_octeon_of_match, + }, +}; +module_platform_driver(dwc3_octeon_driver); + +MODULE_ALIAS("platform:dwc3-octeon"); MODULE_AUTHOR("David Daney "); MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("USB driver for OCTEON III SoC"); +MODULE_DESCRIPTION("DesignWare USB3 OCTEON III Glue Layer"); diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c index 7e6ad8fe61a5..d1539fc9eabd 100644 --- a/drivers/usb/dwc3/dwc3-of-simple.c +++ b/drivers/usb/dwc3/dwc3-of-simple.c @@ -170,7 +170,6 @@ static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = { static const struct of_device_id of_dwc3_simple_match[] = { { .compatible = "rockchip,rk3399-dwc3" }, - { .compatible = "cavium,octeon-7130-usb-uctl" }, { .compatible = "sprd,sc9860-dwc3" }, { .compatible = "allwinner,sun50i-h6-dwc3" }, { .compatible = "hisilicon,hi3670-dwc3" }, From patchwork Sun Jul 16 14:15:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13314816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1147EB64DD for ; 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a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1689516921; bh=7mmkvQv6aEFrTdJigTMeMePl0wk5IoScoajAYdJEYC4=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=FxqRW/XS/Zbp7hFiCpK/SBXoX9c4kh3A5WD7vSbBpax6ZqcSvpADJlLxDob0KSZNw IlJt455CkvilYnkZKiEUSkFpZ2wVUPzQBFyY8U0W97PCebfW90nD7dKaB7/9EFo8LH LymFXVdThgFunD9x+UK+Gu9aObbp64KB27aZhxO82i0gfEJQr+GIVbe/0C9MkqIgMh yt7Aq/iKUovWQNdtISvjqsq9ghlN3EsRatmiNiSIYZWkYAEiPLRMjqRGM1fHZNyQOp uOu2uKhy2saQZPECK9pN9iVlziAzofW4sUV+N95RZjnXnWUyfw6l29TIN2GFQmDyMJ fj6Py+ia0FQ4w== Date: Sun, 16 Jul 2023 16:15:19 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v4 2/6] usb: dwc3: dwc3-octeon: Pass dwc3_octeon to setup functions Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfExOYcVFDVq8z2WsAQmrYoo7nfvrPM4OGIU9aUZLnLohU6vv53ZgWhOQ8pe4VLjD5iuIwKc2ACgqRSOc8I3y+om9kT/xmEHc34TPL28QDgKhZeVxUv+s D70qYFfSV/ZeOVxu02TqWMFtBfGOvQF9WDdVkY26bzW0G/Cko5YjaRLvV9eakqBtBkAIdttPS5b9yx5kmKw33N+hW9gaMwz2qYxC5VKR2OMqZZDeRCjDiPxd ub/R7fq2vGYP8UJBqbz0Enu2JPRMCGDqA3vPbCObrq4mn9+PBLLCRmb5OeL+WknCYoGCBMmB0W6s8FhESnwI0WAduw6r8d/ElIQ2mSXEsT48OknipSRli++D H+P7NpYP Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Pass dwc3_octeon instead of just the base. It fits with the function names and it requires less change in the future if access to dwc3_octeon is needed. Signed-off-by: Ladislav Michl Reviewed-by: Philippe Mathieu-Daudé --- CHANGES: - v4: new patch drivers/usb/dwc3/dwc3-octeon.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 7134cdfc0fb6..20440c4d2366 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -300,12 +300,13 @@ static int dwc3_octeon_config_power(struct device *dev, void __iomem *base) return 0; } -static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) +static int dwc3_octeon_clocks_start(struct dwc3_octeon *octeon) { int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; u32 clock_rate; u64 val; - void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; + struct device *dev = octeon->dev; + void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL; if (dev->of_node) { const char *ss_clock_type; @@ -452,8 +453,8 @@ static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) /* Step 8b: Wait 10 controller-clock cycles. */ udelay(10); - /* Steo 8c: Setup power-power control. */ - if (dwc3_octeon_config_power(dev, base)) + /* Step 8c: Setup power control. */ + if (dwc3_octeon_config_power(dev, octeon->base)) return -EINVAL; /* Step 8d: Deassert UAHC reset signal. */ @@ -477,10 +478,10 @@ static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) return 0; } -static void __init dwc3_octeon_set_endian_mode(void __iomem *base) +static void dwc3_octeon_set_endian_mode(struct dwc3_octeon *octeon) { u64 val; - void __iomem *uctl_shim_cfg_reg = base + USBDRD_UCTL_SHIM_CFG; + void __iomem *uctl_shim_cfg_reg = octeon->base + USBDRD_UCTL_SHIM_CFG; val = dwc3_octeon_readq(uctl_shim_cfg_reg); val &= ~USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE; @@ -492,10 +493,10 @@ static void __init dwc3_octeon_set_endian_mode(void __iomem *base) dwc3_octeon_writeq(uctl_shim_cfg_reg, val); } -static void __init dwc3_octeon_phy_reset(void __iomem *base) +static void dwc3_octeon_phy_reset(struct dwc3_octeon *octeon) { u64 val; - void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; + void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL; val = dwc3_octeon_readq(uctl_ctl_reg); val &= ~USBDRD_UCTL_CTL_UPHY_RST; @@ -518,12 +519,12 @@ static int dwc3_octeon_probe(struct platform_device *pdev) if (IS_ERR(octeon->base)) return PTR_ERR(octeon->base); - err = dwc3_octeon_clocks_start(dev, octeon->base); + err = dwc3_octeon_clocks_start(octeon); if (err) return err; - dwc3_octeon_set_endian_mode(octeon->base); - dwc3_octeon_phy_reset(octeon->base); + dwc3_octeon_set_endian_mode(octeon); + dwc3_octeon_phy_reset(octeon); platform_set_drvdata(pdev, octeon); From patchwork Sun Jul 16 14:15:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13314817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A46E1C0015E for ; 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a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1689516953; bh=3BnJF1XmIFzq3a8gbpm23EgkT/fWjHnjATPV1mDlvX4=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=wfLXsA97gvIvkiNe8vEdR9hFu03kZQD9v2QaAqGCG0NyeaTTKv4weTEbj7revCKkW La/ai6oT+rHguSZGWZHJfT2aomjGNbEAI/9ail3wp5/10NJyq2Ss63j2FkhzHdhBwy yL9CtnBLZzbfLlW7hhbv+6Yl6jyIT7sHagrUhmdqR4E3oHwsu+YZyYPCF0fsyPRAEC hLhSQWrFLSYP9PC4xv/+alq6v3FJt+eOfzLaLF3ty4f/Ai/1UfhXULC7wSGSfJltYe qBaC0H6eDKyzd1FGlpQo58isHxpT8yNw1dVdfkP5ocg6gYuoB9kpqetpHoleQY7E7u lnR0gILuvA9uQ== Date: Sun, 16 Jul 2023 16:15:52 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v4 3/6] usb: dwc3: dwc3-octeon: Avoid half-initialized controller state Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfFCEGxUdkkmm56OpnYW5hKVBJscVKG5jkOuXNyYVQ8Ii+tDt6lQutj7tiDNVtuQsgoDdiWzYOdochmbKJhBXfoHZqAOfWR0P0zg3WXQVIlw3lWiDzCnn mLJFeXCPzrIM6kAg8hNj/7w8/8ZjxsuX9HQu4fXYEoxZI+IUNMNr5BYJZ/hhdfVPJbOMImkdZQ5Q3HQ8R2mixAE8ph9cEt7hgi2jQwhD+l7Ya57I7G4uA8xW qdHHl9me0iyYUft6EKlxUhoSSCT6epIVDyoj3yrX3S7eCL24+yc0m+nr8yFHGUOsFGgAWshY6uUSJ8vTyYtJOi2SqMJ2sR6hpE/0ZHjxbWG+F0EM1/EJQizq Oc6dIulu Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Power gpio configuration is done from the middle of dwc3_octeon_clocks_start leaving hardware in half-initialized state if it fails. As that indicates dwc3_octeon_clocks_start does more than just initialize the clocks rename it appropriately and verify power gpio configuration in advance at the beginning of device probe. Signed-off-by: Ladislav Michl --- CHANGES: - v4: new patch drivers/usb/dwc3/dwc3-octeon.c | 90 ++++++++++++++++------------------ 1 file changed, 43 insertions(+), 47 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 20440c4d2366..d6ad6fbb6c12 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -192,6 +192,8 @@ struct dwc3_octeon { void __iomem *base; }; +#define DWC3_GPIO_POWER_NONE (-1) + #ifdef CONFIG_CAVIUM_OCTEON_SOC #include static inline uint64_t dwc3_octeon_readq(void __iomem *addr) @@ -258,55 +260,15 @@ static int dwc3_octeon_get_divider(void) return div; } -static int dwc3_octeon_config_power(struct device *dev, void __iomem *base) -{ - uint32_t gpio_pwr[3]; - int gpio, len, power_active_low; - struct device_node *node = dev->of_node; - u64 val; - void __iomem *uctl_host_cfg_reg = base + USBDRD_UCTL_HOST_CFG; - - if (of_find_property(node, "power", &len) != NULL) { - if (len == 12) { - of_property_read_u32_array(node, "power", gpio_pwr, 3); - power_active_low = gpio_pwr[2] & 0x01; - gpio = gpio_pwr[1]; - } else if (len == 8) { - of_property_read_u32_array(node, "power", gpio_pwr, 2); - power_active_low = 0; - gpio = gpio_pwr[1]; - } else { - dev_err(dev, "invalid power configuration\n"); - return -EINVAL; - } - dwc3_octeon_config_gpio(((u64)base >> 24) & 1, gpio); - - /* Enable XHCI power control and set if active high or low. */ - val = dwc3_octeon_readq(uctl_host_cfg_reg); - val |= USBDRD_UCTL_HOST_PPC_EN; - if (power_active_low) - val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; - else - val |= USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; - dwc3_octeon_writeq(uctl_host_cfg_reg, val); - } else { - /* Disable XHCI power control and set if active high. */ - val = dwc3_octeon_readq(uctl_host_cfg_reg); - val &= ~USBDRD_UCTL_HOST_PPC_EN; - val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; - dwc3_octeon_writeq(uctl_host_cfg_reg, val); - dev_info(dev, "power control disabled\n"); - } - return 0; -} - -static int dwc3_octeon_clocks_start(struct dwc3_octeon *octeon) +static int dwc3_octeon_setup(struct dwc3_octeon *octeon, + int power_gpio, int power_active_low) { int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; u32 clock_rate; u64 val; struct device *dev = octeon->dev; void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL; + void __iomem *uctl_host_cfg_reg = octeon->base + USBDRD_UCTL_HOST_CFG; if (dev->of_node) { const char *ss_clock_type; @@ -454,8 +416,21 @@ static int dwc3_octeon_clocks_start(struct dwc3_octeon *octeon) udelay(10); /* Step 8c: Setup power control. */ - if (dwc3_octeon_config_power(dev, octeon->base)) - return -EINVAL; + val = dwc3_octeon_readq(uctl_host_cfg_reg); + val |= USBDRD_UCTL_HOST_PPC_EN; + if (power_gpio == DWC3_GPIO_POWER_NONE) { + val &= ~USBDRD_UCTL_HOST_PPC_EN; + } else { + val |= USBDRD_UCTL_HOST_PPC_EN; + dwc3_octeon_config_gpio(((__force u64)octeon->base >> 24) & 1, + power_gpio); + dev_dbg(dev, "power control is using gpio%d\n", power_gpio); + } + if (power_active_low) + val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; + else + val |= USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; + dwc3_octeon_writeq(uctl_host_cfg_reg, val); /* Step 8d: Deassert UAHC reset signal. */ val = dwc3_octeon_readq(uctl_ctl_reg); @@ -508,7 +483,28 @@ static int dwc3_octeon_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *node = dev->of_node; struct dwc3_octeon *octeon; - int err; + int power_active_low, power_gpio; + int err, len; + + power_gpio = DWC3_GPIO_POWER_NONE; + power_active_low = 0; + if (of_find_property(node, "power", &len)) { + u32 gpio_pwr[3]; + + switch (len) { + case 8: + of_property_read_u32_array(node, "power", gpio_pwr, 2); + break; + case 12: + of_property_read_u32_array(node, "power", gpio_pwr, 3); + power_active_low = gpio_pwr[2] & 0x01; + break; + default: + dev_err(dev, "invalid power configuration\n"); + return -EINVAL; + } + power_gpio = gpio_pwr[1]; + } octeon = devm_kzalloc(dev, sizeof(*octeon), GFP_KERNEL); if (!octeon) @@ -519,7 +515,7 @@ static int dwc3_octeon_probe(struct platform_device *pdev) if (IS_ERR(octeon->base)) return PTR_ERR(octeon->base); - err = dwc3_octeon_clocks_start(octeon); + err = dwc3_octeon_setup(octeon, power_gpio, power_active_low); if (err) return err; From patchwork Sun Jul 16 14:16:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13314821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AB38C0015E for ; Sun, 16 Jul 2023 14:16:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230095AbjGPOQh (ORCPT ); Sun, 16 Jul 2023 10:16:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229451AbjGPOQg (ORCPT ); Sun, 16 Jul 2023 10:16:36 -0400 Received: from h2.cmg1.smtp.forpsi.com (h2.cmg1.smtp.forpsi.com [81.2.195.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BABA410C8 for ; Sun, 16 Jul 2023 07:16:34 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id L2Y5qBWyDPm6CL2Y6qIOFa; Sun, 16 Jul 2023 16:16:34 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1689516994; bh=/lBBkjsctJRA0kx3xuSbPshM/xL6Z2izbWU0cogKuaE=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=E4MkG5vBL4zuyP+HQZeYdbIWr5rNjoC3AyOTOgRYS1uTgE5hB9ghweLM4q4jwXUgJ J2iBQqYUhI8edc47G12aNUYBI+zNBt++tTK6mfePGbn7ZHBfAHOpHHirzEBm98VnQn wnPktNaw5sVJtW3IjzeyUv8Wh1bricxJsHreAug83YHJNs4M3qBB7Nkk6bWFfqzYQi yvZuzazWcW84sep2wMrK/9ZhQXVEuMd07YAMW9W3d2eEGd2dSctbGazXgTAFsve7mx tb9EvuQEw/7GsOtNxgEWlNnIM2EXmGwAIsOlP0dhQQk/G6IYb0kOpL4APBHrsb8GkF k0/ecfPANOjug== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1689516994; bh=/lBBkjsctJRA0kx3xuSbPshM/xL6Z2izbWU0cogKuaE=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=E4MkG5vBL4zuyP+HQZeYdbIWr5rNjoC3AyOTOgRYS1uTgE5hB9ghweLM4q4jwXUgJ J2iBQqYUhI8edc47G12aNUYBI+zNBt++tTK6mfePGbn7ZHBfAHOpHHirzEBm98VnQn wnPktNaw5sVJtW3IjzeyUv8Wh1bricxJsHreAug83YHJNs4M3qBB7Nkk6bWFfqzYQi yvZuzazWcW84sep2wMrK/9ZhQXVEuMd07YAMW9W3d2eEGd2dSctbGazXgTAFsve7mx tb9EvuQEw/7GsOtNxgEWlNnIM2EXmGwAIsOlP0dhQQk/G6IYb0kOpL4APBHrsb8GkF k0/ecfPANOjug== Date: Sun, 16 Jul 2023 16:16:33 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v4 4/6] usb: dwc3: dwc3-octeon: Move node parsing into driver probe Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfJuIqDjlZUAFxO6uMCecrhDmveaUyTypI0h03EwWVOzTqM0cbHkP5qHCoZR6dYlBaUBrt6XvIDF+XxESM7apwlT6AE1xPLdIdS29pgHNlNpir1j1g9wm wnq20UB2RPzE1pHzXMxv5faZZwNk2Cqigm4B8kfbpi5lX92rg3T5qLz+5L8Xtmgx1e7BIjW+vo82ck5qKeXVuP65eywraDvbHx2nESORWpYakuBLnlMQm2KX /SC4SN5bn82AyXiEZZB++9uoVah6rYGMJSkV8Z/BlbXkoTNugohxtV0kyZbimkz9poWcsjVlzyjoQvac/427GJ/qHQO8ptdGqO8LcJiAkW/xvVmUPsBvXd4x XLJF5Rm3 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Parse and verify device tree node first, then setup UCTL bridge using verified values. This avoids needless allocations in case DT misconfiguration was found in the middle of setup. Signed-off-by: Ladislav Michl --- CHANGES: - v2: if else block bracket according CodingStyle - v3: more descriptive commit message, power gpio parsing in probe too, checkpatch --strict passed - v4: move changes unrelated to parsing move into separate patches drivers/usb/dwc3/dwc3-octeon.c | 135 +++++++++++++++------------------ 1 file changed, 60 insertions(+), 75 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index d6ad6fbb6c12..45726b39adab 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -261,69 +261,15 @@ static int dwc3_octeon_get_divider(void) } static int dwc3_octeon_setup(struct dwc3_octeon *octeon, + int ref_clk_sel, int ref_clk_fsel, int mpll_mul, int power_gpio, int power_active_low) { - int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; - u32 clock_rate; u64 val; + int div; struct device *dev = octeon->dev; void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL; void __iomem *uctl_host_cfg_reg = octeon->base + USBDRD_UCTL_HOST_CFG; - if (dev->of_node) { - const char *ss_clock_type; - const char *hs_clock_type; - - i = of_property_read_u32(dev->of_node, - "refclk-frequency", &clock_rate); - if (i) { - dev_err(dev, "No UCTL \"refclk-frequency\"\n"); - return -EINVAL; - } - i = of_property_read_string(dev->of_node, - "refclk-type-ss", &ss_clock_type); - if (i) { - dev_err(dev, "No UCTL \"refclk-type-ss\"\n"); - return -EINVAL; - } - i = of_property_read_string(dev->of_node, - "refclk-type-hs", &hs_clock_type); - if (i) { - dev_err(dev, "No UCTL \"refclk-type-hs\"\n"); - return -EINVAL; - } - if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { - if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) - ref_clk_sel = 0; - else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) - ref_clk_sel = 2; - else - dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", - hs_clock_type); - } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { - if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) - ref_clk_sel = 1; - else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) - ref_clk_sel = 3; - else { - dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", - hs_clock_type); - ref_clk_sel = 3; - } - } else - dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n", - ss_clock_type); - - if ((ref_clk_sel == 0 || ref_clk_sel == 1) && - (clock_rate != 100000000)) - dev_warn(dev, "Invalid UCTL clock rate of %u, using 100000000 instead\n", - clock_rate); - - } else { - dev_err(dev, "No USB UCTL device node\n"); - return -EINVAL; - } - /* * Step 1: Wait for all voltages to be stable...that surely * happened before starting the kernel. SKIP @@ -367,24 +313,6 @@ static int dwc3_octeon_setup(struct dwc3_octeon *octeon, val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL; val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel); - ref_clk_fsel = 0x07; - switch (clock_rate) { - default: - dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", - clock_rate); - fallthrough; - case 100000000: - mpll_mul = 0x19; - if (ref_clk_sel < 2) - ref_clk_fsel = 0x27; - break; - case 50000000: - mpll_mul = 0x32; - break; - case 125000000: - mpll_mul = 0x28; - break; - } val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL; val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel); @@ -483,8 +411,64 @@ static int dwc3_octeon_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *node = dev->of_node; struct dwc3_octeon *octeon; + const char *hs_clock_type, *ss_clock_type; + int ref_clk_sel, ref_clk_fsel, mpll_mul; int power_active_low, power_gpio; int err, len; + u32 clock_rate; + + if (of_property_read_u32(node, "refclk-frequency", &clock_rate)) { + dev_err(dev, "No UCTL \"refclk-frequency\"\n"); + return -EINVAL; + } + if (of_property_read_string(node, "refclk-type-ss", &ss_clock_type)) { + dev_err(dev, "No UCTL \"refclk-type-ss\"\n"); + return -EINVAL; + } + if (of_property_read_string(node, "refclk-type-hs", &hs_clock_type)) { + dev_err(dev, "No UCTL \"refclk-type-hs\"\n"); + return -EINVAL; + } + + ref_clk_sel = 2; + if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { + if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) + ref_clk_sel = 0; + else if (strcmp(hs_clock_type, "pll_ref_clk")) + dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", + hs_clock_type); + } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { + if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) { + ref_clk_sel = 1; + } else { + ref_clk_sel = 3; + if (strcmp(hs_clock_type, "pll_ref_clk")) + dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", + hs_clock_type); + } + } else { + dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n", + ss_clock_type); + } + + ref_clk_fsel = 0x07; + switch (clock_rate) { + default: + dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", + clock_rate); + fallthrough; + case 100000000: + mpll_mul = 0x19; + if (ref_clk_sel < 2) + ref_clk_fsel = 0x27; + break; + case 50000000: + mpll_mul = 0x32; + break; + case 125000000: + mpll_mul = 0x28; + break; + } power_gpio = DWC3_GPIO_POWER_NONE; power_active_low = 0; @@ -515,7 +499,8 @@ static int dwc3_octeon_probe(struct platform_device *pdev) if (IS_ERR(octeon->base)) return PTR_ERR(octeon->base); - err = dwc3_octeon_setup(octeon, power_gpio, power_active_low); + err = dwc3_octeon_setup(octeon, ref_clk_sel, ref_clk_fsel, mpll_mul, + power_gpio, power_active_low); if (err) return err; From patchwork Sun Jul 16 14:17:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13314822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9A17C0015E for ; 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a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1689517024; bh=tAEGamY/x6EGfjLvIsf7epNT1w/7wqVxn/uag/blbPk=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=xam7mA7VVxtfFogRRn9btR6W7N/gdkOWh6wJRaqWo8xH6LnzctiIplI9D2kq69WAZ JClqX7AWV7mb6uIN8fHyZHix45IPK/sGN3VU1ed7OVduEClrK4QOCu4UFXEEh0TiJo PJwpAMyDSPZQM/2yHJ3Ban8U+bB1iXDqEIyrg9fxgIniEnAu5Mc6hGuEvlZVCM+bNg pJQzYQRBZyRHUF2+YQuwV1XZNjhNZRXeQxBZhMxWb6WCSJOdGW7V/mbfxGX552eyam Szb5hVQzlu/hUc0WXVtm41s+4fSN7TZMQfE/n1A2eewxCyyzdkWMU7WVrnZc6xt2a6 OB0MlKIxxnUIw== Date: Sun, 16 Jul 2023 16:17:03 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v4 5/6] usb: dwc3: dwc3-octeon: Dump control register on clock init failure Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfAo5o2wh7hs80bRLFm25WvE7unc2GiynDReoXiJkqPFumTamm+xrR5EXWvMqfGyafLQAUILkDvJab18hYsXcZwoKXVYAbextDuGSiZKKXCW8TIw1ShRJ at8UW9BL2lSqOks2ujQM0chbQizmPBlDSQuXbrXIoDFmBrrYjriISeqHcQgeARYc65U8akUnK5yrA14ldkEVR9Q4ipRWO5fvbLHoBUEQlYH8IvkBYt4fieiY 3ROCqbrB3otWzLYBliI6P7gS741nofmYI3QmFfk+vblwjg1sq2rcDfV4VvmH2Ud5mjGUpe5WRAFOWBQ15qB9Cjz4T+APRpJTDdG6KPbTLKpM2uG7deQYzrkO FLe/Y36C Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl It might be interesting to know control register value in case clock fails to enable. Signed-off-by: Ladislav Michl Reviewed-by: Philippe Mathieu-Daudé --- CHANGES: - v4: new patch drivers/usb/dwc3/dwc3-octeon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 45726b39adab..9116df7def86 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -299,8 +299,8 @@ static int dwc3_octeon_setup(struct dwc3_octeon *octeon, val = dwc3_octeon_readq(uctl_ctl_reg); if ((div != FIELD_GET(USBDRD_UCTL_CTL_H_CLKDIV_SEL, val)) || (!(FIELD_GET(USBDRD_UCTL_CTL_H_CLK_EN, val)))) { - dev_err(dev, "dwc3 controller clock init failure.\n"); - return -EINVAL; + dev_err(dev, "clock init failure (UCTL_CTL=%016llx)\n", val); + return -EINVAL; } /* Step 4c: Deassert the controller clock divider reset. */ From patchwork Sun Jul 16 14:18:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13314823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A7F5EB64DD for ; Sun, 16 Jul 2023 14:18:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230100AbjGPOST (ORCPT ); Sun, 16 Jul 2023 10:18:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229451AbjGPOSS (ORCPT ); Sun, 16 Jul 2023 10:18:18 -0400 Received: from h2.cmg2.smtp.forpsi.com (h2.cmg2.smtp.forpsi.com [81.2.195.189]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A622E10C8 for ; Sun, 16 Jul 2023 07:18:17 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id L2ZiqGIwyv5uIL2Zjqf7bX; Sun, 16 Jul 2023 16:18:15 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1689517095; bh=qdO2VOuc14sUkO6Zp+yxVTT9prZLp83cSci1HnsSQuo=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=hpq6GmZtwJOTTnmJf+qnRmJmoYZH4/poKRX0SetUv03iuWpcUH3g1C1stphXjGJF2 5FqiS10SE3/xwo7D5wKeRt7imNMkvsF1qqP0uwCyEQckCR0jlYVpxO10s+trcpmhX5 366KL4lbPsvex7n6yTKiOxFNHfm4CYcS5pC4QZ/hbk2qEb6Tf42u+BuBQ/SSsn6JKo YV6MpfmodXeFyD4ZEi/ey63Jd0ORBdvxQXfCXsB0c05+M23yKmFmsjxtT7TpD+mbuD 95B3/J3tJ3XSGb8OIxg5kWtQzX3/OU3OlBfoQlPFSK3WhpuSf6LJIYBVf5OPYnZa8h O/8dZtcPnF1HA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1689517095; bh=qdO2VOuc14sUkO6Zp+yxVTT9prZLp83cSci1HnsSQuo=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=hpq6GmZtwJOTTnmJf+qnRmJmoYZH4/poKRX0SetUv03iuWpcUH3g1C1stphXjGJF2 5FqiS10SE3/xwo7D5wKeRt7imNMkvsF1qqP0uwCyEQckCR0jlYVpxO10s+trcpmhX5 366KL4lbPsvex7n6yTKiOxFNHfm4CYcS5pC4QZ/hbk2qEb6Tf42u+BuBQ/SSsn6JKo YV6MpfmodXeFyD4ZEi/ey63Jd0ORBdvxQXfCXsB0c05+M23yKmFmsjxtT7TpD+mbuD 95B3/J3tJ3XSGb8OIxg5kWtQzX3/OU3OlBfoQlPFSK3WhpuSf6LJIYBVf5OPYnZa8h O/8dZtcPnF1HA== Date: Sun, 16 Jul 2023 16:18:14 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v4 6/6] usb: dwc3: dwc3-octeon: Add SPDX header and copyright Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfKcGgF/V+a04bA69L8vLH3n4OMYWqA7A71apVZStSQL9tApjZP13X1QHh+LqmcKAIqOFuy7ik0vZrkn5C/oVejx/sDeFzLTsk7/u0vIRoFR5ieXZbCVV kbXY6esu3kKgvuTvDVhlNfx6g/p7qqVJq6VXdTjy4q1MxM9aBbAI4i+9tFnEabG/AtwdDDKZzpRJF7i+a5gGMRMM8zL3b1lStdQZ1n/JPB/y5irlaQ3/mIY+ caQIPsyLACcxKQ0Vush+eW7tvDAcPvdWe2PnIMmDMAyxDestPyEMIiDAm7/bd0VemL0WQX1FcbRNavG6dP5oV4l9TF840OowIoMohAGvH0zoYVLev7vlf/kU BdxqPWt9 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Assign copyright to indicate driver rewrite is done for RACOM s.r.o. As David no longer works for Marvell (Cavium), I'm to blame for breakage. Signed-off-by: Ladislav Michl --- CHANGES: - v2: None - v3: None - v4: Assign copyring to RACOM s.r.o., Mírová 1283, Nové Město na Moravě drivers/usb/dwc3/dwc3-octeon.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 9116df7def86..122f062d2822 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -1,11 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * XHCI HCD glue for Cavium Octeon III SOCs. + * DWC3 glue for Cavium Octeon III SOCs. * * Copyright (C) 2010-2017 Cavium Networks - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * Copyright (C) 2023 RACOM s.r.o. */ #include @@ -537,6 +535,6 @@ static struct platform_driver dwc3_octeon_driver = { module_platform_driver(dwc3_octeon_driver); MODULE_ALIAS("platform:dwc3-octeon"); -MODULE_AUTHOR("David Daney "); +MODULE_AUTHOR("Ladislav Michl "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("DesignWare USB3 OCTEON III Glue Layer");