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[83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:11 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:08 +0200 Subject: [PATCH 01/15] clk: qcom: branch: Add a helper for setting the enable bit MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-1-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=1295; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=6Bd/Fnfm9Yhx1mDIqJ/W7OC8Bh6MqHAA2H25Y3NFUOA=; b=W+t3CYvKLcbnd3HBI6U4rTbNjkWhWpjjL8PwzInHpYqquxKS67oW2oR9Eq80nBfv1/IheKGNt MivQ+jMFAXVClg3i6dYItzbwkIsd+gg504JipLN5HWewLd5NT3MOQOS X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We harcode some clocks to be always-on, as they're essential to the functioning of the SoC / some peripherals. Add a helper to do so to make the writes less magic. Signed-off-by: Konrad Dybcio Reviewed-by: Johan Hovold --- drivers/clk/qcom/clk-branch.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 0cf800b9d08d..155818cc8d49 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -47,6 +47,7 @@ struct clk_branch { #define CBCR_FORCE_MEM_PERIPH_OFF BIT(12) #define CBCR_WAKEUP GENMASK(11, 8) #define CBCR_SLEEP GENMASK(7, 4) +#define CBCR_CLOCK_ENABLE BIT(0) static inline void qcom_branch_set_force_mem_core(struct regmap *regmap, struct clk_branch clk, bool on) @@ -81,6 +82,12 @@ static inline void qcom_branch_set_sleep(struct regmap *regmap, struct clk_branc FIELD_PREP(CBCR_SLEEP, val)); } +static inline void qcom_branch_set_clk_en(struct regmap *regmap, u32 cbcr) +{ + regmap_update_bits(regmap, cbcr, CBCR_CLOCK_ENABLE, + CBCR_CLOCK_ENABLE); +} + extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; From patchwork Mon Jul 17 15:19:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13315887 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CD00C00528 for ; Mon, 17 Jul 2023 15:19:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231460AbjGQPTX (ORCPT ); Mon, 17 Jul 2023 11:19:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231400AbjGQPTT (ORCPT ); Mon, 17 Jul 2023 11:19:19 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6030107 for ; Mon, 17 Jul 2023 08:19:15 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-4f122ff663eso7332308e87.2 for ; Mon, 17 Jul 2023 08:19:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689607154; x=1692199154; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xEbz14sJogEawdfgO5oBd9h7t4FLIUgSkpv1pu1IPqw=; b=L2Ouk7KBh+sMXqs/a+pppZLxaIMTZ4dGtgg/aSl8qpDmqmmuXAb26WlOE3hESDEmyY +uGJ/DHeCdAU0m9sh4MwT2jSOHPd5KfEN2ehzpRtPecjbpx914iRdmKcoj4652T6rvgx K1lNFph20QeMtm1hzuGrnbgkITQGIqOIhmZDSe9GmSoHcXMIX0ordBBbyhsJ7YVuejV9 wtu7FfxsatJLBZMZZgx6l3WEUS063PdE0wYG5z3gMDRMMGB/W+zrvoT9j+W9bFJCBS2d b6X+nhJrxVMqGAGqkxY14pg+JZ1ro5R71cypGwUJqOmV4Gh/miyOT02eMWz1kfnxAtW0 Se/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689607154; x=1692199154; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xEbz14sJogEawdfgO5oBd9h7t4FLIUgSkpv1pu1IPqw=; b=EcwaoZLnSMIocATxhUbllFdZYJesvb/8ZR5MJjqvQaeE/zdRjKpWXjVMESfoXTsbiJ JC+xsBm0KDt2qPng+jgdFsLSWBAaRHre1/JIgcIt5KyopPMJiaHrC8tamZLuJWlb2a2s t+5i2UotzxPaF2GQZAwIUGjypgCca//XA/eH9vg2sf7qG8JFcUjzXaqD+TZ/hx4+ouMh Cj+aew7IVOSxnvZq3qilVzLc8UMfpuq9Ug/VzR5U7ho2abvQA6zKT0O3Vb9lM8QwCwT7 lfYCboiK0V9aGIHenwdLxLNn2YN2S5jbAG1CMcRPRneq93vKTMzPt3FookSCMHt1vDEE Mzog== X-Gm-Message-State: ABy/qLa3jFl4uZqlp7LaTJxbSfPq5MaDxJcU5QD2kMrLbGApJ1Q9eAcg IQSve0FxRN+YmqCkPEjNY+NdMw== X-Google-Smtp-Source: APBJJlG57Lhqko2sVmZQ8dp7QT3ILE9qm108opoFBRY1b5NB/ZxWqmkFpl5ACRIuBXOsi1Wg4akdBg== X-Received: by 2002:a05:6512:46d:b0:4fb:90f7:6769 with SMTP id x13-20020a056512046d00b004fb90f76769mr7248001lfd.21.1689607153898; Mon, 17 Jul 2023 08:19:13 -0700 (PDT) Received: from [192.168.1.101] (abyj181.neoplus.adsl.tpnet.pl. [83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:13 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:09 +0200 Subject: [PATCH 02/15] clk: qcom: Use qcom_branch_set_clk_en() MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-2-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=26116; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=WD5ZHHQLMyFWQF1yLyD4USNKrd2rTZcsxTllxzqVFIw=; b=1i6EXn+AhtpqtfVuQu1WjMmVN9Y7MwxudW2b/HsKxH0DEFNbyKGOvJLMtgW89U8O5Q65obogI 0sTtEEkucM1A+tG0hpDGhTGu6II3bifIN/laovOJ0uOKvxooFgf/Tfw X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Instead of magically poking at the bit0 of branch clocks' CBCR, use the newly introduced helper. Signed-off-by: Konrad Dybcio Acked-by: Johan Hovold --- drivers/clk/qcom/dispcc-qcm2290.c | 2 +- drivers/clk/qcom/dispcc-sc7280.c | 2 +- drivers/clk/qcom/dispcc-sc8280xp.c | 2 +- drivers/clk/qcom/dispcc-sm6115.c | 2 +- drivers/clk/qcom/dispcc-sm8250.c | 2 +- drivers/clk/qcom/dispcc-sm8450.c | 2 +- drivers/clk/qcom/dispcc-sm8550.c | 2 +- drivers/clk/qcom/gcc-sa8775p.c | 18 +++++++++--------- drivers/clk/qcom/gcc-sc7180.c | 16 ++++++++-------- drivers/clk/qcom/gcc-sc7280.c | 14 +++++++------- drivers/clk/qcom/gcc-sc8180x.c | 20 ++++++++++---------- drivers/clk/qcom/gcc-sc8280xp.c | 18 +++++++++--------- drivers/clk/qcom/gcc-sdx55.c | 2 +- drivers/clk/qcom/gcc-sdx65.c | 2 +- drivers/clk/qcom/gcc-sdx75.c | 4 ++-- drivers/clk/qcom/gcc-sm6375.c | 6 +++--- drivers/clk/qcom/gcc-sm7150.c | 16 ++++++++-------- drivers/clk/qcom/gcc-sm8250.c | 12 ++++++------ drivers/clk/qcom/gcc-sm8350.c | 14 +++++++------- drivers/clk/qcom/gcc-sm8450.c | 14 +++++++------- drivers/clk/qcom/gcc-sm8550.c | 14 +++++++------- drivers/clk/qcom/gpucc-sc7280.c | 4 ++-- drivers/clk/qcom/gpucc-sc8280xp.c | 4 ++-- drivers/clk/qcom/gpucc-sm8550.c | 4 ++-- drivers/clk/qcom/lpasscorecc-sc7180.c | 2 +- drivers/clk/qcom/videocc-sm8250.c | 4 ++-- drivers/clk/qcom/videocc-sm8350.c | 4 ++-- drivers/clk/qcom/videocc-sm8450.c | 6 +++--- drivers/clk/qcom/videocc-sm8550.c | 6 +++--- 29 files changed, 109 insertions(+), 109 deletions(-) diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c index 44dd5cfcc150..5f90e8c15c01 100644 --- a/drivers/clk/qcom/dispcc-qcm2290.c +++ b/drivers/clk/qcom/dispcc-qcm2290.c @@ -520,7 +520,7 @@ static int disp_cc_qcm2290_probe(struct platform_device *pdev) clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); /* Keep DISP_CC_XO_CLK always-ON */ - regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x604c); ret = qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap); if (ret) { diff --git a/drivers/clk/qcom/dispcc-sc7280.c b/drivers/clk/qcom/dispcc-sc7280.c index ad596d567f6a..975f31b51539 100644 --- a/drivers/clk/qcom/dispcc-sc7280.c +++ b/drivers/clk/qcom/dispcc-sc7280.c @@ -882,7 +882,7 @@ static int disp_cc_sc7280_probe(struct platform_device *pdev) * Keep the clocks always-ON * DISP_CC_XO_CLK */ - regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x5008); return qcom_cc_really_probe(pdev, &disp_cc_sc7280_desc, regmap); } diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-sc8280xp.c index 167470beb369..37b8bbbe9282 100644 --- a/drivers/clk/qcom/dispcc-sc8280xp.c +++ b/drivers/clk/qcom/dispcc-sc8280xp.c @@ -3179,7 +3179,7 @@ static int disp_cc_sc8280xp_probe(struct platform_device *pdev) } /* DISP_CC_XO_CLK always-on */ - regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x605c); out_pm_runtime_put: pm_runtime_put_sync(&pdev->dev); diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6115.c index 1937edf23f21..cf88ca143bd7 100644 --- a/drivers/clk/qcom/dispcc-sm6115.c +++ b/drivers/clk/qcom/dispcc-sm6115.c @@ -584,7 +584,7 @@ static int disp_cc_sm6115_probe(struct platform_device *pdev) clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); /* Keep DISP_CC_XO_CLK always-ON */ - regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x604c); ret = qcom_cc_really_probe(pdev, &disp_cc_sm6115_desc, regmap); if (ret) { diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index e17bb8b543b5..4f2297043820 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1366,7 +1366,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) regmap_update_bits(regmap, 0x8000, 0x10, 0x10); /* DISP_CC_XO_CLK always-on */ - regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x605c); ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c index adbfd30bfc96..e258cd9ba87e 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -1789,7 +1789,7 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev) * Keep clocks always enabled: * disp_cc_xo_clk */ - regmap_update_bits(regmap, 0xe05c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0xe05c); ret = qcom_cc_really_probe(pdev, &disp_cc_sm8450_desc, regmap); diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index 1e5a11081860..2bd6ca2c952f 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -1774,7 +1774,7 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev) * Keep clocks always enabled: * disp_cc_xo_clk */ - regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0xe054); ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap); diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c index bb94ff367abd..9db144b7f05f 100644 --- a/drivers/clk/qcom/gcc-sa8775p.c +++ b/drivers/clk/qcom/gcc-sa8775p.c @@ -4748,15 +4748,15 @@ static int gcc_sa8775p_probe(struct platform_device *pdev) * GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK. */ - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x32004); + qcom_branch_set_clk_en(regmap, 0x32020); + qcom_branch_set_clk_en(regmap, 0xc7004); + qcom_branch_set_clk_en(regmap, 0xc7018); + qcom_branch_set_clk_en(regmap, 0x33004); + qcom_branch_set_clk_en(regmap, 0x33018); + qcom_branch_set_clk_en(regmap, 0x7d004); + qcom_branch_set_clk_en(regmap, 0x34004); + qcom_branch_set_clk_en(regmap, 0x34024); return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c index cef3c77564cf..4f79ecb8300d 100644 --- a/drivers/clk/qcom/gcc-sc7180.c +++ b/drivers/clk/qcom/gcc-sc7180.c @@ -2447,14 +2447,14 @@ static int gcc_sc7180_probe(struct platform_device *pdev) * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, * GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK */ - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x48004); + qcom_branch_set_clk_en(regmap, 0x0b004); + qcom_branch_set_clk_en(regmap, 0x0b008); + qcom_branch_set_clk_en(regmap, 0x0b00c); + qcom_branch_set_clk_en(regmap, 0x0b02c); + qcom_branch_set_clk_en(regmap, 0x0b028); + qcom_branch_set_clk_en(regmap, 0x0b030); + qcom_branch_set_clk_en(regmap, 0x71004); ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c index 1dc804154031..b23f7103d08d 100644 --- a/drivers/clk/qcom/gcc-sc7280.c +++ b/drivers/clk/qcom/gcc-sc7280.c @@ -3458,13 +3458,13 @@ static int gcc_sc7280_probe(struct platform_device *pdev) * GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK * GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x26004); + qcom_branch_set_clk_en(regmap, 0x26028); + qcom_branch_set_clk_en(regmap, 0x27004); + qcom_branch_set_clk_en(regmap, 0x2701C); + qcom_branch_set_clk_en(regmap, 0x28004); + qcom_branch_set_clk_en(regmap, 0x28014); + qcom_branch_set_clk_en(regmap, 0x71004); regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13)); ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c index c41b9f010585..14f09c407198 100644 --- a/drivers/clk/qcom/gcc-sc8180x.c +++ b/drivers/clk/qcom/gcc-sc8180x.c @@ -4587,16 +4587,16 @@ static int gcc_sc8180x_probe(struct platform_device *pdev) * GCC_CPUSS_GNOC_CLK, GCC_CPUSS_DVM_BUS_CLK, GCC_NPU_CFG_AHB_CLK and * GCC_GPU_CFG_AHB_CLK */ - regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0xb004); + qcom_branch_set_clk_en(regmap, 0xb008); + qcom_branch_set_clk_en(regmap, 0xb00c); + qcom_branch_set_clk_en(regmap, 0xb040); + qcom_branch_set_clk_en(regmap, 0xb044); + qcom_branch_set_clk_en(regmap, 0xb048); + qcom_branch_set_clk_en(regmap, 0x48004); + qcom_branch_set_clk_en(regmap, 0x48190); + qcom_branch_set_clk_en(regmap, 0x4d004); + qcom_branch_set_clk_en(regmap, 0x71004); /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index 1fb6ffac730c..a9b3735baa4b 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -7549,15 +7549,15 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev) * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, * GCC_VIDEO_XO_CLK, GCC_DISP1_AHB_CLK, GCC_DISP1_XO_CLK */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26020, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xbb004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xbb028, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x26004); + qcom_branch_set_clk_en(regmap, 0x26020); + qcom_branch_set_clk_en(regmap, 0x27004); + qcom_branch_set_clk_en(regmap, 0x27028); + qcom_branch_set_clk_en(regmap, 0x71004); + qcom_branch_set_clk_en(regmap, 0x28004); + qcom_branch_set_clk_en(regmap, 0x28028); + qcom_branch_set_clk_en(regmap, 0xbb004); + qcom_branch_set_clk_en(regmap, 0xbb028); ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); if (ret) diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c index d5e17122698c..b1ef6223b5ee 100644 --- a/drivers/clk/qcom/gcc-sdx55.c +++ b/drivers/clk/qcom/gcc-sdx55.c @@ -1616,7 +1616,7 @@ static int gcc_sdx55_probe(struct platform_device *pdev) * of the system: * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK */ - regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x6d008); regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); diff --git a/drivers/clk/qcom/gcc-sdx65.c b/drivers/clk/qcom/gcc-sdx65.c index b0c17043551d..62ea059d528d 100644 --- a/drivers/clk/qcom/gcc-sdx65.c +++ b/drivers/clk/qcom/gcc-sdx65.c @@ -1579,7 +1579,7 @@ static int gcc_sdx65_probe(struct platform_device *pdev) * of the system: * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK */ - regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x6d008); regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); diff --git a/drivers/clk/qcom/gcc-sdx75.c b/drivers/clk/qcom/gcc-sdx75.c index b6772abdcec5..3c838fb43ce8 100644 --- a/drivers/clk/qcom/gcc-sdx75.c +++ b/drivers/clk/qcom/gcc-sdx75.c @@ -2940,8 +2940,8 @@ static int gcc_sdx75_probe(struct platform_device *pdev) * gcc_ahb_pcie_link_clk * gcc_xo_pcie_link_clk */ - regmap_update_bits(regmap, 0x3e004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x3e008, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x3e004); + qcom_branch_set_clk_en(regmap, 0x3e008); return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index 417a0fd242ec..e94e88bdfb91 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -3885,9 +3885,9 @@ static int gcc_sm6375_probe(struct platform_device *pdev) * Keep the following clocks always on: * GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK */ - regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x17028); + qcom_branch_set_clk_en(regmap, 0x2b004); + qcom_branch_set_clk_en(regmap, 0x1702c); clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config); diff --git a/drivers/clk/qcom/gcc-sm7150.c b/drivers/clk/qcom/gcc-sm7150.c index 6da87f0436d0..696cca37b48b 100644 --- a/drivers/clk/qcom/gcc-sm7150.c +++ b/drivers/clk/qcom/gcc-sm7150.c @@ -3008,14 +3008,14 @@ static int gcc_sm7150_probe(struct platform_device *pdev) * GCC_DISP_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_VIDEO_XO_CLK, * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK */ - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x48004); + qcom_branch_set_clk_en(regmap, 0x0b004); + qcom_branch_set_clk_en(regmap, 0x0b008); + qcom_branch_set_clk_en(regmap, 0x0b00c); + qcom_branch_set_clk_en(regmap, 0x0b02c); + qcom_branch_set_clk_en(regmap, 0x0b028); + qcom_branch_set_clk_en(regmap, 0x0b030); + qcom_branch_set_clk_en(regmap, 0x71004); ret = qcom_cc_register_rcg_dfs(regmap, gcc_sm7150_dfs_desc, ARRAY_SIZE(gcc_sm7150_dfs_desc)); diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c index b6cf4bc88d4d..ad3dd69dd198 100644 --- a/drivers/clk/qcom/gcc-sm8250.c +++ b/drivers/clk/qcom/gcc-sm8250.c @@ -3648,12 +3648,12 @@ static int gcc_sm8250_probe(struct platform_device *pdev) * GCC_CPUSS_DVM_BUS_CLK, GCC_GPU_CFG_AHB_CLK, * GCC_SYS_NOC_CPUSS_AHB_CLK */ - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x0b004); + qcom_branch_set_clk_en(regmap, 0x0b008); + qcom_branch_set_clk_en(regmap, 0x0b00c); + qcom_branch_set_clk_en(regmap, 0x4818c); + qcom_branch_set_clk_en(regmap, 0x71004); + qcom_branch_set_clk_en(regmap, 0x52000); ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c index 1385a98eb3bb..b56a7669b770 100644 --- a/drivers/clk/qcom/gcc-sm8350.c +++ b/drivers/clk/qcom/gcc-sm8350.c @@ -3811,13 +3811,13 @@ static int gcc_sm8350_probe(struct platform_device *pdev) * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x26004); + qcom_branch_set_clk_en(regmap, 0x26018); + qcom_branch_set_clk_en(regmap, 0x27004); + qcom_branch_set_clk_en(regmap, 0x2701c); + qcom_branch_set_clk_en(regmap, 0x71004); + qcom_branch_set_clk_en(regmap, 0x28004); + qcom_branch_set_clk_en(regmap, 0x28020); ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); if (ret) diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c index 75635d40a12d..5a7a723ff5ef 100644 --- a/drivers/clk/qcom/gcc-sm8450.c +++ b/drivers/clk/qcom/gcc-sm8450.c @@ -3285,13 +3285,13 @@ static int gcc_sm8450_probe(struct platform_device *pdev) * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, * gcc_video_xo_clk */ - regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x36004); + qcom_branch_set_clk_en(regmap, 0x36020); + qcom_branch_set_clk_en(regmap, 0x37004); + qcom_branch_set_clk_en(regmap, 0x3701c); + qcom_branch_set_clk_en(regmap, 0x81004); + qcom_branch_set_clk_en(regmap, 0x42004); + qcom_branch_set_clk_en(regmap, 0x42028); return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap); } diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c index 277cd4f020ff..a6404421021f 100644 --- a/drivers/clk/qcom/gcc-sm8550.c +++ b/drivers/clk/qcom/gcc-sm8550.c @@ -3349,13 +3349,13 @@ static int gcc_sm8550_probe(struct platform_device *pdev) * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, * gcc_video_xo_clk */ - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x26004); + qcom_branch_set_clk_en(regmap, 0x26028); + qcom_branch_set_clk_en(regmap, 0x27004); + qcom_branch_set_clk_en(regmap, 0x27018); + qcom_branch_set_clk_en(regmap, 0x71004); + qcom_branch_set_clk_en(regmap, 0x32004); + qcom_branch_set_clk_en(regmap, 0x32030); /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ regmap_write(regmap, 0x52024, 0x0); diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c index 1490cd45a654..a678c51cd75e 100644 --- a/drivers/clk/qcom/gpucc-sc7280.c +++ b/drivers/clk/qcom/gpucc-sc7280.c @@ -461,8 +461,8 @@ static int gpu_cc_sc7280_probe(struct platform_device *pdev) * Keep the clocks always-ON * GPU_CC_CB_CLK, GPUCC_CX_GMU_CLK */ - regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x1098, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x1170); + qcom_branch_set_clk_en(regmap, 0x1098); regmap_update_bits(regmap, 0x1098, BIT(13), BIT(13)); return qcom_cc_really_probe(pdev, &gpu_cc_sc7280_desc, regmap); diff --git a/drivers/clk/qcom/gpucc-sc8280xp.c b/drivers/clk/qcom/gpucc-sc8280xp.c index 8e147ee294ee..c709365a3c57 100644 --- a/drivers/clk/qcom/gpucc-sc8280xp.c +++ b/drivers/clk/qcom/gpucc-sc8280xp.c @@ -448,8 +448,8 @@ static int gpu_cc_sc8280xp_probe(struct platform_device *pdev) * Keep the clocks always-ON * GPU_CC_CB_CLK, GPU_CC_CXO_CLK */ - regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x1170); + qcom_branch_set_clk_en(regmap, 0x109c); ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap); pm_runtime_put(&pdev->dev); diff --git a/drivers/clk/qcom/gpucc-sm8550.c b/drivers/clk/qcom/gpucc-sm8550.c index 8a2e3522af51..225807979435 100644 --- a/drivers/clk/qcom/gpucc-sm8550.c +++ b/drivers/clk/qcom/gpucc-sm8550.c @@ -581,8 +581,8 @@ static int gpu_cc_sm8550_probe(struct platform_device *pdev) * gpu_cc_cxo_aon_clk * gpu_cc_demet_clk */ - regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x9004); + qcom_branch_set_clk_en(regmap, 0x900c); return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap); } diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c b/drivers/clk/qcom/lpasscorecc-sc7180.c index 010867dcc2ef..7fa2e28489fd 100644 --- a/drivers/clk/qcom/lpasscorecc-sc7180.c +++ b/drivers/clk/qcom/lpasscorecc-sc7180.c @@ -405,7 +405,7 @@ static int lpass_core_cc_sc7180_probe(struct platform_device *pdev) * Keep the CLK always-ON * LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK */ - regmap_update_bits(regmap, 0x24000, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x24000); /* PLL settings */ regmap_write(regmap, 0x1008, 0x20); diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index ad46c4014a40..1f269025f3f8 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -384,8 +384,8 @@ static int video_cc_sm8250_probe(struct platform_device *pdev) clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); /* Keep VIDEO_CC_AHB_CLK and VIDEO_CC_XO_CLK ALWAYS-ON */ - regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0xe58); + qcom_branch_set_clk_en(regmap, 0xeec); ret = qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap); diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c index b148877fc73d..4e6b2c7fe61b 100644 --- a/drivers/clk/qcom/videocc-sm8350.c +++ b/drivers/clk/qcom/videocc-sm8350.c @@ -524,8 +524,8 @@ static int video_cc_sm8350_probe(struct platform_device *pdev) * video_cc_ahb_clk * video_cc_xo_clk */ - regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0xe58); + qcom_branch_set_clk_en(regmap, 0xeec); ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap); pm_runtime_put(&pdev->dev); diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c index 7d0029b8b799..deaf58c95749 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -428,9 +428,9 @@ static int video_cc_sm8450_probe(struct platform_device *pdev) * video_cc_sleep_clk * video_cc_xo_clk */ - regmap_update_bits(regmap, 0x80e4, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8130, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8114, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x80e4); + qcom_branch_set_clk_en(regmap, 0x8130); + qcom_branch_set_clk_en(regmap, 0x8114); ret = qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap); diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c index e2400fe23e60..802bbd616b2f 100644 --- a/drivers/clk/qcom/videocc-sm8550.c +++ b/drivers/clk/qcom/videocc-sm8550.c @@ -435,9 +435,9 @@ static int video_cc_sm8550_probe(struct platform_device *pdev) * video_cc_sleep_clk * video_cc_xo_clk */ - regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0)); + qcom_branch_set_clk_en(regmap, 0x80f4); + qcom_branch_set_clk_en(regmap, 0x8140); + qcom_branch_set_clk_en(regmap, 0x8124); ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap); From patchwork Mon Jul 17 15:19:10 2023 Content-Type: text/plain; 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[83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:14 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:10 +0200 Subject: [PATCH 03/15] clk: qcom: gcc-sm6375: Unregister critical clocks MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-3-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=6998; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=nlQSrpDwXAIARKneY1DtqMYtmRn22TVOrx5+llC+mac=; b=Q8exJDNvf0akjWbLPSSCB3p1/wGsxf7IiaC12cwhOiJjkDGuhdyQjIWhE1y7NZQgd/WL03TeR 09db139MQWIAkYjF+lSjURkUbstR21+5GO8OwWhjceBVb21azUQy2a2 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm6375.c | 103 ++++++------------------------------------ 1 file changed, 13 insertions(+), 90 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index e94e88bdfb91..14dafea45ac9 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -1742,22 +1742,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk = { }, }; -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x17008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_camss_axi_clk = { .halt_reg = 0x58044, .halt_check = BRANCH_HALT, @@ -2308,22 +2292,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { }, }; -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0x1700c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x1700c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x1700c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_disp_gpll0_clk_src = { .reg = 0x17058, .shift = 0, @@ -2454,22 +2422,6 @@ static struct clk_branch gcc_gp3_clk = { }, }; -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x36004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_gpll0_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -3093,26 +3045,6 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x2b06c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x2b06c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x79004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { .halt_reg = 0x45098, .halt_check = BRANCH_HALT, @@ -3432,22 +3364,6 @@ static struct clk_branch gcc_venus_ctl_axi_clk = { }, }; -static struct clk_branch gcc_video_ahb_clk = { - .halt_reg = 0x17004, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0x17004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x17004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_video_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_video_axi0_clk = { .halt_reg = 0x1701c, .halt_check = BRANCH_HALT_VOTED, @@ -3614,7 +3530,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, @@ -3670,7 +3585,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, @@ -3682,7 +3596,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, @@ -3738,7 +3651,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, @@ -3765,7 +3677,6 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, - [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, @@ -3883,11 +3794,23 @@ static int gcc_sm6375_probe(struct platform_device *pdev) /* * Keep the following clocks always on: - * GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK + * GCC_CAMERA_XO_CLK + * GCC_CPUSS_GNOC_CLK + * GCC_DISP_XO_CLK + * GCC_CAMERA_AHB_CLK + * GCC_DISP_AHB_CLK + * GCC_GPU_CFG_AHB_CLK + * GCC_SYS_NOC_CPUSS_AHB_CLK + * GCC_VIDEO_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x17028); qcom_branch_set_clk_en(regmap, 0x2b004); qcom_branch_set_clk_en(regmap, 0x1702c); + qcom_branch_set_clk_en(regmap, 0x17008); + qcom_branch_set_clk_en(regmap, 0x1700c); + qcom_branch_set_clk_en(regmap, 0x36004); + qcom_branch_set_clk_en(regmap, 0x2b06c); + qcom_branch_set_clk_en(regmap, 0x17004); clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config); From patchwork Mon Jul 17 15:19:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13315888 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8498CC04FE0 for ; Mon, 17 Jul 2023 15:19:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231439AbjGQPTZ (ORCPT ); Mon, 17 Jul 2023 11:19:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231434AbjGQPTW (ORCPT ); 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[83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:16 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:11 +0200 Subject: [PATCH 04/15] clk: qcom: gcc-sm6375: Add runtime PM MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-4-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=1780; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=WXWB5RGonBM5RqpbxW2SMsHOf815i9gADOm2q9pJjmc=; b=pWDCxZlE9tVeTMDDwCA3p9Rrnt12uzwSvlwHXrl1IvLIW1632NI1TETMDnuB+qC3FrRMZgcEF TtvljvXN3azCzTks/QYfkOJ+xYNaQKKqWTAnKYaUWJ/hO2MD6rDpj2Y X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GCC block on SM6375 is powered by the VDD_CX rail. We need to ensure that it's enabled to prevent unwanted power collapse. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm6375.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index 14dafea45ac9..4b2de545d3f8 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -3784,9 +3785,19 @@ static int gcc_sm6375_probe(struct platform_device *pdev) struct regmap *regmap; int ret; + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + regmap = qcom_cc_map(pdev, &gcc_sm6375_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); if (ret) @@ -3817,7 +3828,10 @@ static int gcc_sm6375_probe(struct platform_device *pdev) clk_lucid_pll_configure(&gpll8, regmap, &gpll8_config); clk_zonda_pll_configure(&gpll9, regmap, &gpll9_config); - return qcom_cc_really_probe(pdev, &gcc_sm6375_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gcc_sm6375_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver gcc_sm6375_driver = { From patchwork Mon Jul 17 15:19:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13315889 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 936CEC001DC for ; Mon, 17 Jul 2023 15:19:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231535AbjGQPT0 (ORCPT ); Mon, 17 Jul 2023 11:19:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231411AbjGQPTX (ORCPT ); Mon, 17 Jul 2023 11:19:23 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 228FA10EB for ; Mon, 17 Jul 2023 08:19:20 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4fb73ba3b5dso7491351e87.1 for ; Mon, 17 Jul 2023 08:19:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689607158; x=1692199158; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+KuPxi1C9v4ead/OACB04tCRB3cg6PlY88neux9MKiA=; b=EaOiMiPGl0szt/u6qKnLFCt30b8Wg/W8aK13JrTNCd564obk0rB+4MOCLzhg9DITvo P0XTAcSjbaYOBHVEf3jtvPNZXjHS+IGpqqYv1j1uisTe5w4MjUrjbi5rpsLnv8CsUALb 7bQ12iAMHRV4kBrzpUys58T1VI6yByH6d9SCJDljgVMisP8TPdkZJ7WQUDDyzF1vFcO9 dI0j/NBLen/VqrvWhZwvXt+XG/ZEKeuPSwMxo4AYR+yu/IRA8i8VCMs/2nWk8A0qW12P KgfNZI43plk7LEtSTKUIJ4woWRVTOPDLFgid3ynvEbOdbryAJFCrBxpzICRafZ7rvjPP dFqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689607158; x=1692199158; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+KuPxi1C9v4ead/OACB04tCRB3cg6PlY88neux9MKiA=; b=XELJRI4qbfOu5j/FX6KAvpb0czcr/TizROpAOm5NUm1/YjQM9AODkRDnwNYNJ9mIKp /Z5JrcEFKKp9l5iABG3XACzAe8iSJfSWWzVK+vcbftb8cKFrTpA6bfgvnea56KIJdYlJ M8/dPWuxrK+8RXtIfouROV7C5qCEEw3rwxwWd6V8j6FA39HI7r37H04sJN0dThNfzIyF RlurLb/kRCS3RfViMJsglJCW75hOyS7bqyhhhgsYM19aw1UvNbk5g1Epm2Bw0+KT0foU MPm8Wg/XiLi8c16oe/QunNCwMDSr1h1D4K8sRM9v4ZSXyCfAljJd4MC3tMKhZv/r1brW 0rNg== X-Gm-Message-State: ABy/qLZeGHNvKo7IkFbQ6ZrCuuEMlMtIJUcrQa+89RkVyw0L5WELT6hY o3CkCwHQj1D61D6Iyg6aH3lpAQ== X-Google-Smtp-Source: APBJJlGS0BoLKRIohSP2V+ZDI59LSw+/TuRNizZszu2Ewo+hjR4KjhizENM/BpOcGgr6tCpNGWDLVw== X-Received: by 2002:ac2:548b:0:b0:4f9:72a5:2b76 with SMTP id t11-20020ac2548b000000b004f972a52b76mr7826843lfk.65.1689607158068; Mon, 17 Jul 2023 08:19:18 -0700 (PDT) Received: from [192.168.1.101] (abyj181.neoplus.adsl.tpnet.pl. [83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:17 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:12 +0200 Subject: [PATCH 05/15] clk: qcom: gpucc-sm6375: Unregister critical clocks MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-5-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=9588; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=qrPiFGkb35Smv+A56ju84eBm0qjbLG5DXe1UpLsgD14=; b=40ig1X5bIzfGx13qAC9tEY/MyfhAPa/1IYBhtQWC94fSClVve1HzxtI5vFtPMFoiS+HUMkpsm +WQzaSk1LAvCMiQ0XbDPTV1GoRKu3CTzr5mj0otBeV8VZXlBAFge8c5 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm6375.c | 105 ++++++++++++++++++++++++++++++++++------ drivers/clk/qcom/gpucc-sm6375.c | 38 +++------------ 2 files changed, 97 insertions(+), 46 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c index 4b2de545d3f8..a8eb7a47e284 100644 --- a/drivers/clk/qcom/gcc-sm6375.c +++ b/drivers/clk/qcom/gcc-sm6375.c @@ -1743,6 +1743,21 @@ static struct clk_branch gcc_cam_throttle_rt_clk = { }, }; +static struct clk_branch gcc_camera_ahb_clk = { + .halt_reg = 0x17008, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0x17008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x17008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camera_ahb_clk", + .ops = &clk_branch2_aon_ops, + }, + }, +}; + static struct clk_branch gcc_camss_axi_clk = { .halt_reg = 0x58044, .halt_check = BRANCH_HALT, @@ -2293,6 +2308,21 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { }, }; +static struct clk_branch gcc_disp_ahb_clk = { + .halt_reg = 0x1700c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1700c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x1700c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_ahb_clk", + .ops = &clk_branch2_aon_ops, + }, + }, +}; + static struct clk_regmap_div gcc_disp_gpll0_clk_src = { .reg = 0x17058, .shift = 0, @@ -2423,6 +2453,21 @@ static struct clk_branch gcc_gp3_clk = { }, }; +static struct clk_branch gcc_gpu_cfg_ahb_clk = { + .halt_reg = 0x36004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x36004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x36004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_cfg_ahb_clk", + .ops = &clk_branch2_aon_ops, + }, + }, +}; + static struct clk_branch gcc_gpu_gpll0_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -3046,6 +3091,26 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; +static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { + .halt_reg = 0x2b06c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2b06c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x79004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_cpuss_ahb_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { .halt_reg = 0x45098, .halt_check = BRANCH_HALT, @@ -3365,6 +3430,21 @@ static struct clk_branch gcc_venus_ctl_axi_clk = { }, }; +static struct clk_branch gcc_video_ahb_clk = { + .halt_reg = 0x17004, + .halt_check = BRANCH_HALT_DELAY, + .hwcg_reg = 0x17004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x17004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_ahb_clk", + .ops = &clk_branch2_aon_ops, + }, + }, +}; + static struct clk_branch gcc_video_axi0_clk = { .halt_reg = 0x1701c, .halt_check = BRANCH_HALT_VOTED, @@ -3531,6 +3611,7 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, + [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CCI_0_CLK] = &gcc_camss_cci_0_clk.clkr, @@ -3586,6 +3667,7 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr, + [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, @@ -3597,6 +3679,7 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, + [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, @@ -3652,6 +3735,7 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, + [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, @@ -3678,6 +3762,7 @@ static struct clk_regmap *gcc_sm6375_clocks[] = { [GCC_VCODEC0_AXI_CLK] = &gcc_vcodec0_axi_clk.clkr, [GCC_VENUS_AHB_CLK] = &gcc_venus_ahb_clk.clkr, [GCC_VENUS_CTL_AXI_CLK] = &gcc_venus_ctl_axi_clk.clkr, + [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr, [GCC_VIDEO_VCODEC0_SYS_CLK] = &gcc_video_vcodec0_sys_clk.clkr, @@ -3805,23 +3890,11 @@ static int gcc_sm6375_probe(struct platform_device *pdev) /* * Keep the following clocks always on: - * GCC_CAMERA_XO_CLK - * GCC_CPUSS_GNOC_CLK - * GCC_DISP_XO_CLK - * GCC_CAMERA_AHB_CLK - * GCC_DISP_AHB_CLK - * GCC_GPU_CFG_AHB_CLK - * GCC_SYS_NOC_CPUSS_AHB_CLK - * GCC_VIDEO_AHB_CLK + * GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK */ - qcom_branch_set_clk_en(regmap, 0x17028); - qcom_branch_set_clk_en(regmap, 0x2b004); - qcom_branch_set_clk_en(regmap, 0x1702c); - qcom_branch_set_clk_en(regmap, 0x17008); - qcom_branch_set_clk_en(regmap, 0x1700c); - qcom_branch_set_clk_en(regmap, 0x36004); - qcom_branch_set_clk_en(regmap, 0x2b06c); - qcom_branch_set_clk_en(regmap, 0x17004); + regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0)); + regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0)); clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config); diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c index 2d863dc3d83b..d70c6ed0440b 100644 --- a/drivers/clk/qcom/gpucc-sm6375.c +++ b/drivers/clk/qcom/gpucc-sm6375.c @@ -182,20 +182,6 @@ static struct clk_rcg2 gpucc_gx_gfx3d_clk_src = { }, }; -static struct clk_branch gpucc_ahb_clk = { - .halt_reg = 0x1078, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x1078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpucc_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpucc_cx_gfx3d_clk = { .halt_reg = 0x10a4, .halt_check = BRANCH_HALT_DELAY, @@ -293,20 +279,6 @@ static struct clk_branch gpucc_cxo_clk = { }, }; -static struct clk_branch gpucc_gx_cxo_clk = { - .halt_reg = 0x1060, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x1060, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpucc_gx_cxo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpucc_gx_gfx3d_clk = { .halt_reg = 0x1054, .halt_check = BRANCH_HALT_DELAY, @@ -380,7 +352,6 @@ static struct gdsc gpu_gx_gdsc = { }; static struct clk_regmap *gpucc_sm6375_clocks[] = { - [GPU_CC_AHB_CLK] = &gpucc_ahb_clk.clkr, [GPU_CC_CX_GFX3D_CLK] = &gpucc_cx_gfx3d_clk.clkr, [GPU_CC_CX_GFX3D_SLV_CLK] = &gpucc_cx_gfx3d_slv_clk.clkr, [GPU_CC_CX_GMU_CLK] = &gpucc_cx_gmu_clk.clkr, @@ -388,7 +359,6 @@ static struct clk_regmap *gpucc_sm6375_clocks[] = { [GPU_CC_CXO_AON_CLK] = &gpucc_cxo_aon_clk.clkr, [GPU_CC_CXO_CLK] = &gpucc_cxo_clk.clkr, [GPU_CC_GMU_CLK_SRC] = &gpucc_gmu_clk_src.clkr, - [GPU_CC_GX_CXO_CLK] = &gpucc_gx_cxo_clk.clkr, [GPU_CC_GX_GFX3D_CLK] = &gpucc_gx_gfx3d_clk.clkr, [GPU_CC_GX_GFX3D_CLK_SRC] = &gpucc_gx_gfx3d_clk_src.clkr, [GPU_CC_GX_GMU_CLK] = &gpucc_gx_gmu_clk.clkr, @@ -454,6 +424,14 @@ static int gpucc_sm6375_probe(struct platform_device *pdev) clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config); clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config); + /* + * Keep clocks always enabled: + * gpucc_ahb_clk + * gpucc_gx_cxo_clk + */ + qcom_branch_set_clk_en(regmap, 0x1078); + qcom_branch_set_clk_en(regmap, 0x1060); + ret = qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap); pm_runtime_put(&pdev->dev); From patchwork Mon Jul 17 15:19:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13315890 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4D01EB64DC for ; Mon, 17 Jul 2023 15:19:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231417AbjGQPTg (ORCPT ); Mon, 17 Jul 2023 11:19:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231409AbjGQPTY (ORCPT ); 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[83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:19 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:13 +0200 Subject: [PATCH 06/15] clk: qcom: gpucc-sm6115: Unregister critical clocks MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-6-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=3009; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=gGAKlFsEiMqa1it7eUHKXDQHPq4ci/PWNufQygBA064=; b=aGgzTFz/dux49UIL4Jba0PLcD4jT5zrtFO320nx1kJrqM0u124ZO9trfZoW4Ic9nu+bC+g8MJ 0Lg0yit19gxClVTvBBAspBNpX+ssuJRvr3X6EAWQ2c7PY29OXaagFGJ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6115.c | 38 ++++++++------------------------------ 1 file changed, 8 insertions(+), 30 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c index c84727e8352d..ac048f7973d0 100644 --- a/drivers/clk/qcom/gpucc-sm6115.c +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -233,20 +233,6 @@ static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { }, }; -static struct clk_branch gpu_cc_ahb_clk = { - .halt_reg = 0x1078, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x1078, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpu_cc_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpu_cc_crc_ahb_clk = { .halt_reg = 0x107c, .halt_check = BRANCH_HALT_DELAY, @@ -335,20 +321,6 @@ static struct clk_branch gpu_cc_cxo_clk = { }, }; -static struct clk_branch gpu_cc_gx_cxo_clk = { - .halt_reg = 0x1060, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0x1060, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpu_cc_gx_cxo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gpu_cc_gx_gfx3d_clk = { .halt_reg = 0x1054, .halt_check = BRANCH_HALT_SKIP, @@ -417,7 +389,6 @@ static struct gdsc gpu_gx_gdsc = { }; static struct clk_regmap *gpu_cc_sm6115_clocks[] = { - [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, @@ -425,7 +396,6 @@ static struct clk_regmap *gpu_cc_sm6115_clocks[] = { [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, - [GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr, [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, @@ -487,6 +457,14 @@ static int gpu_cc_sm6115_probe(struct platform_device *pdev) qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true); qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true); + /* + * Keep clocks always enabled: + * gpu_cc_ahb_clk + * gpu_cc_gx_cxo_clk + */ + qcom_branch_set_clk_en(regmap, 0x1078); + qcom_branch_set_clk_en(regmap, 0x1060); + return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); } From patchwork Mon Jul 17 15:19:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13315891 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE669C00528 for ; Mon, 17 Jul 2023 15:19:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231409AbjGQPTh (ORCPT ); Mon, 17 Jul 2023 11:19:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231349AbjGQPT0 (ORCPT ); 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[83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:20 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:14 +0200 Subject: [PATCH 07/15] clk: qcom: gpucc-sm6115: Add runtime PM MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-7-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=1880; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=o/nBQFsy6m0Ejq8unCaPVPl+lPMZHWnHPCCx0UDdlsM=; b=6zENJRt1rnQwS88lMzbUfG17CjAcgwstRaXd3IyR0lKxmh6OaPAnukiieoNDlxIsTo7z2zi1s xIgjDV6A7OEDC2l4rappuf9sWVqtBlURpfgAH5TdeStkzgLuFos71Pu X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GPU_CC block on SM6115 is powered by the VDD_CX rail. We need to ensure that it's enabled to prevent unwanted power collapse. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gpucc-sm6115.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c index ac048f7973d0..6fb84492d292 100644 --- a/drivers/clk/qcom/gpucc-sm6115.c +++ b/drivers/clk/qcom/gpucc-sm6115.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -442,10 +443,21 @@ MODULE_DEVICE_TABLE(of, gpu_cc_sm6115_match_table); static int gpu_cc_sm6115_probe(struct platform_device *pdev) { struct regmap *regmap; + int ret; + + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; regmap = qcom_cc_map(pdev, &gpu_cc_sm6115_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); @@ -465,7 +477,10 @@ static int gpu_cc_sm6115_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x1078); qcom_branch_set_clk_en(regmap, 0x1060); - return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver gpu_cc_sm6115_driver = { From patchwork Mon Jul 17 15:19:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13315892 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF6A0EB64DC for ; Mon, 17 Jul 2023 15:19:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231489AbjGQPTl (ORCPT ); Mon, 17 Jul 2023 11:19:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230266AbjGQPTe (ORCPT ); Mon, 17 Jul 2023 11:19:34 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA9F7E7F for ; Mon, 17 Jul 2023 08:19:24 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-4fbb281eec6so7264737e87.1 for ; Mon, 17 Jul 2023 08:19:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689607162; x=1692199162; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=E9bzAyxEmZcjuCgWaxCe1scGgqcWcCc2saD7jQbkp1s=; b=vT5vpikihNkMJKaZ/Qf6szhp3xNMEA4DwQ6u06WwTwuPK7dKC7kQJwAii06wK7TNKS XLF6hdPM0V7qNOM1A7+iXyNi01G9cPKcjb9zx5oC71o+dF+gh+yfm9EV7cV2IpGyyd7Q aue+eCvd/GaLRITjAJhJRqqIXE9sQHejGU5OdINb37UV3Z/vgAXa4NBeH+jXB5ZMve5f XAFQIbc6akIiZBwhf/BjSXlmR9rzv8G9Rlry2Ypfgeud8Oi7LrDrPWZNiQKKo+vVEzpe KJmoW7Z1AdITQrCgbXULFCk4FQFcUaI6g3oUa7K2e5MZFMncTHPGtswaWdXVKFPBEXtn /q7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689607162; x=1692199162; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E9bzAyxEmZcjuCgWaxCe1scGgqcWcCc2saD7jQbkp1s=; b=SKeMG6zx+ZwEshBguNHBP24oBTaMrpohF1R3edE0gR3mOBgFGjr5HR45ESTd1D11vo K1F7bDD3exNgUcTWARU9x48D/TRcHcSSDroUcp6gJyM/yGQVqfMTxirQyFPDpIp+MbAV uScD+p+EWWuKTnHFNCBDZz5TZ42kZnedTUIiF8TYhq6ugXXaW8BfYpo+bLm8QzXPidwE XAjqcdAYXBzeYYa7UTdkBWhl72y40uyqub0IJfpOVxcG00F4s+VLEGNxv8NWBJJ/z2vg UB9pyE9yW1gnORrdVozsonbU3CRwmjUW0nRv2aMVYgORQvu8Wvcms1/YXti+QJqojLQp xVdw== X-Gm-Message-State: ABy/qLYjRdWyE/UJHCHSxbrBzfpXt6toEFICcJcp0/PxiewP3qEs8gE+ pjxd3rN7aoTDkL2KkDy+D9aS41ktcnoaCpn55Jj2jQ== X-Google-Smtp-Source: APBJJlEYn7XZQDHm872lmrD3HHbdNPVNmhgyBztZ+PidTZMCUCNaQ2G94NYFJWgsOdrEMwgj3/nQlg== X-Received: by 2002:a05:6512:348b:b0:4fb:8616:7a03 with SMTP id v11-20020a056512348b00b004fb86167a03mr7426349lfr.4.1689607162748; Mon, 17 Jul 2023 08:19:22 -0700 (PDT) Received: from [192.168.1.101] (abyj181.neoplus.adsl.tpnet.pl. [83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:22 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:15 +0200 Subject: [PATCH 08/15] clk: qcom: gcc-sm6115: Unregister critical clocks MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-8-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=7208; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Aprdi0pZJRcBcTqfoFWAZFZktiahphM2R1wPtOeWO3k=; b=YtWCtGmXdJsmjCmRwxfGg668SV4dORifui04NPqdj8pEemuT9pVl8Oi2UM+iAzXxEyZc3e0pY 9gEbb12MF3KAL+mxHS9JvdtTwH8s1g9gGR6pAmBAH+o+0DENyIsnvc+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm6115.c | 133 ++++++------------------------------------ 1 file changed, 18 insertions(+), 115 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c index 033e308ff865..1b6016e7ddeb 100644 --- a/drivers/clk/qcom/gcc-sm6115.c +++ b/drivers/clk/qcom/gcc-sm6115.c @@ -1585,36 +1585,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk = { }, }; -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x17008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_xo_clk = { - .halt_reg = 0x17028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x17028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_camss_axi_clk = { .halt_reg = 0x58044, .halt_check = BRANCH_HALT, @@ -2123,38 +2093,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { }, }; -static struct clk_branch gcc_cpuss_gnoc_clk = { - .halt_reg = 0x2b004, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x2b004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x79004, - .enable_mask = BIT(22), - .hw.init = &(struct clk_init_data){ - .name = "gcc_cpuss_gnoc_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0x1700c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x1700c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x1700c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_disp_gpll0_clk_src = { .reg = 0x17058, .shift = 0, @@ -2214,20 +2152,6 @@ static struct clk_branch gcc_disp_throttle_core_clk = { }, }; -static struct clk_branch gcc_disp_xo_clk = { - .halt_reg = 0x1702c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1702c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gp1_clk = { .halt_reg = 0x4d000, .halt_check = BRANCH_HALT, @@ -2282,22 +2206,6 @@ static struct clk_branch gcc_gp3_clk = { }, }; -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x36004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_gpll0_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -2770,22 +2678,6 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x2b06c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x2b06c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x79004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = { .halt_reg = 0x45098, .halt_check = BRANCH_HALT, @@ -3271,8 +3163,6 @@ static struct clk_regmap *gcc_sm6115_clocks[] = { [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, @@ -3321,20 +3211,16 @@ static struct clk_regmap *gcc_sm6115_clocks[] = { [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, - [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, @@ -3375,7 +3261,6 @@ static struct clk_regmap *gcc_sm6115_clocks[] = { [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, @@ -3512,6 +3397,24 @@ static int gcc_sm6115_probe(struct platform_device *pdev) clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); + /* + * Keep the following clocks always on: + * GCC_CAMERA_AHB_CLK + * GCC_CAMERA_XO_CLK + * GCC_CPUSS_GNOC_CLK + * GCC_DISP_AHB_CLK + * GCC_DISP_XO_CLK + * GCC_GPU_CFG_AHB_CLK + * GCC_SYS_NOC_CPUSS_AHB_CLK + */ + qcom_branch_set_clk_en(regmap, 0x17008); + qcom_branch_set_clk_en(regmap, 0x17028); + qcom_branch_set_clk_en(regmap, 0x2b004); + qcom_branch_set_clk_en(regmap, 0x1700c); + qcom_branch_set_clk_en(regmap, 0x1702c); + qcom_branch_set_clk_en(regmap, 0x36004); + qcom_branch_set_clk_en(regmap, 0x2b06c); + return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); } From patchwork Mon Jul 17 15:19:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13315893 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FA37C001B0 for ; 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[83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:23 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:16 +0200 Subject: [PATCH 09/15] clk: qcom: gcc-sm6115: Add runtime PM MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-9-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=1944; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=lXR6hOkSuPWCLG8Y1XTv1XtQPJ6qFUCSZCtX0olhcqk=; b=DQYrdPNp19ItZkKR9xWvUUJTORbiBfixcO8AHbrs211Ztx4OFUykP8yb7igKdKVAa5/WLFnmo qw6yMvFLjcWCmwnUwF5TEtWfHufk7HvsdnuJvf5ryqyOpsGjqyupVfF X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GCC block on SM6115 is mostly powered by the VDD_CX rail. We need to ensure that it's enabled to prevent unwanted power collapse. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sm6115.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c index 1b6016e7ddeb..7f1e278c63c0 100644 --- a/drivers/clk/qcom/gcc-sm6115.c +++ b/drivers/clk/qcom/gcc-sm6115.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -3383,14 +3384,26 @@ static int gcc_sm6115_probe(struct platform_device *pdev) struct regmap *regmap; int ret; + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + regmap = qcom_cc_map(pdev, &gcc_sm6115_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); - if (ret) + if (ret) { + pm_runtime_put(&pdev->dev); return ret; + } clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); @@ -3415,7 +3428,10 @@ static int gcc_sm6115_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x36004); qcom_branch_set_clk_en(regmap, 0x2b06c); - return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver gcc_sm6115_driver = { From patchwork Mon Jul 17 15:19:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13315894 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4128FEB64DC for ; Mon, 17 Jul 2023 15:20:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231840AbjGQPT6 (ORCPT ); Mon, 17 Jul 2023 11:19:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231465AbjGQPTj (ORCPT ); Mon, 17 Jul 2023 11:19:39 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7F90171F for ; Mon, 17 Jul 2023 08:19:27 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-4fba8f2197bso7469409e87.3 for ; Mon, 17 Jul 2023 08:19:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689607165; x=1692199165; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mx86M5YQS8ymXI+vhUkZgSGnBjsFbSeN3nBqebJBsPs=; b=koh4FjdIFtADjbfwJhBoCJQwPDHdjexRnhGMoOt7JLCxB+qLWP5V4U6ZhvsYSxMaEZ x1qbJA3TEvKDyrsNusKiFgxi3c0CVDZfpPCwYhKlg8bRVAgzafsnPLQjlOe684/RXdmU EVrMZ8mQN9t1qEazImEgmnUN+bJuFdIKoCBeJ7cz0Kqe3AYZOO0ojYyzYye691b1lZ/W qRfHEVW3QEFZ0d0t4ZhlX8ZNRl3tuIvx0GrG8O325+eR0QYGv61Dq9wpJ8bYTpV2j3Dw FIU3DN0kNPC/Zc1ziGgpwA42vro3g1MWsiZISlVmMWgf5j9jp5PUmNZM+GApYyWnJonq nO3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689607165; x=1692199165; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mx86M5YQS8ymXI+vhUkZgSGnBjsFbSeN3nBqebJBsPs=; b=U97o9Et/xUEuWuyyWT2clWUCetCkrGDwIO7X58nTKVQyrbqAScp/1QkEu4MjaLIRiJ R9YmT0y0eqFG632WvmvTCqAWJlxjWi7f/5mdXAgxUgI0TQIvc/fiBAh9LntkGgrok2bl 5g9KO2KzOw7p0LDkaKRbeYjCv361qOdo4UxQL6LVRJye4vJ4BN5kCJ7d8CctvRSOjg7s QDxk504hC2O3J87YJyTU3GK4JOWptpI60q7aN1hJVkJffI4CcvP9+GNehsM36ZFcIX6S W7AVQHrGomNOCO6sInPa3pnfhn3UlLVkz/M/2m0lh2dosZ/l4JDs6iI/dJmA/GXuJzP4 lE7A== X-Gm-Message-State: ABy/qLZPAbmy9O87jKgAADrEk/utzt82L+Oyt0dBXq7PnoGzYgQUNcqc jihLCzumFg9terBemMZThLXBGA== X-Google-Smtp-Source: APBJJlF429YCiFOgbvSi+8scBlWlk5xW0hgHCNsF7hN0jSNrxvsUJNKLi1EEesPwRq6jNsFwvzZM/w== X-Received: by 2002:a05:6512:311b:b0:4f8:7897:55e6 with SMTP id n27-20020a056512311b00b004f8789755e6mr6798837lfb.45.1689607165533; Mon, 17 Jul 2023 08:19:25 -0700 (PDT) Received: from [192.168.1.101] (abyj181.neoplus.adsl.tpnet.pl. [83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:25 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:17 +0200 Subject: [PATCH 10/15] clk: qcom: gcc-qcm2290: Unregister critical clocks MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-10-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=6725; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=9cGrBLjkf/WHHpMBheuUWUOeDKVWRiwfgvREpTuuJGM=; b=epHujApYdIacicRVBFYoStpuG8TBPBgFBYfQlAGo4OFydyohxJA6rspQcP3JA6EwWPxIuuBMv UE5TYKpOB+WDQ2cRST1hLJDom70hMClEOCeNub5oACZG5f0KgO8Pis7 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some clocks need to be always-on, but we don't really do anything with them, other than calling enable() once and telling Linux they're enabled. Unregister them to save a couple of bytes and, perhaps more importantly, allow for runtime suspend of the clock controller device, as CLK_IS_CRITICAL prevents the latter. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-qcm2290.c | 114 ++++++----------------------------------- 1 file changed, 16 insertions(+), 98 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c index 48995e50c6bd..1a8acc2de921 100644 --- a/drivers/clk/qcom/gcc-qcm2290.c +++ b/drivers/clk/qcom/gcc-qcm2290.c @@ -1397,36 +1397,6 @@ static struct clk_branch gcc_cam_throttle_rt_clk = { }, }; -static struct clk_branch gcc_camera_ahb_clk = { - .halt_reg = 0x17008, - .halt_check = BRANCH_HALT_DELAY, - .hwcg_reg = 0x17008, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x17008, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_camera_xo_clk = { - .halt_reg = 0x17028, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x17028, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_camera_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_camss_axi_clk = { .halt_reg = 0x58044, .halt_check = BRANCH_HALT, @@ -1825,22 +1795,6 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { }, }; -static struct clk_branch gcc_disp_ahb_clk = { - .halt_reg = 0x1700c, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x1700c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x1700c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_regmap_div gcc_disp_gpll0_clk_src = { .reg = 0x17058, .shift = 0, @@ -1899,20 +1853,6 @@ static struct clk_branch gcc_disp_throttle_core_clk = { }, }; -static struct clk_branch gcc_disp_xo_clk = { - .halt_reg = 0x1702c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x1702c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_disp_xo_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gp1_clk = { .halt_reg = 0x4d000, .halt_check = BRANCH_HALT, @@ -1964,22 +1904,6 @@ static struct clk_branch gcc_gp3_clk = { }, }; -static struct clk_branch gcc_gpu_cfg_ahb_clk = { - .halt_reg = 0x36004, - .halt_check = BRANCH_HALT, - .hwcg_reg = 0x36004, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x36004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_gpu_cfg_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_gpu_gpll0_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -2439,22 +2363,6 @@ static struct clk_branch gcc_sdcc2_apps_clk = { }, }; -static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { - .halt_reg = 0x2b06c, - .halt_check = BRANCH_HALT_VOTED, - .hwcg_reg = 0x2b06c, - .hwcg_bit = 1, - .clkr = { - .enable_reg = 0x79004, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gcc_sys_noc_cpuss_ahb_clk", - .flags = CLK_IS_CRITICAL, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = { .halt_reg = 0x1a080, .halt_check = BRANCH_HALT, @@ -2774,8 +2682,6 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = { [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, [GCC_CAM_THROTTLE_NRT_CLK] = &gcc_cam_throttle_nrt_clk.clkr, [GCC_CAM_THROTTLE_RT_CLK] = &gcc_cam_throttle_rt_clk.clkr, - [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr, - [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr, [GCC_CAMSS_AXI_CLK] = &gcc_camss_axi_clk.clkr, [GCC_CAMSS_AXI_CLK_SRC] = &gcc_camss_axi_clk_src.clkr, [GCC_CAMSS_CAMNOC_ATB_CLK] = &gcc_camss_camnoc_atb_clk.clkr, @@ -2816,19 +2722,16 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = { [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, [GCC_CAMSS_TOP_AHB_CLK_SRC] = &gcc_camss_top_ahb_clk_src.clkr, [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, - [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr, [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr, [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr, [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr, - [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr, [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, - [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, @@ -2869,7 +2772,6 @@ static struct clk_regmap *gcc_qcm2290_clocks[] = { [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, - [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr, [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, @@ -2994,6 +2896,22 @@ static int gcc_qcm2290_probe(struct platform_device *pdev) clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config); clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config); + /* + * Keep clocks always enabled: + * GCC_CAMERA_AHB_CLK + * GCC_CAMERA_XO_CLK + * GCC_DISP_AHB_CLK + * GCC_DISP_XO_CLK + * GCC_GPU_CFG_AHB_CLK + * GCC_SYS_NOC_CPUSS_AHB_CLK + */ + qcom_branch_set_clk_en(regmap, 0x17008); + qcom_branch_set_clk_en(regmap, 0x17028); + qcom_branch_set_clk_en(regmap, 0x1700c); + qcom_branch_set_clk_en(regmap, 0x1702c); + qcom_branch_set_clk_en(regmap, 0x36004); + qcom_branch_set_clk_en(regmap, 0x2b06c); + return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap); } From patchwork Mon Jul 17 15:19:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13315895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EA78C001DC for ; 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[83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:26 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:18 +0200 Subject: [PATCH 11/15] clk: qcom: gcc-qcm2290: Add runtime PM MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-11-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=1980; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=SEE5Vf2kJq6CXu3dBwAauLybj1NpUkl0+Tc5/vKK29A=; b=xpHotqpRsd1M6m6fXXG+MlRWzVc91b4BPgGLqLB6PoDcJtO6t4WTluXgb8iW4mKZN3lEG/wW6 53LYl6aqR+mDtzTQEBZpmTgapcF2rbKk+1paoIbTctCdLj3Ur5Ddb2j X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GCC block on QCM2290 is mostly powered by the VDD_CX rail. We need to ensure that it's enabled to prevent unwanted power collapse. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-qcm2290.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c index 1a8acc2de921..573cb550d678 100644 --- a/drivers/clk/qcom/gcc-qcm2290.c +++ b/drivers/clk/qcom/gcc-qcm2290.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -2882,14 +2883,26 @@ static int gcc_qcm2290_probe(struct platform_device *pdev) struct regmap *regmap; int ret; + ret = devm_pm_runtime_enable(&pdev->dev); + if (ret) + return ret; + + ret = pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + regmap = qcom_cc_map(pdev, &gcc_qcm2290_desc); - if (IS_ERR(regmap)) + if (IS_ERR(regmap)) { + pm_runtime_put(&pdev->dev); return PTR_ERR(regmap); + } ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); - if (ret) + if (ret) { + pm_runtime_put(&pdev->dev); return ret; + } clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config); clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config); @@ -2912,7 +2925,10 @@ static int gcc_qcm2290_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x36004); qcom_branch_set_clk_en(regmap, 0x2b06c); - return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap); + pm_runtime_put(&pdev->dev); + + return ret; } static struct platform_driver gcc_qcm2290_driver = { From patchwork Mon Jul 17 15:19:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13315896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72ED5EB64DC for ; Mon, 17 Jul 2023 15:20:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231789AbjGQPUR (ORCPT ); Mon, 17 Jul 2023 11:20:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231623AbjGQPT4 (ORCPT ); Mon, 17 Jul 2023 11:19:56 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26B2F19A1 for ; Mon, 17 Jul 2023 08:19:30 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-4fb41682472so7381471e87.2 for ; Mon, 17 Jul 2023 08:19:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689607168; x=1692199168; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Hib3PW+pD9Vw/aBXh9phjmFHPMYV0WlytMyF3Y7iRI0=; b=ySpZsA4uVOf6a6NXu+CgSrkKV5uqya3BOQAA+PS1SpMmvBS6r5JwQ0aEyQoK9ZqMsS UKzy/px5q2FbmTiNEmBJRaPJguE6qdd+xTqVBW/b5QDk53EtVvk1y9m0IAAMrflxzaLd 4vV2BLae/ubxxUqgS42VH34WPIJ3kHI+D0siP70LlKBAFyIll6YRsjHiKeo8AcjyyIlK 0p7Yk0RvADkVXGaxhTZ7kHf8WBdlpu+U42L7zp4vJFluYWnwWEnrztiF2fRj3GZrInZb NLueirZg6JMDXq9CojQ1hzuIi4DwwPYtfRZKLw3xjnlpXcLNuKWJ5JwEwqymz6+cnfF+ ZNYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689607168; x=1692199168; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hib3PW+pD9Vw/aBXh9phjmFHPMYV0WlytMyF3Y7iRI0=; b=BHUSnTxaPAYr1lUQDyf0janqkA5t6r5ADZrsowPRd8zviicRtti6Z3CSlc1XT+AjT0 fbO7c+mepbLe6BjSJh4kDC8uZwdE9wjyMObUPnCPaQrlczdDipJKCMgVxkyyjHjNY5FW 7vb1YwcYxHda9cnXVAZE145dte+mmf1UFgwMsnZqGAdYhKmb5pwu7Y6/je2+NJnot7AV tyqFPbfVKti4/vQ0wPh/ME6A66mTDRS59odyPmptkKY06d4xjywXlcnjbNs5QQP7E6rE wiYVX20IWfY1kAQwCe8natvTjTV9/Vzxm/G/2a3k3XivURN+40NYQlZSjKWxHIe+0cIP ep6w== X-Gm-Message-State: ABy/qLZhDI1Gm+SBV9nEIawOY9IPpHBmQG3I0wUZiWDzdq2+tfJCfV/r wCKKxSK+ONJSsdhJ4+EC5RM2JA== X-Google-Smtp-Source: APBJJlHAd+cImmf9IAr9Szob0MMlVWb2rHb5jscP1K+qpg1C3WKfO7W8NAOaeuotXyJaqsYCyv3FXA== X-Received: by 2002:a05:6512:53b:b0:4fb:89bb:bcc5 with SMTP id o27-20020a056512053b00b004fb89bbbcc5mr11228445lfc.50.1689607168350; Mon, 17 Jul 2023 08:19:28 -0700 (PDT) Received: from [192.168.1.101] (abyj181.neoplus.adsl.tpnet.pl. [83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:27 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:19 +0200 Subject: [PATCH 12/15] arm64: dts: qcom: sm6375: Add VDD_CX to GCC MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-12-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=718; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=C5XEfW1WulMPJ7l5fdZmAX7BDZDcdKgcMmWnfi4QWbk=; b=lIIYO4AAgn3LQgFkNPM78AvqMep4285ACx41eHmSryMN4ieLlG+4MiBKsUD0PFHAb/5ggeJap upV1mIuDrvvC9e87w7J/sOYEIiT3vtWIVYbQWLFanqfT4fy1tBV90/8 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GCC block is mainly powered by VDD_CX. Describe that. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index e7ff55443da7..6fec45b54c98 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -904,6 +904,7 @@ gcc: clock-controller@1400000 { clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&sleep_clk>; + power-domains = <&rpmpd SM6375_VDDCX>; #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; From patchwork Mon Jul 17 15:19:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13315897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2C04EB64DC for ; Mon, 17 Jul 2023 15:20:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231946AbjGQPUX (ORCPT ); Mon, 17 Jul 2023 11:20:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231824AbjGQPT5 (ORCPT ); Mon, 17 Jul 2023 11:19:57 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 459711BC2 for ; Mon, 17 Jul 2023 08:19:31 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-4fbaef9871cso7269636e87.0 for ; Mon, 17 Jul 2023 08:19:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689607169; x=1692199169; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ZkK0zo9Pzls7HuP6fjOXcbL6dtei0B7+SlDRygwdvi8=; b=iR1XfiKEzrx7+T4BDT5YuM955j5yDVy9OhdERnmdlfO6RjaGQtzMIdoGtE5Mjjezhd +3j1ecAmLtYvr1aFTK2pqDTZrzdc3ZM9kn/IFosFTienwFzol7xDCNmw8CMda7YoK8lU KGMtE+Yqr92xe0eiLB8nHadioD/dWtJiq+xDuk87+eks7sSS17pGU/ISpC26N8a7Za4i bJaqmNZF2QcXv0EqFRsYsNIO0ZLF2Vuvcx1HT3933tK6NqnFtG2cRvIso7kjuoB2zal5 /6rCohkAuVVGnxTdP8pf0jNWBbe4YIv8BaHk5uA0MLxLEKtpHDOZrVfaymPL0+g/CZ0N lJlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689607169; x=1692199169; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZkK0zo9Pzls7HuP6fjOXcbL6dtei0B7+SlDRygwdvi8=; b=UV/RtPDuwnl3w+Cabdf2z/8FkHvWZ8bWdIwu6PMuh0HOgTEH4bznmOOFAYS/PvL+sW Z9n2XrwfLLDrJovjdwNdSjvqcONnBtrp15A+POU87ZnGDpt3fyZAZe8lI+Q3mR8lCkK+ 8fLKYup94MDi1Y85Iy7coLjhmn//gFbKaxVjUF4L9+uscEQiXHUKtGXgSGHddxXxhNxM TTfAO2tPEvG0ntx6KenSzBRjnN3aAxDoItRIbaStOzSJAAaupRjmwQnQWb8N6N995Zfo nbQocE9P6LbpKFUzn3UpgXiAtWDQmO5Qzxy0ty6lCEBoR7T7OraxaG6Vyn2w/O92Es7t vB2w== X-Gm-Message-State: ABy/qLauLd16ULS/N0ILzZd0y56T1EABHlVfjBplncZ342pXsiegLn2k 8JlQ7nA4x9z64k0TkptHog3srA== X-Google-Smtp-Source: APBJJlEUuPJiBCoXWIVpOX6xMff+ZiEeee+KaZXIUJ20OrKIlUEG/fh8XyOh0tXXq7iUZpHtW3OiOw== X-Received: by 2002:ac2:4546:0:b0:4fa:d522:a38e with SMTP id j6-20020ac24546000000b004fad522a38emr8262794lfm.35.1689607169690; Mon, 17 Jul 2023 08:19:29 -0700 (PDT) Received: from [192.168.1.101] (abyj181.neoplus.adsl.tpnet.pl. [83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:29 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:20 +0200 Subject: [PATCH 13/15] arm64: dts: qcom: qcm2290: Add VDD_CX to GCC MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-13-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=764; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=CPIjnOdtakV5i/cKNTsCCaP/1W9vDnorxYs0r/7/pcg=; b=WOkbSks1r0/0/zz3X2U6Fi1XiOfql7qbx696TFz4HDvz9aDWN8L/4R9cCn0Xe2bSuOw2blzri Ypn4itLVWWqA3FXGDaS4p66CG3cykA3YI6V/hCCKLXU3IpaKvRNXPf1 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GCC block is mainly powered by VDD_CX. Describe that. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index d46e591e72b5..a3191e3548c1 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -622,6 +622,7 @@ gcc: clock-controller@1400000 { reg = <0x0 0x01400000 0x0 0x1f0000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; clock-names = "bi_tcxo", "sleep_clk"; + power-domains = <&rpmpd QCM2290_VDDCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From patchwork Mon Jul 17 15:19:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13315898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89B59C00528 for ; Mon, 17 Jul 2023 15:20:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231827AbjGQPUY (ORCPT ); Mon, 17 Jul 2023 11:20:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231465AbjGQPT7 (ORCPT ); Mon, 17 Jul 2023 11:19:59 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 677431BD8 for ; Mon, 17 Jul 2023 08:19:33 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4fb960b7c9dso7454287e87.0 for ; Mon, 17 Jul 2023 08:19:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689607171; x=1692199171; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2ZVz0HHbNacYcZ7SswA3bwyZfWy1YH5AMNjeXJBFPFg=; b=rNZgbBZpPSV/suV6tgIxgg4kwXvvWfXFhsYAXsuDsXPyn3ogYa6AhAMB3K/eb7b9m0 kTlXUad7J2qcGe3C5yzvyjW8qyEJlPRWmHZQpZ7KdpM3bGqMkbFS8KfBSHYo9pGMv3Kz V3F+kyEZSClCsJYw06QomxibukGtsnZOUgJiBXHmbcM59vrI3TJrenZleJJAOvikgUiL TUASUEtBkdtCPDHxLhb+IzarEOgHsaTSrleD6nlrlFCzFftztEyK26g3Pl0l19DpeAtY dvEYD5Zi6rHZI2vcpNtuOW2puNkRGTXxXljnSoc7kwwDio5gAaPICN9qWfL2oAx278VE qqgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689607171; x=1692199171; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2ZVz0HHbNacYcZ7SswA3bwyZfWy1YH5AMNjeXJBFPFg=; b=A8BrQcOz6HaRtuXEwigWwKz2+eiVRBepcnejn9cWIsJHI6ZULl4faJPE19UoR2Pu5l MPes/xkKf1C8TqPVT2GadkRrIP005FJZaQFLs1glVkrNQXQbncKyGivLMQwaoqzKV2X1 NHeyrnere8MlTlh2IXjF+UqI3IhXspkWRM3Fh4acPAqtayUTqxkhpAbPacR/pQ6qG9NF c+llKZ+9eh3cbiQvWtJQyJMJHZa0vd+NuEZTgO8rku5M8ucn0IyPtGxJcGloNsqHQbhs 2h1B9Rfq9o5nTIheWVRqjL/WR5owfwrd4RDhaYbE+J5Mr8+1hW/EpKatQRB1AfJ9I0XT 2OvQ== X-Gm-Message-State: ABy/qLbEndhWt9PHTbos7wUJawZ1Lo8uljosMsWeG3c0ZJWmhsobCl6g dEb6T0dnYGmvX1Ki9T5WDqOIbw== X-Google-Smtp-Source: APBJJlE66n6oQEJ427y2dX9pgdTTKd00k6qtINgc9SZdc8nG9vgP5b0qivWIq4kYysk9vggbXLOGXg== X-Received: by 2002:a05:6512:304e:b0:4fb:89e3:5ac4 with SMTP id b14-20020a056512304e00b004fb89e35ac4mr9148515lfb.66.1689607171063; Mon, 17 Jul 2023 08:19:31 -0700 (PDT) Received: from [192.168.1.101] (abyj181.neoplus.adsl.tpnet.pl. [83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:30 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:21 +0200 Subject: [PATCH 14/15] arm64: dts: qcom: sm6115: Add VDD_CX to GCC MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-14-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=758; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=teCmvh/mH8/+KIQ6w2EiUF+9FzEW2n4wijD09cbH2a4=; b=Z6lj84tCtOpwyb5JGxRB90l01ovLnN0ixjCPdiYSidGzkn9vehSp80TM9eBEPDZtKZiNTZMJx jHf11RCWkK0CDgzc5nJ9DXHOh81HZwyCwcG3HSLvDV8PIeemm2MGyUo X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GCC block is mainly powered by VDD_CX. Describe that. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 839c60351240..29b5b388cd94 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -784,6 +784,7 @@ gcc: clock-controller@1400000 { reg = <0x0 0x01400000 0x0 0x1f0000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; clock-names = "bi_tcxo", "sleep_clk"; + power-domains = <&rpmpd SM6115_VDDCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From patchwork Mon Jul 17 15:19:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13315899 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B18C7C001B0 for ; Mon, 17 Jul 2023 15:20:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231931AbjGQPUo (ORCPT ); Mon, 17 Jul 2023 11:20:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231837AbjGQPUZ (ORCPT ); Mon, 17 Jul 2023 11:20:25 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31D092694 for ; Mon, 17 Jul 2023 08:19:53 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4fa48b5dc2eso7448289e87.1 for ; Mon, 17 Jul 2023 08:19:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689607172; x=1692199172; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6ucP2HxOwgP4Yjc3Q8ZZBgQ8j1uIc3OmiWC7cbRp7SQ=; b=aAsyFds6D3PMJEXo1mRw7yaSFEFyCwzpw8bc7QERWt12x+GbYXficzoCDkDyBo7h4Z 62Z6Rxu+5TMH3EeAAlv60yIOJkKs1lSTWu6iBieEmkUsquuIa11nMNQdHG1kcNXk6Jml vJ3dObu5l1Rzkk8/4WSFhvQI/+4XhyexGyeCk2bUjkLEU5rjBwlHMcklMQfaStrCnlHC 0xORplVjcyGhMZq87BeArmLClMW1oKgWZH6VyMbA1rowzdSZMO1VTIDvtjbCAqA2QdlV Wng487nS0xowQ1eGL8UF+0LXKbfRkU6VVCeJzJxiPeyy1m56qprgDRFCfjNPyi5WNzZ/ iDAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689607172; x=1692199172; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6ucP2HxOwgP4Yjc3Q8ZZBgQ8j1uIc3OmiWC7cbRp7SQ=; b=KNplKnflBGXCl1189HrWARfl6ueQ3v/MZKZRvwlwsEaHmWIl+txZCibU4nq5aM295t LhSLhYrfHN2a32kBvkp0GQZHvqDZKCXvsbipDaYIkp9sNOFdwVcTrQgHz91k/AaMSQFH Gx0+Dy9N8iTsJeEjp3g/KUw0FL5gGiS1jkJZmLqNoLpgNtx4FwxxVGP42Z8o4TOtgtfD LtcGUdKtTRdd9ktC6/x9wvzGFaN1k7QGzzAwxDN2dkIo3cPtLaiY+1KqizUEo+KxGfm+ EUIDxYyxYubPXI7n1K0B9+TAZ7TucUDXCcs0jOgeC+Ni/299oywm0NlHF6DKzUJ+18Ev fZfQ== X-Gm-Message-State: ABy/qLbslfuEhOnWVG2wOJrTxlz7ixs93jvCQzgm24j9PIvnqyvyxj3h bIYCW9OA8JSvJjUrQYd969ijI8EvnlF4kSDFoe35Ig== X-Google-Smtp-Source: APBJJlETFLB1UkIpgDT8VZRfl/t0P/UEyKDkNh0LsL4uDtc+FiFnAOYV9Piu5SCozU2cMNsEkgAryA== X-Received: by 2002:a05:6512:3121:b0:4f8:6533:3341 with SMTP id p1-20020a056512312100b004f865333341mr8483185lfd.20.1689607172501; Mon, 17 Jul 2023 08:19:32 -0700 (PDT) Received: from [192.168.1.101] (abyj181.neoplus.adsl.tpnet.pl. [83.9.29.181]) by smtp.gmail.com with ESMTPSA id z7-20020ac24187000000b004f26d63f823sm2873949lfh.237.2023.07.17.08.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 08:19:32 -0700 (PDT) From: Konrad Dybcio Date: Mon, 17 Jul 2023 17:19:22 +0200 Subject: [PATCH 15/15] arm64: dts: qcom: sm6115: Add VDD_CX to GPU_CCC MIME-Version: 1.0 Message-Id: <20230717-topic-branch_aon_cleanup-v1-15-27784d27a4f4@linaro.org> References: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> In-Reply-To: <20230717-topic-branch_aon_cleanup-v1-0-27784d27a4f4@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689607149; l=782; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=KUdFQ1vDlHA4ohS8EU78+JEQV/TntyZtIcOU/vB61S4=; b=PXU+1NIif1o8q606ns3V3Z9OE4O7LZWnqOhTWMcpM/+BblfkOHNE3GpDoGEyTgvH3VTTUBZrq TubYMkT6OmRDcWp5p4Sj2bY+QorleRofBFq1lfUNCd7lsYo875iG8b+ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GPU_CC block is powered by VDD_CX. Describe that. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 29b5b388cd94..bfaaa1801a4d 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1430,6 +1430,8 @@ gpucc: clock-controller@5990000 { clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmpd SM6115_VDDCX>; + required-opps = <&rpmpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>;