From patchwork Mon Jul 17 17:26:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13316077 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10E84EB64DC for ; Mon, 17 Jul 2023 17:27:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231139AbjGQR1P (ORCPT ); Mon, 17 Jul 2023 13:27:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230019AbjGQR1D (ORCPT ); Mon, 17 Jul 2023 13:27:03 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C42DBD; Mon, 17 Jul 2023 10:26:57 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-189-171.ewe-ip-backbone.de [91.248.189.171]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id C95EC66028F5; Mon, 17 Jul 2023 18:26:55 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1689614815; bh=E9QpBFx3OjWlRLEoFnsSGJDKU0c7IinxD+9ybLulYfM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gBd2jq4JHb9CE+ya1XOhEhR8MKtURZmk5lB5peFJDBeh0wOKk17+kgS9Nm7+Hhgcu qOh5mOdHVwJqaRFRLPSb2mtpgUa+weZKMTIfWhfBBUMJL1KX4zqgXU+i8nqP4Ys4ZA YqZ6FfDfHgAG8X+lXT+iuq+YzVtnzqGIfVVtZur9+umaXpmzUAAMSJ0oVdd/n7vcnn mlCT5fMjyhVTy91uj1/5o/yi1XBcgko8OTZSzbQSWmaBNERCxbnaTt6Ea5+4Xhrsvb QP69NWwHMMo1j1VpSErayFf4O6ZrLxo9WHyDL2CyiGpkf1/nBS++clnJnMr8ehOU7a b7jOZmADZrYiw== Received: by jupiter.universe (Postfix, from userid 1000) id 19AC7480C77; Mon, 17 Jul 2023 19:26:53 +0200 (CEST) From: Sebastian Reichel To: linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Serge Semin Cc: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 1/5] dt-bindings: PCI: dwc: improve msi handling Date: Mon, 17 Jul 2023 19:26:47 +0200 Message-Id: <20230717172651.64324-2-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230717172651.64324-1-sebastian.reichel@collabora.com> References: <20230717172651.64324-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Allow missing "msi" interrupt, iff the node has a "msi-map" property. Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/pci/snps,dw-pcie.yaml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index 1a83f0f65f19..abc1bcef13ec 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -25,6 +25,15 @@ select: allOf: - $ref: /schemas/pci/pci-bus.yaml# - $ref: /schemas/pci/snps,dw-pcie-common.yaml# + - if: + not: + required: + - msi-map + then: + properties: + interrupt-names: + contains: + const: "msi" properties: reg: @@ -193,9 +202,6 @@ properties: oneOf: - description: See native "app" IRQ for details enum: [ intr ] - allOf: - - contains: - const: msi additionalProperties: true From patchwork Mon Jul 17 17:26:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13316074 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40096C001B0 for ; Mon, 17 Jul 2023 17:27:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231146AbjGQR1M (ORCPT ); Mon, 17 Jul 2023 13:27:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229635AbjGQR1D (ORCPT ); Mon, 17 Jul 2023 13:27:03 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71176B9; Mon, 17 Jul 2023 10:26:57 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-189-171.ewe-ip-backbone.de [91.248.189.171]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id C41976602329; Mon, 17 Jul 2023 18:26:55 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1689614815; bh=zCQp1ogz508z6XY8UW74TYNiCI6zGXJQ14juwMUHFuY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PjuqyPP6FNMstblmNNyUcLTbaBHu8rFZqdVtn5U8dGvx5BsT+hLIeL+5r2GZkz1pg 3XWVdVZU611A1ThtQ3RwODScRqgLH89lNbzO4woyKOJnHF6LdW872MhtQATPH0OGBz U/hOlPCyXbjqRVdsY1uOi0UZvpMO2shCvAqNot1Qoa1oyXOYAyVRmpp5mo/ziUIB7A h4oIBUXIxgvCuGe1oTpobQXW3F/z/+b8sUDI3Z2OD1Q6cPIdTO9WP7m+E55e3s/UJl A+bfiinMWT6XMYuP9DE7cu1HE4GZ19xNYXxiuT89XZIdahMff2BtFxBQQ9t4A1CMm1 MBdB9ot1PoNuw== Received: by jupiter.universe (Postfix, from userid 1000) id 1BD67480C78; Mon, 17 Jul 2023 19:26:53 +0200 (CEST) From: Sebastian Reichel To: linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Serge Semin Cc: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 2/5] dt-bindings: PCI: dwc: rockchip: Fix interrupt-names issue Date: Mon, 17 Jul 2023 19:26:48 +0200 Message-Id: <20230717172651.64324-3-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230717172651.64324-1-sebastian.reichel@collabora.com> References: <20230717172651.64324-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The RK356x (and RK3588) have 5 ganged interrupts. For example the "legacy" interrupt combines "inta/intb/intc/intd" with a register providing the details. Currently the binding is not specifying these interrupts resulting in a bunch of errors for all rk356x boards using PCIe. Fix this by specifying the interrupts and add them to the example to prevent regressions. This changes the reference from snps,dw-pcie.yaml to snps,dw-pcie-common.yaml, since the interrupts are vendor specific and should not be listed in the generic file. The only other bit from the generic binding are the reg-names, which are overwritten by this binding. Signed-off-by: Sebastian Reichel --- .../bindings/pci/rockchip-dw-pcie.yaml | 43 ++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index a4f61ced5e88..7836b9a5547c 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -17,7 +17,8 @@ description: |+ snps,dw-pcie.yaml. allOf: - - $ref: /schemas/pci/snps,dw-pcie.yaml# + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/snps,dw-pcie-common.yaml# properties: compatible: @@ -60,6 +61,39 @@ properties: - const: aux - const: pipe + interrupts: + items: + - description: + Combined system interrupt, which is used to signal the following + interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, + hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, + edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app + - description: + Combined PM interrupt, which is used to signal the following + interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, + linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, + linkst_out_l0s, pm_dstate_update + - description: + Combined message interrupt, which is used to signal the following + interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, + pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active + - description: + Combined legacy interrupt, which is used to signal the following + interrupts - inta, intb, intc, intd + - description: + Combined error interrupt, which is used to signal the following + interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, + tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, + nf_err_rx, f_err_rx, radm_qoverflow + + interrupt-names: + items: + - const: sys + - const: pmc + - const: msg + - const: legacy + - const: err + msi-map: true num-lanes: true @@ -108,6 +142,7 @@ unevaluatedProperties: false examples: - | + #include bus { #address-cells = <2>; @@ -127,6 +162,12 @@ examples: "aclk_dbi", "pclk", "aux"; device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; linux,pci-domain = <2>; max-link-speed = <2>; msi-map = <0x2000 &its 0x2000 0x1000>; From patchwork Mon Jul 17 17:26:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13316076 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10E3EC001E0 for ; Mon, 17 Jul 2023 17:27:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231220AbjGQR1O (ORCPT ); Mon, 17 Jul 2023 13:27:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229884AbjGQR1D (ORCPT ); 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Mon, 17 Jul 2023 19:26:53 +0200 (CEST) From: Sebastian Reichel To: linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Serge Semin Cc: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 3/5] dt-bindings: PCI: dwc: rockchip: Use generic binding Date: Mon, 17 Jul 2023 19:26:49 +0200 Message-Id: <20230717172651.64324-4-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230717172651.64324-1-sebastian.reichel@collabora.com> References: <20230717172651.64324-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Use the generic binding for Rockchip. This should either be ignored/dropped or squashed into the previous commit. Signed-off-by: Sebastian Reichel --- Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 3 +-- Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 6 +++++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 7836b9a5547c..ad9954f7fe02 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -17,8 +17,7 @@ description: |+ snps,dw-pcie.yaml. allOf: - - $ref: /schemas/pci/pci-bus.yaml# - - $ref: /schemas/pci/snps,dw-pcie-common.yaml# + - $ref: /schemas/pci/snps,dw-pcie.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index abc1bcef13ec..95d343c75485 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -196,12 +196,16 @@ properties: Status register (the event is supposed to be unmasked in the Link Control register). const: bw_mg + - description: + Combined Legacy A/B/C/D interrupt signal. See "^int(a|b|c|d)$" for + details. + const: legacy - description: Vendor-specific IRQ names. Consider using the generic names above for new bindings. oneOf: - description: See native "app" IRQ for details - enum: [ intr ] + enum: [ intr, sys, pmc, msg, err ] additionalProperties: true From patchwork Mon Jul 17 17:26:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13316075 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA938C001DC for ; Mon, 17 Jul 2023 17:27:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231174AbjGQR1N (ORCPT ); Mon, 17 Jul 2023 13:27:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230500AbjGQR1D (ORCPT ); Mon, 17 Jul 2023 13:27:03 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF16AD8; Mon, 17 Jul 2023 10:26:57 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-189-171.ewe-ip-backbone.de [91.248.189.171]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id E09F86606FC8; Mon, 17 Jul 2023 18:26:55 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1689614816; bh=GALTLk1kp81TWDcsFroSmRcnp70s2ikSUk1HG3RlfRQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cZUsBZPo1A8U4vH4pXrI8+kODvY49w9R9s8Bz+sAvYJ6s81eW9IL/9fHAQ5b30ZlH tQZa/pCyp5f2FzezGXpQGbAKmIb7mmxWwlBJU5YMGVS4FukE/HswiUgOn2HiLasLpa sYXVwsyu81hz8eLju/qLDwAhVz2IDbq3amZfGnFYgbAjW4Z3NuAcWtqEhSKPa9+NOB XuDHyHbZiv1/Q7vIgCnkRsAD42yrtPXOKOZgGUnqSLMlYrYFZTpceESix/i5XJZOCk e9fV/ZLZJl6joamxDS9PxW5sW+wbPC30ZRna+SyZ1Ggs6gJCA+mTLAfeYV8Yw0qQ8g F+31a4qQxOUKA== Received: by jupiter.universe (Postfix, from userid 1000) id 1EE9D480C7A; Mon, 17 Jul 2023 19:26:53 +0200 (CEST) From: Sebastian Reichel To: linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Serge Semin Cc: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v3 4/5] dt-bindings: PCI: dwc: rockchip: Add missing legacy-interrupt-controller Date: Mon, 17 Jul 2023 19:26:50 +0200 Message-Id: <20230717172651.64324-5-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230717172651.64324-1-sebastian.reichel@collabora.com> References: <20230717172651.64324-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rockchip RK356x and RK3588 handle legacy interrupts via a ganged interrupts. The RK356x DT implements this via a sub-node named "legacy-interrupt-controller", just like a couple of other PCIe implementations. This adds proper documentation for this and updates the example to avoid regressions. Reviewed-by: Rob Herring Signed-off-by: Sebastian Reichel --- .../bindings/pci/rockchip-dw-pcie.yaml | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index ad9954f7fe02..1ae8dcfa072c 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -93,6 +93,28 @@ properties: - const: legacy - const: err + legacy-interrupt-controller: + description: Interrupt controller node for handling legacy PCI interrupts. + type: object + additionalProperties: false + properties: + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + interrupt-controller: true + + interrupts: + items: + - description: combined legacy interrupt + required: + - "#address-cells" + - "#interrupt-cells" + - interrupt-controller + - interrupts + msi-map: true num-lanes: true @@ -180,6 +202,14 @@ examples: reset-names = "pipe"; #address-cells = <3>; #size-cells = <2>; + + legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; }; }; ... From patchwork Mon Jul 17 17:26:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 13316079 X-Patchwork-Delegate: robh@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70D82C001DC for ; Mon, 17 Jul 2023 17:27:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230500AbjGQR1T (ORCPT ); Mon, 17 Jul 2023 13:27:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230527AbjGQR1M (ORCPT ); Mon, 17 Jul 2023 13:27:12 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B898991; Mon, 17 Jul 2023 10:27:03 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-189-171.ewe-ip-backbone.de [91.248.189.171]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 506E6660701C; Mon, 17 Jul 2023 18:26:58 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1689614818; bh=iJEV5hp8TWN3be/f2X5Jvjfl1ZZIqLvw4EgQ1zURuRM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=amNXOZA5M4AahwkI/tBTxFzARFVnwQTiWDEiZ8aExhCDyIdFSr7pdLtc5OEHL2DZY Ej/3aM/rgiY0HgFFkLcvuooC/xkykLdHKhSp8KiBjw27Qg0FNROV6D/GgTb/sYiQ8G d3LMG7Lb7bFG1uHlmSkKkxCBQuKku2oz6xtdZrSwEzQxj8pXbeSi37dWBT7hPsaAN0 uzyK1y0awcip1zy5y4te9EwYVOu3ER5SAUs0QUznTKED2HkbXyiH8/1IXqDkCAF5Ig MFG04QJ6kpizjL9gtfm+RBP31+UtlYRrkUa6YDkduivEj0qgi+DdGltx9GuxHICqif PdEMC3lvWMPzA== Received: by jupiter.universe (Postfix, from userid 1000) id 208EE480C7B; Mon, 17 Jul 2023 19:26:53 +0200 (CEST) From: Sebastian Reichel To: linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Serge Semin Cc: Jingoo Han , Gustavo Pimentel , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sebastian Reichel , kernel@collabora.com, Kever Yang , Jagan Teki Subject: [PATCH v3 5/5] arm64: dts: rockchip: rk3588: add PCIe2 support Date: Mon, 17 Jul 2023 19:26:51 +0200 Message-Id: <20230717172651.64324-6-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230717172651.64324-1-sebastian.reichel@collabora.com> References: <20230717172651.64324-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add all three PCIe2 IP blocks to the RK3588 DT. Note, that RK3588 also has two PCIe3 IP blocks, that will be handled separately. Co-developed-by: Kever Yang Signed-off-by: Kever Yang Tested-by: Jagan Teki # edgeble-neu6a, 6b Reviewed-by: Jagan Teki Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 51 +++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 102 ++++++++++++++++++++++ 2 files changed, 153 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 6be9bf81c09c..88d702575db2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -80,6 +80,57 @@ i2s10_8ch: i2s@fde00000 { status = "disabled"; }; + pcie2x1l0: pcie@fe170000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, + <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, + <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, + <0 0 0 2 &pcie2x1l0_intc 1>, + <0 0 0 3 &pcie2x1l0_intc 2>, + <0 0 0 4 &pcie2x1l0_intc 3>; + linux,pci-domain = <2>; + max-link-speed = <2>; + msi-map = <0x2000 &its0 0x2000 0x1000>; + num-lanes = <1>; + phys = <&combphy1_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; + reg = <0xa 0x40800000 0x0 0x00400000>, + <0x0 0xfe170000 0x0 0x00010000>, + <0x0 0xf2000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie2x1l0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + gmac0: ethernet@fe1b0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1b0000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index c9f9dd2472f5..b9b509257aaa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1227,6 +1227,108 @@ qos_vop_m1: qos@fdf82200 { reg = <0x0 0xfdf82200 0x0 0x20>; }; + pcie2x1l1: pcie@fe180000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x30 0x3f>; + clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, + <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, + <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, + <0 0 0 2 &pcie2x1l1_intc 1>, + <0 0 0 3 &pcie2x1l1_intc 2>, + <0 0 0 4 &pcie2x1l1_intc 3>; + linux,pci-domain = <3>; + max-link-speed = <2>; + msi-map = <0x3000 &its0 0x3000 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, + <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; + reg = <0xa 0x40c00000 0x0 0x00400000>, + <0x0 0xfe180000 0x0 0x00010000>, + <0x0 0xf3000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie2x1l1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pcie2x1l2: pcie@fe190000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x40 0x4f>; + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, + <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain = <4>; + max-link-speed = <2>; + msi-map = <0x4000 &its0 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; + reg = <0xa 0x41000000 0x0 0x00400000>, + <0x0 0xfe190000 0x0 0x00010000>, + <0x0 0xf4000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + gmac1: ethernet@fe1c0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1c0000 0x0 0x10000>;