From patchwork Tue Jul 18 14:11:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13317348 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FEBEC001DC for ; Tue, 18 Jul 2023 14:11:40 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.8578.1689689493732484416 for ; Tue, 18 Jul 2023 07:11:35 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.01,214,1684767600"; d="scan'208";a="173413952" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 18 Jul 2023 23:11:35 +0900 Received: from localhost.localdomain (unknown [10.226.92.137]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 704534007F26; Tue, 18 Jul 2023 23:11:33 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Fabrizio Castro Subject: [PATCH 6.1.y-cip 1/6] arm64: dts: renesas: rzg2lc-smarc: Include SoM DTSI into board DTS Date: Tue, 18 Jul 2023 15:11:24 +0100 Message-Id: <20230718141129.119809-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230718141129.119809-1-biju.das.jz@bp.renesas.com> References: <20230718141129.119809-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jul 2023 14:11:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/12392 From: Lad Prabhakar commit 29df86bbbad007eb1863c9d31473122c87c3e771 upstream. Move including the rzg2lc-smarc-som.dtsi from the carrier board rzg2lc-smarc.dtsi to the actual RZ/G2LC SMARC EVK board dts r9a07g044c2-smarc.dts. Also move the SW1 related macros along with PMOD1_SER0 to board dts so that we have all the configuration options in the same file. This patch is to keep consistency with other SMARC EVKs (RZ/G2L, RZ/G2UL) and it makes sense not include the SoM into the carrier board as we might in future have a different carrier board with the same SoM. Suggested-by: Geert Uytterhoeven Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220919092130.93074-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- .../boot/dts/renesas/r9a07g044c2-smarc.dts | 30 +++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 28 ----------------- 2 files changed, 30 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index fc34058002e2..f67a6f125d9c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -6,7 +6,37 @@ */ /dts-v1/; + +/* + * DIP-Switch SW1 setting on SoM + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD) + * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1) + * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1) + * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0) + * Please change below macros according to SW1 setting + */ + +#define SW_SD0_DEV_SEL 1 + +#define SW_SCIF_CAN 0 +#if (SW_SCIF_CAN) +/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */ +#define SW_RSPI_CAN 0 +#else +/* Please set SW_RSPI_CAN. Default value is 1 */ +#define SW_RSPI_CAN 1 +#endif + +#if (SW_SCIF_CAN && SW_RSPI_CAN) +#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" +#endif + +/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + #include "r9a07g044c2.dtsi" +#include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc.dtsi" / { diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 6be25a8a28db..b6bd27196d88 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -8,37 +8,9 @@ #include #include -/* - * DIP-Switch SW1 setting on SoM - * 1 : High; 0: Low - * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD) - * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1) - * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1) - * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0) - * Please change below macros according to SW1 setting - */ - -#define SW_SD0_DEV_SEL 1 - -#define SW_SCIF_CAN 0 -#if (SW_SCIF_CAN) -/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */ -#define SW_RSPI_CAN 0 -#else -/* Please set SW_RSPI_CAN. Default value is 1 */ -#define SW_RSPI_CAN 1 -#endif - -#if (SW_SCIF_CAN && SW_RSPI_CAN) -#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" -#endif - -#include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" -/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ -#define PMOD1_SER0 1 / { aliases { From patchwork Tue Jul 18 14:11:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13317346 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01C75EB64DA for ; Tue, 18 Jul 2023 14:11:40 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.8584.1689689497866713402 for ; Tue, 18 Jul 2023 07:11:38 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.01,214,1684767600"; d="scan'208";a="169768602" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 18 Jul 2023 23:11:37 +0900 Received: from localhost.localdomain (unknown [10.226.92.137]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A3089400F736; Tue, 18 Jul 2023 23:11:35 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Fabrizio Castro Subject: [PATCH 6.1.y-cip 2/6] arm64: defconfig: Enable Renesas MTU3a counter config Date: Tue, 18 Jul 2023 15:11:25 +0100 Message-Id: <20230718141129.119809-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230718141129.119809-1-biju.das.jz@bp.renesas.com> References: <20230718141129.119809-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jul 2023 14:11:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/12393 commit cacde5cc9dbc1af46a5d35efd17365bc3324b4fb upstream. Enable MFD & counter related configs for Renesas MTU3a Counter as it is populated on RZ/{G2L, LC, UL} and RZ/V2L SMARC EVKs. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230417100607.309068-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 9110a0f1b272..3164657aa297 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -653,6 +653,7 @@ CONFIG_MFD_SPMI_PMIC=y CONFIG_MFD_RK808=y CONFIG_MFD_SEC_CORE=y CONFIG_MFD_SL28CPLD=y +CONFIG_RZ_MTU3=y CONFIG_MFD_ROHM_BD718XX=y CONFIG_MFD_WCD934X=m CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -1309,6 +1310,8 @@ CONFIG_INTERCONNECT_QCOM_SM8150=m CONFIG_INTERCONNECT_QCOM_SM8250=m CONFIG_INTERCONNECT_QCOM_SM8350=m CONFIG_INTERCONNECT_QCOM_SM8450=m +CONFIG_COUNTER=m +CONFIG_RZ_MTU3_CNT=m CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS_POSIX_ACL=y From patchwork Tue Jul 18 14:11:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13317350 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E96CCC0015E for ; Tue, 18 Jul 2023 14:11:49 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.8584.1689689497866713402 for ; Tue, 18 Jul 2023 07:11:40 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.01,214,1684767600"; d="scan'208";a="169768612" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 18 Jul 2023 23:11:39 +0900 Received: from localhost.localdomain (unknown [10.226.92.137]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id D46524007F26; Tue, 18 Jul 2023 23:11:37 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Fabrizio Castro Subject: [PATCH 6.1.y-cip 3/6] pwm: Add Renesas RZ/G2L MTU3a PWM driver Date: Tue, 18 Jul 2023 15:11:26 +0100 Message-Id: <20230718141129.119809-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230718141129.119809-1-biju.das.jz@bp.renesas.com> References: <20230718141129.119809-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jul 2023 14:11:49 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/12394 commit 254d3a727421ccc935f085eaa9bae51cb6c9df25 upstream. The RZ/G2L Multi-Function Timer Pulse Unit 3 (a.k.a MTU3a) uses one counter and two match components to configure duty_cycle and period to generate PWM output waveform. Add basic support for RZ/G2L MTU3a PWM driver by creating separate PWM channels for each IOs. Signed-off-by: Biju Das Reviewed-by: Uwe Kleine-König Signed-off-by: Thierry Reding Signed-off-by: Biju Das --- drivers/pwm/Kconfig | 11 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-rz-mtu3.c | 551 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 563 insertions(+) create mode 100644 drivers/pwm/pwm-rz-mtu3.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 60d13a949bc5..18a7cc6a7fc9 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -481,6 +481,17 @@ config PWM_ROCKCHIP Generic PWM framework driver for the PWM controller found on Rockchip SoCs. +config PWM_RZ_MTU3 + tristate "Renesas RZ/G2L MTU3a PWM Timer support" + depends on RZ_MTU3 || COMPILE_TEST + depends on HAS_IOMEM + help + This driver exposes the MTU3a PWM Timer controller found in Renesas + RZ/G2L like chips through the PWM API. + + To compile this driver as a module, choose M here: the module + will be called pwm-rz-mtu3. + config PWM_SAMSUNG tristate "Samsung PWM support" depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 7bf1a29f02b8..b85fc9fba326 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_PWM_RASPBERRYPI_POE) += pwm-raspberrypi-poe.o obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o +obj-$(CONFIG_PWM_RZ_MTU3) += pwm-rz-mtu3.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o diff --git a/drivers/pwm/pwm-rz-mtu3.c b/drivers/pwm/pwm-rz-mtu3.c new file mode 100644 index 000000000000..bed8bd671e37 --- /dev/null +++ b/drivers/pwm/pwm-rz-mtu3.c @@ -0,0 +1,551 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G2L MTU3a PWM Timer driver + * + * Copyright (C) 2023 Renesas Electronics Corporation + * + * Hardware manual for this IP can be found here + * https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?language=en + * + * Limitations: + * - When PWM is disabled, the output is driven to Hi-Z. + * - While the hardware supports both polarities, the driver (for now) + * only handles normal polarity. + * - HW uses one counter and two match components to configure duty_cycle + * and period. + * - Multi-Function Timer Pulse Unit (a.k.a MTU) has 7 HW channels for PWM + * operations. (The channels are MTU{0..4, 6, 7}.) + * - MTU{1, 2} channels have a single IO, whereas all other HW channels have + * 2 IOs. + * - Each IO is modelled as an independent PWM channel. + * - rz_mtu3_channel_io_map table is used to map the PWM channel to the + * corresponding HW channel as there are difference in number of IOs + * between HW channels. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RZ_MTU3_MAX_PWM_CHANNELS 12 +#define RZ_MTU3_MAX_HW_CHANNELS 7 + +/** + * struct rz_mtu3_channel_io_map - MTU3 pwm channel map + * + * @base_pwm_number: First PWM of a channel + * @num: number of IOs on the HW channel. + */ +struct rz_mtu3_channel_io_map { + u8 base_pwm_number; + u8 num_channel_ios; +}; + +/** + * struct rz_mtu3_pwm_channel - MTU3 pwm channel data + * + * @mtu: MTU3 channel data + * @map: MTU3 pwm channel map + */ +struct rz_mtu3_pwm_channel { + struct rz_mtu3_channel *mtu; + const struct rz_mtu3_channel_io_map *map; +}; + +/** + * struct rz_mtu3_pwm_chip - MTU3 pwm private data + * + * @chip: MTU3 pwm chip data + * @clk: MTU3 module clock + * @lock: Lock to prevent concurrent access for usage count + * @rate: MTU3 clock rate + * @user_count: MTU3 usage count + * @enable_count: MTU3 enable count + * @prescale: MTU3 prescale + * @channel_data: MTU3 pwm channel data + */ + +struct rz_mtu3_pwm_chip { + struct pwm_chip chip; + struct clk *clk; + struct mutex lock; + unsigned long rate; + u32 user_count[RZ_MTU3_MAX_HW_CHANNELS]; + u32 enable_count[RZ_MTU3_MAX_HW_CHANNELS]; + u8 prescale[RZ_MTU3_MAX_HW_CHANNELS]; + struct rz_mtu3_pwm_channel channel_data[RZ_MTU3_MAX_HW_CHANNELS]; +}; + +/* + * The MTU channels are {0..4, 6, 7} and the number of IO on MTU1 + * and MTU2 channel is 1 compared to 2 on others. + */ +static const struct rz_mtu3_channel_io_map channel_map[] = { + { 0, 2 }, { 2, 1 }, { 3, 1 }, { 4, 2 }, { 6, 2 }, { 8, 2 }, { 10, 2 } +}; + +static inline struct rz_mtu3_pwm_chip *to_rz_mtu3_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct rz_mtu3_pwm_chip, chip); +} + +static void rz_mtu3_pwm_read_tgr_registers(struct rz_mtu3_pwm_channel *priv, + u16 reg_pv_offset, u16 *pv_val, + u16 reg_dc_offset, u16 *dc_val) +{ + *pv_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_pv_offset); + *dc_val = rz_mtu3_16bit_ch_read(priv->mtu, reg_dc_offset); +} + +static void rz_mtu3_pwm_write_tgr_registers(struct rz_mtu3_pwm_channel *priv, + u16 reg_pv_offset, u16 pv_val, + u16 reg_dc_offset, u16 dc_val) +{ + rz_mtu3_16bit_ch_write(priv->mtu, reg_pv_offset, pv_val); + rz_mtu3_16bit_ch_write(priv->mtu, reg_dc_offset, dc_val); +} + +static u8 rz_mtu3_pwm_calculate_prescale(struct rz_mtu3_pwm_chip *rz_mtu3, + u64 period_cycles) +{ + u32 prescaled_period_cycles; + u8 prescale; + + /* + * Supported prescale values are 1, 4, 16 and 64. + * TODO: Support prescale values 2, 8, 32, 256 and 1024. + */ + prescaled_period_cycles = period_cycles >> 16; + if (prescaled_period_cycles >= 16) + prescale = 3; + else + prescale = (fls(prescaled_period_cycles) + 1) / 2; + + return prescale; +} + +static struct rz_mtu3_pwm_channel * +rz_mtu3_get_channel(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, u32 hwpwm) +{ + struct rz_mtu3_pwm_channel *priv = rz_mtu3_pwm->channel_data; + unsigned int ch; + + for (ch = 0; ch < RZ_MTU3_MAX_HW_CHANNELS; ch++, priv++) { + if (priv->map->base_pwm_number + priv->map->num_channel_ios > hwpwm) + break; + } + + return priv; +} + +static bool rz_mtu3_pwm_is_ch_enabled(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, + u32 hwpwm) +{ + struct rz_mtu3_pwm_channel *priv; + bool is_channel_en; + u8 val; + + priv = rz_mtu3_get_channel(rz_mtu3_pwm, hwpwm); + is_channel_en = rz_mtu3_is_enabled(priv->mtu); + if (!is_channel_en) + return false; + + if (priv->map->base_pwm_number == hwpwm) + val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORH); + else + val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TIORL); + + return val & RZ_MTU3_TIOR_IOA; +} + +static int rz_mtu3_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); + struct rz_mtu3_pwm_channel *priv; + bool is_mtu3_channel_available; + u32 ch; + + priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); + ch = priv - rz_mtu3_pwm->channel_data; + + mutex_lock(&rz_mtu3_pwm->lock); + /* + * Each channel must be requested only once, so if the channel + * serves two PWMs and the other is already requested, skip over + * rz_mtu3_request_channel() + */ + if (!rz_mtu3_pwm->user_count[ch]) { + is_mtu3_channel_available = rz_mtu3_request_channel(priv->mtu); + if (!is_mtu3_channel_available) { + mutex_unlock(&rz_mtu3_pwm->lock); + return -EBUSY; + } + } + + rz_mtu3_pwm->user_count[ch]++; + mutex_unlock(&rz_mtu3_pwm->lock); + + return 0; +} + +static void rz_mtu3_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); + struct rz_mtu3_pwm_channel *priv; + u32 ch; + + priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); + ch = priv - rz_mtu3_pwm->channel_data; + + mutex_lock(&rz_mtu3_pwm->lock); + rz_mtu3_pwm->user_count[ch]--; + if (!rz_mtu3_pwm->user_count[ch]) + rz_mtu3_release_channel(priv->mtu); + + mutex_unlock(&rz_mtu3_pwm->lock); +} + +static int rz_mtu3_pwm_enable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, + struct pwm_device *pwm) +{ + struct rz_mtu3_pwm_channel *priv; + u32 ch; + u8 val; + int rc; + + rc = pm_runtime_resume_and_get(rz_mtu3_pwm->chip.dev); + if (rc) + return rc; + + priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); + ch = priv - rz_mtu3_pwm->channel_data; + val = RZ_MTU3_TIOR_OC_IOB_TOGGLE | RZ_MTU3_TIOR_OC_IOA_H_COMP_MATCH; + + rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TMDR1, RZ_MTU3_TMDR1_MD_PWMMODE1); + if (priv->map->base_pwm_number == pwm->hwpwm) + rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, val); + else + rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, val); + + mutex_lock(&rz_mtu3_pwm->lock); + if (!rz_mtu3_pwm->enable_count[ch]) + rz_mtu3_enable(priv->mtu); + + rz_mtu3_pwm->enable_count[ch]++; + mutex_unlock(&rz_mtu3_pwm->lock); + + return 0; +} + +static void rz_mtu3_pwm_disable(struct rz_mtu3_pwm_chip *rz_mtu3_pwm, + struct pwm_device *pwm) +{ + struct rz_mtu3_pwm_channel *priv; + u32 ch; + + priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); + ch = priv - rz_mtu3_pwm->channel_data; + + /* Disable output pins of MTU3 channel */ + if (priv->map->base_pwm_number == pwm->hwpwm) + rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORH, RZ_MTU3_TIOR_OC_RETAIN); + else + rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TIORL, RZ_MTU3_TIOR_OC_RETAIN); + + mutex_lock(&rz_mtu3_pwm->lock); + rz_mtu3_pwm->enable_count[ch]--; + if (!rz_mtu3_pwm->enable_count[ch]) + rz_mtu3_disable(priv->mtu); + + mutex_unlock(&rz_mtu3_pwm->lock); + + pm_runtime_put_sync(rz_mtu3_pwm->chip.dev); +} + +static int rz_mtu3_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); + int rc; + + rc = pm_runtime_resume_and_get(chip->dev); + if (rc) + return rc; + + state->enabled = rz_mtu3_pwm_is_ch_enabled(rz_mtu3_pwm, pwm->hwpwm); + if (state->enabled) { + struct rz_mtu3_pwm_channel *priv; + u8 prescale, val; + u16 dc, pv; + u64 tmp; + + priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); + if (priv->map->base_pwm_number == pwm->hwpwm) + rz_mtu3_pwm_read_tgr_registers(priv, RZ_MTU3_TGRA, &pv, + RZ_MTU3_TGRB, &dc); + else + rz_mtu3_pwm_read_tgr_registers(priv, RZ_MTU3_TGRC, &pv, + RZ_MTU3_TGRD, &dc); + + val = rz_mtu3_8bit_ch_read(priv->mtu, RZ_MTU3_TCR); + prescale = FIELD_GET(RZ_MTU3_TCR_TPCS, val); + + /* With prescale <= 7 and pv <= 0xffff this doesn't overflow. */ + tmp = NSEC_PER_SEC * (u64)pv << (2 * prescale); + state->period = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate); + tmp = NSEC_PER_SEC * (u64)dc << (2 * prescale); + state->duty_cycle = DIV_ROUND_UP_ULL(tmp, rz_mtu3_pwm->rate); + + if (state->duty_cycle > state->period) + state->duty_cycle = state->period; + } + + state->polarity = PWM_POLARITY_NORMAL; + pm_runtime_put(chip->dev); + + return 0; +} + +static u16 rz_mtu3_pwm_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale) +{ + return min(period_or_duty_cycle >> (2 * prescale), (u64)U16_MAX); +} + +static int rz_mtu3_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); + struct rz_mtu3_pwm_channel *priv; + u64 period_cycles; + u64 duty_cycles; + u8 prescale; + u16 pv, dc; + u8 val; + u32 ch; + + priv = rz_mtu3_get_channel(rz_mtu3_pwm, pwm->hwpwm); + ch = priv - rz_mtu3_pwm->channel_data; + + period_cycles = mul_u64_u32_div(state->period, rz_mtu3_pwm->rate, + NSEC_PER_SEC); + prescale = rz_mtu3_pwm_calculate_prescale(rz_mtu3_pwm, period_cycles); + + /* + * Prescalar is shared by multiple channels, so prescale can + * NOT be modified when there are multiple channels in use with + * different settings. Modify prescalar if other PWM is off or handle + * it, if current prescale value is less than the one we want to set. + */ + if (rz_mtu3_pwm->enable_count[ch] > 1) { + if (rz_mtu3_pwm->prescale[ch] > prescale) + return -EBUSY; + + prescale = rz_mtu3_pwm->prescale[ch]; + } + + pv = rz_mtu3_pwm_calculate_pv_or_dc(period_cycles, prescale); + + duty_cycles = mul_u64_u32_div(state->duty_cycle, rz_mtu3_pwm->rate, + NSEC_PER_SEC); + dc = rz_mtu3_pwm_calculate_pv_or_dc(duty_cycles, prescale); + + /* + * If the PWM channel is disabled, make sure to turn on the clock + * before writing the register. + */ + if (!pwm->state.enabled) { + int rc; + + rc = pm_runtime_resume_and_get(chip->dev); + if (rc) + return rc; + } + + val = RZ_MTU3_TCR_CKEG_RISING | prescale; + + /* Counter must be stopped while updating TCR register */ + if (rz_mtu3_pwm->prescale[ch] != prescale && rz_mtu3_pwm->enable_count[ch]) + rz_mtu3_disable(priv->mtu); + + if (priv->map->base_pwm_number == pwm->hwpwm) { + rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR, + RZ_MTU3_TCR_CCLR_TGRA | val); + rz_mtu3_pwm_write_tgr_registers(priv, RZ_MTU3_TGRA, pv, + RZ_MTU3_TGRB, dc); + } else { + rz_mtu3_8bit_ch_write(priv->mtu, RZ_MTU3_TCR, + RZ_MTU3_TCR_CCLR_TGRC | val); + rz_mtu3_pwm_write_tgr_registers(priv, RZ_MTU3_TGRC, pv, + RZ_MTU3_TGRD, dc); + } + + if (rz_mtu3_pwm->prescale[ch] != prescale) { + /* + * Prescalar is shared by multiple channels, we cache the + * prescalar value from first enabled channel and use the same + * value for both channels. + */ + rz_mtu3_pwm->prescale[ch] = prescale; + + if (rz_mtu3_pwm->enable_count[ch]) + rz_mtu3_enable(priv->mtu); + } + + /* If the PWM is not enabled, turn the clock off again to save power. */ + if (!pwm->state.enabled) + pm_runtime_put(chip->dev); + + return 0; +} + +static int rz_mtu3_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = to_rz_mtu3_pwm_chip(chip); + bool enabled = pwm->state.enabled; + int ret; + + if (state->polarity != PWM_POLARITY_NORMAL) + return -EINVAL; + + if (!state->enabled) { + if (enabled) + rz_mtu3_pwm_disable(rz_mtu3_pwm, pwm); + + return 0; + } + + mutex_lock(&rz_mtu3_pwm->lock); + ret = rz_mtu3_pwm_config(chip, pwm, state); + mutex_unlock(&rz_mtu3_pwm->lock); + if (ret) + return ret; + + if (!enabled) + ret = rz_mtu3_pwm_enable(rz_mtu3_pwm, pwm); + + return ret; +} + +static const struct pwm_ops rz_mtu3_pwm_ops = { + .request = rz_mtu3_pwm_request, + .free = rz_mtu3_pwm_free, + .get_state = rz_mtu3_pwm_get_state, + .apply = rz_mtu3_pwm_apply, + .owner = THIS_MODULE, +}; + +static int rz_mtu3_pwm_pm_runtime_suspend(struct device *dev) +{ + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = dev_get_drvdata(dev); + + clk_disable_unprepare(rz_mtu3_pwm->clk); + + return 0; +} + +static int rz_mtu3_pwm_pm_runtime_resume(struct device *dev) +{ + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = dev_get_drvdata(dev); + + return clk_prepare_enable(rz_mtu3_pwm->clk); +} + +static DEFINE_RUNTIME_DEV_PM_OPS(rz_mtu3_pwm_pm_ops, + rz_mtu3_pwm_pm_runtime_suspend, + rz_mtu3_pwm_pm_runtime_resume, NULL); + +static void rz_mtu3_pwm_pm_disable(void *data) +{ + struct rz_mtu3_pwm_chip *rz_mtu3_pwm = data; + + clk_rate_exclusive_put(rz_mtu3_pwm->clk); + pm_runtime_disable(rz_mtu3_pwm->chip.dev); + pm_runtime_set_suspended(rz_mtu3_pwm->chip.dev); +} + +static int rz_mtu3_pwm_probe(struct platform_device *pdev) +{ + struct rz_mtu3 *parent_ddata = dev_get_drvdata(pdev->dev.parent); + struct rz_mtu3_pwm_chip *rz_mtu3_pwm; + struct device *dev = &pdev->dev; + unsigned int i, j = 0; + int ret; + + rz_mtu3_pwm = devm_kzalloc(&pdev->dev, sizeof(*rz_mtu3_pwm), GFP_KERNEL); + if (!rz_mtu3_pwm) + return -ENOMEM; + + rz_mtu3_pwm->clk = parent_ddata->clk; + + for (i = 0; i < RZ_MTU_NUM_CHANNELS; i++) { + if (i == RZ_MTU3_CHAN_5 || i == RZ_MTU3_CHAN_8) + continue; + + rz_mtu3_pwm->channel_data[j].mtu = &parent_ddata->channels[i]; + rz_mtu3_pwm->channel_data[j].mtu->dev = dev; + rz_mtu3_pwm->channel_data[j].map = &channel_map[j]; + j++; + } + + mutex_init(&rz_mtu3_pwm->lock); + platform_set_drvdata(pdev, rz_mtu3_pwm); + ret = clk_prepare_enable(rz_mtu3_pwm->clk); + if (ret) + return dev_err_probe(dev, ret, "Clock enable failed\n"); + + clk_rate_exclusive_get(rz_mtu3_pwm->clk); + + rz_mtu3_pwm->rate = clk_get_rate(rz_mtu3_pwm->clk); + /* + * Refuse clk rates > 1 GHz to prevent overflow later for computing + * period and duty cycle. + */ + if (rz_mtu3_pwm->rate > NSEC_PER_SEC) { + ret = -EINVAL; + clk_rate_exclusive_put(rz_mtu3_pwm->clk); + goto disable_clock; + } + + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + rz_mtu3_pwm->chip.dev = &pdev->dev; + ret = devm_add_action_or_reset(&pdev->dev, rz_mtu3_pwm_pm_disable, + rz_mtu3_pwm); + if (ret < 0) + return ret; + + rz_mtu3_pwm->chip.ops = &rz_mtu3_pwm_ops; + rz_mtu3_pwm->chip.npwm = RZ_MTU3_MAX_PWM_CHANNELS; + ret = devm_pwmchip_add(&pdev->dev, &rz_mtu3_pwm->chip); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n"); + + pm_runtime_idle(&pdev->dev); + + return 0; + +disable_clock: + clk_disable_unprepare(rz_mtu3_pwm->clk); + return ret; +} + +static struct platform_driver rz_mtu3_pwm_driver = { + .driver = { + .name = "pwm-rz-mtu3", + .pm = pm_ptr(&rz_mtu3_pwm_pm_ops), + }, + .probe = rz_mtu3_pwm_probe, +}; +module_platform_driver(rz_mtu3_pwm_driver); + +MODULE_AUTHOR("Biju Das "); +MODULE_ALIAS("platform:pwm-rz-mtu3"); +MODULE_DESCRIPTION("Renesas RZ/G2L MTU3a PWM Timer Driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Jul 18 14:11:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13317349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF45CEB64DD for ; Tue, 18 Jul 2023 14:11:49 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.8584.1689689497866713402 for ; Tue, 18 Jul 2023 07:11:42 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.01,214,1684767600"; d="scan'208";a="169768620" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 18 Jul 2023 23:11:41 +0900 Received: from localhost.localdomain (unknown [10.226.92.137]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 2EC25400F736; Tue, 18 Jul 2023 23:11:39 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Fabrizio Castro Subject: [PATCH 6.1.y-cip 4/6] arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3 Date: Tue, 18 Jul 2023 15:11:27 +0100 Message-Id: <20230718141129.119809-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230718141129.119809-1-biju.das.jz@bp.renesas.com> References: <20230718141129.119809-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jul 2023 14:11:49 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/12395 commit fb9341ebc7df140813d4fbc4a29fddba55a90728 upstream. Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC EVK. The MTU3a PWM pins are muxed with spi1 pins and counter external input phase clock pins are muxed with scif2 pins. Disable these IPs when PMOD_MTU3 macro is enabled. Apart from this, the counter Z phase clock signal is muxed with the SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal is enabled. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230706153047.368993-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- .../boot/dts/renesas/r9a07g044l2-smarc.dts | 21 +++++++++++++++++ .../boot/dts/renesas/r9a07g054l2-smarc.dts | 20 ++++++++++++++++ .../dts/renesas/rzg2l-smarc-pinfunction.dtsi | 20 ++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 23 ++++++++++++++++--- 4 files changed, 81 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts index bc2af6c92ccd..568d49cfe44a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts @@ -6,6 +6,27 @@ */ /dts-v1/; + +/* Enable SCIF2 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + +/* + * To enable MTU3a PWM on PMOD0, + * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and + * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && PMOD1_SER0) +#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive " +#endif + +#define MTU3_COUNTER_Z_PHASE_SIGNAL 0 + +#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL) +#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0" +#endif + #include "r9a07g044l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index 3d01a4cf0fbe..b3e6016880dd 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -6,6 +6,26 @@ */ /dts-v1/; + +/* Enable SCIF2 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + +/* + * To enable MTU3a PWM on PMOD0, + * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and + * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && PMOD1_SER0) +#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive " +#endif + +#define MTU3_COUNTER_Z_PHASE_SIGNAL 0 +#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL) +#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0" +#endif + #include "r9a07g054l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi index 9085d8c76ce1..18c526c7a4cf 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi @@ -53,6 +53,26 @@ i2c3_pins: i2c3 { ; /* SCL */ }; + mtu3_pins: mtu3 { + mtu3-ext-clk-input-pin { + pinmux = , /* MTCLKA */ + ; /* MTCLKB */ + }; + + mtu3-pwm { + pinmux = , /* MTIOC3A */ + , /* MTIOC3B */ + , /* MTIOC3C */ + ; /* MTIOC3D */ + }; + +#if MTU3_COUNTER_Z_PHASE_SIGNAL + mtu3-zphase-clk { + pinmux = ; /* MTIOC1A */ + }; +#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */ + }; + scif0_pins: scif0 { pinmux = , /* TxD */ ; /* RxD */ diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index e180a955b6ac..018c34f841bf 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -8,9 +8,6 @@ #include #include -/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ -#define PMOD1_SER0 1 - / { aliases { serial1 = &scif2; @@ -36,6 +33,26 @@ wm8978: codec@1a { }; }; +#if PMOD_MTU3 +&mtu3 { + pinctrl-0 = <&mtu3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +#if MTU3_COUNTER_Z_PHASE_SIGNAL +/* SDHI cd pin is muxed with counter Z phase signal */ +&sdhi1 { + status = "disabled"; +}; +#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */ + +&spi1 { + status = "disabled"; +}; +#endif /* PMOD_MTU3 */ + /* * To enable SCIF2 (SER0) on PMOD1 (CN7) * SW1 should be at position 2->3 so that SER0_CTS# line is activated From patchwork Tue Jul 18 14:11:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13317351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E292CEB64DC for ; Tue, 18 Jul 2023 14:11:49 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web11.8584.1689689497866713402 for ; Tue, 18 Jul 2023 07:11:44 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.171, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.01,214,1684767600"; d="scan'208";a="169768628" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 18 Jul 2023 23:11:44 +0900 Received: from localhost.localdomain (unknown [10.226.92.137]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 6B965400F736; Tue, 18 Jul 2023 23:11:42 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Fabrizio Castro Subject: [PATCH 6.1.y-cip 5/6] arm64: dts: renesas: rzg2lc-smarc: Add support for enabling MTU3 Date: Tue, 18 Jul 2023 15:11:28 +0100 Message-Id: <20230718141129.119809-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230718141129.119809-1-biju.das.jz@bp.renesas.com> References: <20230718141129.119809-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jul 2023 14:11:49 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/12396 commit 742ebf5d715a4d4b9b4800f5b9eb3a2fae9c9282 upstream. Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/G2LC SMARC EVK. The MTU3a PWM pins on PMOD0 are muxed with SPI1. Disable SPI1, when PMOD_MTU3 macro is enabled. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230707155849.86649-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 12 ++++++++++++ .../boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 9 +++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 14 +++++++++++++- 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index f67a6f125d9c..0b90367b6d1e 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -35,6 +35,18 @@ /* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ #define PMOD1_SER0 1 +/* + * To enable MTU3a PWM on PMOD0, + * - Set DIP-Switch SW1-4 to Off position. + * - Set SW_RSPI_CAN macro to 0. + * - Set PMOD_MTU3 macro to 1. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && SW_RSPI_CAN) +#error "Cannot set as both PMOD_MTU3 and SW_RSPI_CAN are mutually exclusive" +#endif + #include "r9a07g044c2.dtsi" #include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index a78a8def363e..92c64d58349f 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -50,6 +50,15 @@ i2c2_pins: i2c2 { ; /* SCL */ }; + mtu3_pins: mtu3 { + mtu3-pwm { + pinmux = , /* MTIOC3A */ + , /* MTIOC3B */ + , /* MTIOC3C */ + ; /* MTIOC3D */ + }; + }; + scif0_pins: scif0 { pinmux = , /* TxD */ ; /* RxD */ diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index b6bd27196d88..664318e3dfb6 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -11,7 +11,6 @@ #include "rzg2lc-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" - / { aliases { serial1 = &scif1; @@ -50,6 +49,19 @@ wm8978: codec@1a { }; }; +#if PMOD_MTU3 +&mtu3 { + pinctrl-0 = <&mtu3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&spi1 { + status = "disabled"; +}; +#endif + /* * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board * SW1 should be at position 2->3 so that SER0_CTS# line is activated From patchwork Tue Jul 18 14:11:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13317352 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E28F3EB64DA for ; Tue, 18 Jul 2023 14:11:49 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web10.8682.1689689506829253600 for ; Tue, 18 Jul 2023 07:11:47 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: bp.renesas.com, ip: 210.160.252.172, mailfrom: biju.das.jz@bp.renesas.com) X-IronPort-AV: E=Sophos;i="6.01,214,1684767600"; d="scan'208";a="173413983" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 18 Jul 2023 23:11:46 +0900 Received: from localhost.localdomain (unknown [10.226.92.137]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A228D400F736; Tue, 18 Jul 2023 23:11:44 +0900 (JST) From: Biju Das To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Fabrizio Castro Subject: [PATCH 6.1.y-cip 6/6] arm64: defconfig: Enable Renesas MTU3a PWM config Date: Tue, 18 Jul 2023 15:11:29 +0100 Message-Id: <20230718141129.119809-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230718141129.119809-1-biju.das.jz@bp.renesas.com> References: <20230718141129.119809-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jul 2023 14:11:49 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/12397 commit aaa08e28e0051e88c88cc14bfa0db968b977cc85 upstream. Enable PWM config for Renesas MTU3a PWM as it is populated on RZ/{G2L, LC, UL} and RZ/V2L SMARC EVKs. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230703132706.355237-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 3164657aa297..b8174d962370 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1211,6 +1211,7 @@ CONFIG_PWM_MEDIATEK=m CONFIG_PWM_RCAR=m CONFIG_PWM_RENESAS_TPU=m CONFIG_PWM_ROCKCHIP=y +CONFIG_PWM_RZ_MTU3=m CONFIG_PWM_SAMSUNG=y CONFIG_PWM_SL28CPLD=m CONFIG_PWM_SUN4I=m