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Signed-off-by: Michael Riesch Acked-by: Conor Dooley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 1e2e51401dc5..1dfafc339ddd 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -677,6 +677,8 @@ patternProperties: description: iWave Systems Technologies Pvt. Ltd. "^jadard,.*": description: Jadard Technology Inc. + "^jasonic,.*": + description: Jasonic Technology Ltd. "^jdi,.*": description: Japan Display Inc. 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Tue, 18 Jul 2023 15:31:55 +0000 From: Michael Riesch Date: Tue, 18 Jul 2023 17:31:51 +0200 Subject: [PATCH 2/4] dt-bindings: display: st7789v: add jasonic jt240mhqs-hwt-ek-e3 display Message-Id: <20230718-feature-lcd-panel-v1-2-e9a85d5374fd@wolfvision.net> References: <20230718-feature-lcd-panel-v1-0-e9a85d5374fd@wolfvision.net> In-Reply-To: <20230718-feature-lcd-panel-v1-0-e9a85d5374fd@wolfvision.net> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Sam Ravnborg , David Airlie , Daniel Vetter , Maxime Ripard , Miquel Raynal , Sebastian Reichel , Gerald Loacker X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689694312; l=811; i=michael.riesch@wolfvision.net; s=20230406; h=from:subject:message-id; bh=tGeIwdn9vAFkllDPaAoK5b1eixQq8cAEyAN7no9veUQ=; b=ijXA8RFzyear/UMIfx16H/zlDTuVW6gUUuWuuBDqLXH6o60QSB6+A9WRSdbpb3n2dT6/Bmbh9 3MkbTDM43RMA5xuxSqOwUzMSaj8lmVgsgVyRCXenbweEEgVymRze+Ib X-Developer-Key: i=michael.riesch@wolfvision.net; a=ed25519; pk=G03kuYHL670EcdsWaNfVA7KnHWmkSpj98XziQm/hjbk= X-ClientProxiedBy: VI1PR0102CA0027.eurprd01.prod.exchangelabs.com (2603:10a6:802::40) To DU0PR08MB9155.eurprd08.prod.outlook.com (2603:10a6:10:416::5) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR08MB9155:EE_|DU2PR08MB10201:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b3473e2-d78c-4739-b9b6-08db87a41e09 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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JT240MHQS-HWT-EK-E3 display. Signed-off-by: Michael Riesch Acked-by: Conor Dooley --- Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml b/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml index 905c064cd106..eb1a7256ac32 100644 --- a/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml +++ b/Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml @@ -18,6 +18,7 @@ properties: enum: - edt,et028013dma - inanbo,t28cp45tn89-v17 + - jasonic,jt240mhqs-hwt-ek-e3 - sitronix,st7789v reg: true From patchwork Tue Jul 18 15:31:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Riesch X-Patchwork-Id: 13317416 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1F3C9EB64DC for ; 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Here, the area to be displayed can be restricted in one direction (by default, in vertical direction). This is useful for panels that are partially occluded by design. Add support for the partial mode. Signed-off-by: Michael Riesch --- drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 38 ++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7789v.c b/drivers/gpu/drm/panel/panel-sitronix-st7789v.c index d16d17f21d92..729d8d7dbf7f 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7789v.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7789v.c @@ -118,6 +118,9 @@ struct st7789_panel_info { u32 bus_format; u32 bus_flags; bool invert_mode; + bool partial_mode; + u16 partial_start; + u16 partial_end; }; struct st7789v { @@ -330,9 +333,14 @@ static int st7789v_get_modes(struct drm_panel *panel, static int st7789v_prepare(struct drm_panel *panel) { struct st7789v *ctx = panel_to_st7789v(panel); - u8 pixel_fmt, polarity; + u8 mode, pixel_fmt, polarity; int ret; + if (!ctx->info->partial_mode) + mode = ST7789V_RGBCTRL_WO; + else + mode = 0; + switch (ctx->info->bus_format) { case MEDIA_BUS_FMT_RGB666_1X18: pixel_fmt = MIPI_DCS_PIXEL_FMT_18BIT; @@ -472,6 +480,32 @@ static int st7789v_prepare(struct drm_panel *panel) MIPI_DCS_EXIT_INVERT_MODE)); } + if (ctx->info->partial_mode) { + u8 area_data[4] = { + (ctx->info->partial_start >> 8) & 0xff, + (ctx->info->partial_start >> 0) & 0xff, + ((ctx->info->partial_end - 1) >> 8) & 0xff, + ((ctx->info->partial_end - 1) >> 0) & 0xff, + }; + + ST7789V_TEST(ret, st7789v_write_command( + ctx, MIPI_DCS_ENTER_PARTIAL_MODE)); + + ST7789V_TEST(ret, st7789v_write_command( + ctx, MIPI_DCS_SET_PAGE_ADDRESS)); + ST7789V_TEST(ret, st7789v_write_data(ctx, area_data[0])); + ST7789V_TEST(ret, st7789v_write_data(ctx, area_data[1])); + ST7789V_TEST(ret, st7789v_write_data(ctx, area_data[2])); + ST7789V_TEST(ret, st7789v_write_data(ctx, area_data[3])); + + ST7789V_TEST(ret, st7789v_write_command( + ctx, MIPI_DCS_SET_PARTIAL_ROWS)); + ST7789V_TEST(ret, st7789v_write_data(ctx, area_data[0])); + ST7789V_TEST(ret, st7789v_write_data(ctx, area_data[1])); + ST7789V_TEST(ret, st7789v_write_data(ctx, area_data[2])); + ST7789V_TEST(ret, st7789v_write_data(ctx, area_data[3])); + } + ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_RAMCTRL_CMD)); ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_RAMCTRL_DM_RGB | ST7789V_RAMCTRL_RM_RGB)); @@ -479,7 +513,7 @@ static int st7789v_prepare(struct drm_panel *panel) ST7789V_RAMCTRL_MAGIC)); ST7789V_TEST(ret, st7789v_write_command(ctx, ST7789V_RGBCTRL_CMD)); - ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_RGBCTRL_WO | + ST7789V_TEST(ret, st7789v_write_data(ctx, mode | ST7789V_RGBCTRL_RCM(2) | polarity)); ST7789V_TEST(ret, st7789v_write_data(ctx, ST7789V_RGBCTRL_VBP(8))); From patchwork Tue Jul 18 15:31:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Riesch X-Patchwork-Id: 13317417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3E1BEB64DA for ; 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While the controller features a resolution of 320x240, only an area of 280x240 is visible by design. Signed-off-by: Michael Riesch --- drivers/gpu/drm/panel/panel-sitronix-st7789v.c | 29 ++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7789v.c b/drivers/gpu/drm/panel/panel-sitronix-st7789v.c index 729d8d7dbf7f..4c6aed993ba1 100644 --- a/drivers/gpu/drm/panel/panel-sitronix-st7789v.c +++ b/drivers/gpu/drm/panel/panel-sitronix-st7789v.c @@ -278,6 +278,21 @@ static const struct drm_display_mode et028013dma_mode = { .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, }; +static const struct drm_display_mode jt240mhqs_hwt_ek_e3_mode = { + .clock = 6000, + .hdisplay = 240, + .hsync_start = 240 + 28, + .hsync_end = 240 + 28 + 10, + .htotal = 240 + 28 + 10 + 10, + .vdisplay = 280, + .vsync_start = 280 + 8, + .vsync_end = 280 + 8 + 4, + .vtotal = 280 + 8 + 4 + 4, + .width_mm = 43, + .height_mm = 37, + .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, +}; + static const struct st7789_panel_info default_panel = { .mode = &default_mode, .invert_mode = true, @@ -302,6 +317,17 @@ static const struct st7789_panel_info et028013dma_panel = { DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, }; +static const struct st7789_panel_info jt240mhqs_hwt_ek_e3_panel = { + .mode = &jt240mhqs_hwt_ek_e3_mode, + .invert_mode = true, + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | + DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, + .partial_mode = true, + .partial_start = 38, + .partial_end = 318, +}; + static int st7789v_get_modes(struct drm_panel *panel, struct drm_connector *connector) { @@ -612,6 +638,7 @@ static const struct spi_device_id st7789v_spi_id[] = { { "st7789v", (unsigned long) &default_panel }, { "t28cp45tn89-v17", (unsigned long) &t28cp45tn89_panel }, { "et028013dma", (unsigned long) &et028013dma_panel }, + { "jt240mhqs-hwt-ek-e3", (unsigned long) &jt240mhqs_hwt_ek_e3_panel }, { } }; MODULE_DEVICE_TABLE(spi, st7789v_spi_id); @@ -620,6 +647,8 @@ static const struct of_device_id st7789v_of_match[] = { { .compatible = "sitronix,st7789v", .data = &default_panel }, { .compatible = "inanbo,t28cp45tn89-v17", .data = &t28cp45tn89_panel }, { .compatible = "edt,et028013dma", .data = &et028013dma_panel }, + { .compatible = "jasonic,jt240mhqs-hwt-ek-e3", + .data = &jt240mhqs_hwt_ek_e3_panel }, { } }; MODULE_DEVICE_TABLE(of, st7789v_of_match);