From patchwork Tue Jul 18 15:32:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 13317420 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60945C00528 for ; Tue, 18 Jul 2023 15:32:20 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.10790.1689694336488386504 for ; Tue, 18 Jul 2023 08:32:19 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: renesas.com, ip: 210.160.252.172, mailfrom: fabrizio.castro.jz@renesas.com) X-IronPort-AV: E=Sophos;i="6.01,214,1684767600"; d="scan'208";a="173423809" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 19 Jul 2023 00:32:18 +0900 Received: from mulinux.home (unknown [10.226.93.62]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 61356400563A; Wed, 19 Jul 2023 00:32:16 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar , Chris Paterson , Fabrizio Castro Subject: [PATCH 6.1.y-cip 1/6] pinctrl: renesas: rzv2m: Handle non-unique subnode names Date: Tue, 18 Jul 2023 16:32:07 +0100 Message-Id: <20230718153212.327448-2-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230718153212.327448-1-fabrizio.castro.jz@renesas.com> References: <20230718153212.327448-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jul 2023 15:32:20 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/12404 From: Geert Uytterhoeven Commit f46a0b47cc0829acd050213194c5a77351e619b2 upstream. The eMMC and SDHI pin control configuration nodes in DT have subnodes with the same names ("data" and "ctrl"). As the RZ/V2M pin control driver considers only the names of the subnodes, this leads to conflicts: pinctrl-rzv2m b6250000.pinctrl: pin P8_2 already requested by 85000000.mmc; cannot claim for 85020000.mmc pinctrl-rzv2m b6250000.pinctrl: pin-130 (85020000.mmc) status -22 renesas_sdhi_internal_dmac 85020000.mmc: Error applying setting, reverse things back Fix this by constructing unique names from the node names of both the pin control configuration node and its child node, where appropriate. Reported by: Fabrizio Castro Fixes: 92a9b825257614af ("pinctrl: renesas: Add RZ/V2M pin and gpio controller driver") Signed-off-by: Geert Uytterhoeven Tested-by: Fabrizio Castro Link: https://lore.kernel.org/r/607bd6ab4905b0b1b119a06ef953fa1184505777.1688396717.git.geert+renesas@glider.be Signed-off-by: Fabrizio Castro --- I'll try and backport this patch also to v5.10.y-cip. drivers/pinctrl/renesas/pinctrl-rzv2m.c | 28 ++++++++++++++++++------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzv2m.c b/drivers/pinctrl/renesas/pinctrl-rzv2m.c index e8c18198bebd..35f382b055e8 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzv2m.c +++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c @@ -207,6 +207,7 @@ static int rzv2m_map_add_config(struct pinctrl_map *map, static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct device_node *np, + struct device_node *parent, struct pinctrl_map **map, unsigned int *num_maps, unsigned int *index) @@ -224,6 +225,7 @@ static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev, struct property *prop; int ret, gsel, fsel; const char **pin_fn; + const char *name; const char *pin; pinmux = of_find_property(np, "pinmux", NULL); @@ -307,8 +309,19 @@ static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev, psel_val[i] = MUX_FUNC(value); } + if (parent) { + name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", + parent, np); + if (!name) { + ret = -ENOMEM; + goto done; + } + } else { + name = np->name; + } + /* Register a single pin group listing all the pins we read from DT */ - gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL); + gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); if (gsel < 0) { ret = gsel; goto done; @@ -318,17 +331,16 @@ static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev, * Register a single group function where the 'data' is an array PSEL * register values read from DT. */ - pin_fn[0] = np->name; - fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1, - psel_val); + pin_fn[0] = name; + fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); if (fsel < 0) { ret = fsel; goto remove_group; } maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; - maps[idx].data.mux.group = np->name; - maps[idx].data.mux.function = np->name; + maps[idx].data.mux.group = name; + maps[idx].data.mux.function = name; idx++; dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); @@ -375,7 +387,7 @@ static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev, index = 0; for_each_child_of_node(np, child) { - ret = rzv2m_dt_subnode_to_map(pctldev, child, map, + ret = rzv2m_dt_subnode_to_map(pctldev, child, np, map, num_maps, &index); if (ret < 0) { of_node_put(child); @@ -384,7 +396,7 @@ static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev, } if (*num_maps == 0) { - ret = rzv2m_dt_subnode_to_map(pctldev, np, map, + ret = rzv2m_dt_subnode_to_map(pctldev, np, NULL, map, num_maps, &index); if (ret < 0) goto done; From patchwork Tue Jul 18 15:32:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 13317422 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 419D6EB64DA for ; Tue, 18 Jul 2023 15:32:30 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.10790.1689694336488386504 for ; Tue, 18 Jul 2023 08:32:21 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: renesas.com, ip: 210.160.252.172, mailfrom: fabrizio.castro.jz@renesas.com) X-IronPort-AV: E=Sophos;i="6.01,214,1684767600"; d="scan'208";a="173423821" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 19 Jul 2023 00:32:21 +0900 Received: from mulinux.home (unknown [10.226.93.62]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 37455400563A; Wed, 19 Jul 2023 00:32:18 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar , Chris Paterson , Fabrizio Castro Subject: [PATCH 6.1.y-cip 2/6] dt-bindings: mmc: renesas,sdhi: Document RZ/V2M support Date: Tue, 18 Jul 2023 16:32:08 +0100 Message-Id: <20230718153212.327448-3-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230718153212.327448-1-fabrizio.castro.jz@renesas.com> References: <20230718153212.327448-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jul 2023 15:32:30 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/12405 Commit c9dc89944b66abf9aa0ad57aa45e4edf030e2441 upstream. Document support for the SD Card/MMC interface on the Renesas RZ/V2M (a.k.a. r9a09g011) SoC. Signed-off-by: Fabrizio Castro Acked-by: Rob Herring Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/20221213230129.549968-3-fabrizio.castro.jz@renesas.com Signed-off-by: Ulf Hansson Signed-off-by: Fabrizio Castro --- Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 0424b06cb655..1b9cf33e2cf1 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -59,6 +59,7 @@ properties: - renesas,sdhi-r9a07g043 # RZ/G2UL - renesas,sdhi-r9a07g044 # RZ/G2{L,LC} - renesas,sdhi-r9a07g054 # RZ/V2L + - renesas,sdhi-r9a09g011 # RZ/V2M - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2 - items: - enum: From patchwork Tue Jul 18 15:32:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 13317421 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DD77C001DC for ; Tue, 18 Jul 2023 15:32:30 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web11.10790.1689694336488386504 for ; Tue, 18 Jul 2023 08:32:24 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: renesas.com, ip: 210.160.252.172, mailfrom: fabrizio.castro.jz@renesas.com) X-IronPort-AV: E=Sophos;i="6.01,214,1684767600"; d="scan'208";a="173423833" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 19 Jul 2023 00:32:24 +0900 Received: from mulinux.home (unknown [10.226.93.62]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 08202400C9F4; Wed, 19 Jul 2023 00:32:21 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar , Chris Paterson , Fabrizio Castro Subject: [PATCH 6.1.y-cip 3/6] clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries Date: Tue, 18 Jul 2023 16:32:09 +0100 Message-Id: <20230718153212.327448-4-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230718153212.327448-1-fabrizio.castro.jz@renesas.com> References: <20230718153212.327448-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jul 2023 15:32:30 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/12406 From: Phil Edworthy Commit d969103ac89de797fda351aa984f69602b149a72 upstream. Add SDHI/eMMC clock/reset entries to CPG driver. Signed-off-by: Phil Edworthy Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20221213230129.549968-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Fabrizio Castro --- drivers/clk/renesas/r9a09g011-cpg.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index 8ee4b5e27bdd..a3506abb990c 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -30,6 +30,7 @@ #define SEL_B SEL_PLL_PACK(0x214, 0, 1) #define SEL_D SEL_PLL_PACK(0x214, 1, 1) #define SEL_E SEL_PLL_PACK(0x214, 2, 1) +#define SEL_SDI SEL_PLL_PACK(0x300, 0, 1) #define SEL_W0 SEL_PLL_PACK(0x32C, 0, 1) enum clk_ids { @@ -59,6 +60,7 @@ enum clk_ids { CLK_SEL_B_D2, CLK_SEL_D, CLK_SEL_E, + CLK_SEL_SDI, CLK_SEL_W0, /* Module Clocks */ @@ -92,6 +94,7 @@ static const struct clk_div_table dtable_divd[] = { {0, 0}, }; + static const struct clk_div_table dtable_divw[] = { {0, 6}, {1, 7}, @@ -108,6 +111,7 @@ static const char * const sel_b[] = { ".main", ".divb" }; static const char * const sel_d[] = { ".main", ".divd" }; static const char * const sel_e[] = { ".main", ".dive" }; static const char * const sel_w[] = { ".main", ".divw" }; +static const char * const sel_sdi[] = { ".main", ".pll2_200" }; static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { /* External Clock Inputs */ @@ -134,6 +138,7 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { DEF_MUX_RO(".selb", CLK_SEL_B, SEL_B, sel_b), DEF_MUX_RO(".seld", CLK_SEL_D, SEL_D, sel_d), DEF_MUX_RO(".sele", CLK_SEL_E, SEL_E, sel_e), + DEF_MUX(".selsdi", CLK_SEL_SDI, SEL_SDI, sel_sdi), DEF_MUX(".selw0", CLK_SEL_W0, SEL_W0, sel_w), DEF_FIXED(".selb_d2", CLK_SEL_B_D2, CLK_SEL_B, 1, 2), @@ -142,6 +147,18 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2), DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5), + DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0), + DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1), + DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2), + DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3), + DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4), + DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5), + DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6), + DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7), + DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8), + DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9), + DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10), + DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11), DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8), DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9), @@ -178,6 +195,9 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { static const struct rzg2l_reset r9a09g011_resets[] = { DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2), + DEF_RST_MON(R9A09G011_SDI0_IXRST, 0x608, 0, 6), + DEF_RST_MON(R9A09G011_SDI1_IXRST, 0x608, 1, 7), + DEF_RST_MON(R9A09G011_EMM_IXRST, 0x608, 2, 8), DEF_RST(R9A09G011_USB_PRESET_N, 0x608, 7), DEF_RST(R9A09G011_USB_DRD_RESET, 0x608, 8), DEF_RST(R9A09G011_USB_ARESETN_P, 0x608, 9), From patchwork Tue Jul 18 15:32:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 13317423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D8DAEB64DD for ; Tue, 18 Jul 2023 15:32:30 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.10926.1689694348777557318 for ; Tue, 18 Jul 2023 08:32:29 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: renesas.com, ip: 210.160.252.171, mailfrom: fabrizio.castro.jz@renesas.com) X-IronPort-AV: E=Sophos;i="6.01,214,1684767600"; d="scan'208";a="169778328" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 19 Jul 2023 00:32:27 +0900 Received: from mulinux.home (unknown [10.226.93.62]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id CCA2B400563A; Wed, 19 Jul 2023 00:32:24 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar , Chris Paterson , Fabrizio Castro Subject: [PATCH 6.1.y-cip 4/6] mmc: renesas_sdhi: Add RZ/V2M compatible string Date: Tue, 18 Jul 2023 16:32:10 +0100 Message-Id: <20230718153212.327448-5-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230718153212.327448-1-fabrizio.castro.jz@renesas.com> References: <20230718153212.327448-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jul 2023 15:32:30 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/12407 Commit 08e03039e0000a7ec7ba13dc18bddc6afd32cb27 upstream. The SDHI/eMMC IPs found with the RZ/V2M (a.k.a. r9a09g011), are very similar to the ones found in R-Car Gen3, but they are not exactly the same, and as a result need an SoC specific compatible string for fine tuning driver support. Signed-off-by: Fabrizio Castro Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/20221213230129.549968-4-fabrizio.castro.jz@renesas.com Signed-off-by: Ulf Hansson Signed-off-by: Fabrizio Castro --- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c index 7c81c2680701..3e254f76c1c6 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -211,6 +211,11 @@ static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = { .manual_tap_correction = true, }; +static const struct renesas_sdhi_quirks sdhi_quirks_r9a09g011 = { + .fixed_addr_mode = true, + .hs400_disabled = true, +}; + /* * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. * So, we want to treat them equally and only have a match for ES1.2 to enforce @@ -252,6 +257,11 @@ static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatible = { .quirks = &sdhi_quirks_r8a77990, }; +static const struct renesas_sdhi_of_data_with_quirks of_r9a09g011_compatible = { + .of_data = &of_data_rcar_gen3, + .quirks = &sdhi_quirks_r9a09g011, +}; + static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = { .of_data = &of_data_rcar_gen3, }; @@ -275,6 +285,7 @@ static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { { .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, }, { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, }, { .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, }, + { .compatible = "renesas,sdhi-r9a09g011", .data = &of_r9a09g011_compatible, }, { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, { .compatible = "renesas,rcar-gen4-sdhi", .data = &of_rcar_gen3_compatible, }, {}, From patchwork Tue Jul 18 15:32:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 13317425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45FEBEB64DC for ; Tue, 18 Jul 2023 15:32:40 +0000 (UTC) Received: from relmlie6.idc.renesas.com (relmlie6.idc.renesas.com [210.160.252.172]) by mx.groups.io with SMTP id smtpd.web10.10928.1689694350696635069 for ; Tue, 18 Jul 2023 08:32:30 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: renesas.com, ip: 210.160.252.172, mailfrom: fabrizio.castro.jz@renesas.com) X-IronPort-AV: E=Sophos;i="6.01,214,1684767600"; d="scan'208";a="173423852" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 19 Jul 2023 00:32:29 +0900 Received: from mulinux.home (unknown [10.226.93.62]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A755F400563A; Wed, 19 Jul 2023 00:32:27 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar , Chris Paterson , Fabrizio Castro Subject: [PATCH 6.1.y-cip 5/6] arm64: dts: renesas: r9a09g011: Add eMMC and SDHI support Date: Tue, 18 Jul 2023 16:32:11 +0100 Message-Id: <20230718153212.327448-6-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230718153212.327448-1-fabrizio.castro.jz@renesas.com> References: <20230718153212.327448-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jul 2023 15:32:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/12408 Commit 36aa3eee39b2bce5596d3a1178d3c381c1cf3b57 upstream. The RZ/V2M comes with 2 SDHI interfaces and 1 eMMC interface. Add the relevant nodes to the SoC specific device tree. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20221213230129.549968-5-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Fabrizio Castro --- arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index d3af097f5fae..46d67b200a66 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -69,6 +69,54 @@ gic: interrupt-controller@82010000 { clock-names = "clk"; }; + sdhi0: mmc@85000000 { + compatible = "renesas,sdhi-r9a09g011", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x85000000 0 0x2000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>, + <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>, + <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>, + <&cpg CPG_MOD R9A09G011_SDI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A09G011_SDI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi1: mmc@85010000 { + compatible = "renesas,sdhi-r9a09g011", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x85010000 0 0x2000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>, + <&cpg CPG_MOD R9A09G011_SDI1_CLK_HS>, + <&cpg CPG_MOD R9A09G011_SDI1_IMCLK2>, + <&cpg CPG_MOD R9A09G011_SDI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A09G011_SDI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + emmc: mmc@85020000 { + compatible = "renesas,sdhi-r9a09g011", + "renesas,rcar-gen3-sdhi"; + reg = <0x0 0x85020000 0 0x2000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A09G011_EMM_IMCLK>, + <&cpg CPG_MOD R9A09G011_EMM_CLK_HS>, + <&cpg CPG_MOD R9A09G011_EMM_IMCLK2>, + <&cpg CPG_MOD R9A09G011_EMM_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A09G011_EMM_IXRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + usb3drd: usb3drd@85070400 { compatible = "renesas,r9a09g011-usb3drd", "renesas,rzv2m-usb3drd"; From patchwork Tue Jul 18 15:32:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 13317424 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45F80EB64DA for ; Tue, 18 Jul 2023 15:32:40 +0000 (UTC) Received: from relmlie5.idc.renesas.com (relmlie5.idc.renesas.com [210.160.252.171]) by mx.groups.io with SMTP id smtpd.web10.10926.1689694348777557318 for ; Tue, 18 Jul 2023 08:32:33 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: renesas.com, ip: 210.160.252.171, mailfrom: fabrizio.castro.jz@renesas.com) X-IronPort-AV: E=Sophos;i="6.01,214,1684767600"; d="scan'208";a="169778349" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 19 Jul 2023 00:32:32 +0900 Received: from mulinux.home (unknown [10.226.93.62]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 7A834400C9F4; Wed, 19 Jul 2023 00:32:30 +0900 (JST) From: Fabrizio Castro To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu , Pavel Machek Cc: Biju Das , Lad Prabhakar , Chris Paterson , Fabrizio Castro Subject: [PATCH 6.1.y-cip 6/6] arm64: dts: renesas: rzv2mevk2: Add uSD card and eMMC support Date: Tue, 18 Jul 2023 16:32:12 +0100 Message-Id: <20230718153212.327448-7-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230718153212.327448-1-fabrizio.castro.jz@renesas.com> References: <20230718153212.327448-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Tue, 18 Jul 2023 15:32:40 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/12409 Commit b6c0be722b0c0a7204b6289464a04cd7b4fdfca0 upstream. The RZ/V2M EVK comes with a slot for a uSD card, and an eMMC. Add support for the both of them. Please note that the pinctrl driver for RZ/V2M doesn't support interrupts yet, therefore the card detect pin has been connected to the SDHI IP directly in this patch. We'll connect the card detect pin to its corresponding GPIO when we'll have driver support for interrupts in the RZ/V2M pinctrl driver. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230130191152.182826-1-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Fabrizio Castro --- .../boot/dts/renesas/r9a09g011-v2mevk2.dts | 123 ++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts index 8b7f6da693a7..39fe3f94991e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "r9a09g011.dtsi" +#include #include / { @@ -60,6 +61,36 @@ memory@180000000 { device_type = "memory"; reg = <0x1 0x80000000 0x0 0x80000000>; }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&pwc 0 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 0>, <1800000 1>; + }; }; &avb { @@ -75,6 +106,23 @@ phy0: ethernet-phy@0 { }; }; +&emmc { + pinctrl-0 = <&emmc_pins>; + pinctrl-1 = <&emmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_1v8>; + bus-width = <8>; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + fixed-emmc-driver-type = <1>; + max-frequency = <200000000>; + status = "okay"; +}; + &extal_clk { clock-frequency = <48000000>; }; @@ -118,6 +166,26 @@ &i2c2 { }; &pinctrl { + emmc_pins: emmc { + data { + pinmux = , /* MMDAT0 */ + , /* MMDAT1 */ + , /* MMDAT2 */ + , /* MMDAT3 */ + , /* MMDAT4 */ + , /* MMDAT5 */ + , /* MMDAT6 */ + ; /* MMDAT7 */ + power-source = <1800>; + }; + + ctrl { + pinmux = , /* MMCMD */ + ; /* MMCLK */ + power-source = <1800>; + }; + }; + i2c0_pins: i2c0 { pinmux = , /* SDA */ ; /* SCL */ @@ -128,6 +196,48 @@ i2c2_pins: i2c2 { ; /* SCL */ }; + sdhi0_pins: sd0 { + data { + pinmux = , /* SD0DAT0 */ + , /* SD0DAT1 */ + , /* SD0DAT2 */ + ; /* SD0DAT3 */ + power-source = <3300>; + }; + + ctrl { + pinmux = , /* SD0CMD */ + ; /* SD0CLK */ + power-source = <3300>; + }; + + cd { + pinmux = ; /* SD0CD */ + power-source = <3300>; + }; + }; + + sdhi0_pins_uhs: sd0-uhs { + data { + pinmux = , /* SD0DAT0 */ + , /* SD0DAT1 */ + , /* SD0DAT2 */ + ; /* SD0DAT3 */ + power-source = <1800>; + }; + + ctrl { + pinmux = , /* SD0CMD */ + ; /* SD0CLK */ + power-source = <1800>; + }; + + cd { + pinmux = ; /* SD0CD */ + power-source = <1800>; + }; + }; + uart0_pins: uart0 { pinmux = , /* UATX0 */ , /* UARX0 */ @@ -141,6 +251,19 @@ &pwc { status = "okay"; }; +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3v3>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + &uart0 { pinctrl-0 = <&uart0_pins>; pinctrl-names = "default";