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Tue, 18 Jul 2023 18:22:02 +0000 From: Frank Li To: mani@kernel.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: [PATCH v2 1/2] PCI: layerscape: Add support for Link down notification Date: Tue, 18 Jul 2023 14:21:41 -0400 Message-Id: <20230718182142.1864070-1-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 X-ClientProxiedBy: SJ0PR13CA0049.namprd13.prod.outlook.com (2603:10b6:a03:2c2::24) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB9572:EE_ X-MS-Office365-Filtering-Correlation-Id: 8246d3d0-da16-42c4-b9eb-08db87bbe194 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Acked-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- Change from v1 to v2 - move pci_epc_linkdown() after dev_dbg() drivers/pci/controller/dwc/pci-layerscape-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index de4c1758a6c3..e0969ff2ddf7 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -89,6 +89,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) dev_dbg(pci->dev, "Link up\n"); } else if (val & PEX_PF0_PME_MES_DR_LDD) { dev_dbg(pci->dev, "Link down\n"); + pci_epc_linkdown(pci->ep.epc); } else if (val & PEX_PF0_PME_MES_DR_HRD) { dev_dbg(pci->dev, "Hot reset\n"); } From patchwork Tue Jul 18 18:21:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13317600 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BC39EB64DC for ; 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b=NM+TGiiW61HKamuPo9u1j3RpUGfPExfwBozuvB5BrYnUBOKnhiw9liMIHRq9cAxhqqWg2ApKMIp+02xFh3IAL0E5YW35Fn0h4rTDG64Vgl8/LLkChKH/SbQKyDZaktug5XwkAdoAvC1ztWy5B6ANuvqNc2b2Y5ylpOJ/MsA/Sbc= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by PAXPR04MB9572.eurprd04.prod.outlook.com (2603:10a6:102:24f::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6588.32; Tue, 18 Jul 2023 18:22:05 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::6cc2:14b2:ca51:6c0]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::6cc2:14b2:ca51:6c0%4]) with mapi id 15.20.6588.031; Tue, 18 Jul 2023 18:22:05 +0000 From: Frank Li To: mani@kernel.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev, kw@linux.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org, roy.zang@nxp.com Subject: [PATCH v2 2/2] PCI: layerscape: Add the workaround for lost link capablities during reset Date: Tue, 18 Jul 2023 14:21:42 -0400 Message-Id: <20230718182142.1864070-2-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230718182142.1864070-1-Frank.Li@nxp.com> References: <20230718182142.1864070-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR13CA0049.namprd13.prod.outlook.com (2603:10b6:a03:2c2::24) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PAXPR04MB9572:EE_ X-MS-Office365-Filtering-Correlation-Id: 7e881eaa-83b7-4738-1f6e-08db87bbe3cc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: uO7tZzEFOHabv7LgIwkm56YQyoVZc5QVudwYkcTa1N3YpVlvQNFCruNRhsaUSgPDwo0nW+NO5JtVz1q7M6UNEfUbHD1FzSyrRxR3mb6pa2s9OdZ1JbFYvdbJj0hW3KrcAaPJ2knEuaSfe2WDDVLZBeN4UP/UOopdZUmdc2OPqo0BKb8HphhTH2Cn2fRsxk20ZR/OzIaqA1RJVIN1B/o4/de04wy/mq5tFbDy+taGt9lACUUTn6rXTEI4000Gb9z62jLQd9y+dK/RMIqW4wXzVgWgsUejOhc0D2CDnrtPq9BRSL/8DlpXOW3hY8k8g6dXz839nZDWmH3bycPVcxT6Aw6Y8c8dJVdhCnEq9RhrAOyAtc0bJue/3JWp5TSGqLPMKk6v+eOvilNQpmaz3XpYwBUu1eI8fFCoT25l/ma7x3b3pY+OfLhJjzauCYDDCYbIixw3Nfmt2U64zgeZ3+RNv4D0y/RrSj5uJxjQseO5YasKZXZRmzq8vPwbIgravOOmeJQFMCQ8Kbi6uA5EyBqYqZXQUlNGPX7uDzi2mD+tSUbz+5JT4GZSFpf5JrTJOUb48YV/EZyOUHmbIKbgxfagXCTDh09Rb5bJPYf1+KVxy2gPloQk0Qq6TkYUgsbAMNjW3twJCGwBqHNiHzzGMBywAPvQVXt1eOx4L8r3eTSckZQmasUYYRE4UYz4CZIiZE1REGLdJDG0oP7jFcHaNS3d/RYPPa897MjrKUf6Pv9ELxbBSIQepkt0bW0E3UuAlsbbkOJBH5uokVHWOdSJWZCcjzaKJwAhnpU7sSN4vAENgCIjvQeuf768oJGN8KcpXZ0cU6foTK1dH7moP546igFe3Ch750P/2S8MLiZei7UYQooy4kmsvGRnjtuZ+o3Sq4O5dW1UcqoSmLU0LxsTpe6MAETqDMwkTemzc1F3vyrDt7irGTXV15/YUMNr239ZGtif35EiNDBRtF+lYn1bj4V0AEJBQptO/BOp4770RUBAgF43bbVBWUm+tPmsi0mkZqFnZYsUiaVS03tY+7pJVVag6LaHTQ3hjNf6XwAahdys9JuvpuWVs8H8JKHaKle32bESU7ef5Yyf8OX4xhj56BqNJOj1S/B1TsMBTooR6QAZ6CBIs7yhTrsJeRj+eYinwA4zdKvfIqQuOSlkLQfBGihnFMe0ycdRbOYvngHz+RB1adAGaU5aTDth91nHUwHPiaObaaxw6tESci0Vhba304mW/s/2n6vbqGisVCN02bbR48nJganw+mCBEXZ+f+LoVKZaMAO2wQ1s9aDvOOZQZmOyfak2lPeKwcObEXDgBlJrOhEIwqSySzCLUrJrXXwyBzPemAL5/LZ6zw6WvW0mWBg1yaAwA/jSZrLXj+rLKlfTijhCJqOgNUBwumVvtfZ7FZyeStD5Trf8+LappJbYguK4rsnXL3SXA8qjosBLFlf/f7cyGAxDV7j5dj7WtgNY3QndmkRTV0dXKUkTuDLUyR3s1/iWgAYNlDehR2uuyX49T03WBKDCVGecgsGT0E9cYIc4Ax3WgPilVFUwR4MjqrYdYX6aXNfX2RqEvESc9F+ZLLm/xEsy6hU/CgncME+qlCpc X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7e881eaa-83b7-4738-1f6e-08db87bbe3cc X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jul 2023 18:22:05.4761 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9dGNXB9PAG+qpq4dA//KxAaULkF8qhbVJQCNWACN8MnPviDTvCKtK+2eV+pOhB5DS9jRhJHOg3Sc/LAVmz3iQA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB9572 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Xiaowei Bao A workaround for the issue where the PCI Express Endpoint (EP) controller loses the values of the Maximum Link Width and Supported Link Speed from the Link Capabilities Register, which initially configured by the Reset Configuration Word (RCW) during a link-down or hot reset event. Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support") Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang Signed-off-by: Frank Li Acked-by: Manivannan Sadhasivam --- change from v1 to v2: - add comments at restore register - add fixes tag .../pci/controller/dwc/pci-layerscape-ep.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c index e0969ff2ddf7..b1faf41a2fae 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -45,6 +45,7 @@ struct ls_pcie_ep { struct pci_epc_features *ls_epc; const struct ls_pcie_ep_drvdata *drvdata; int irq; + u32 lnkcap; bool big_endian; }; @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) struct ls_pcie_ep *pcie = dev_id; struct dw_pcie *pci = pcie->pci; u32 val, cfg; + u8 offset; val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); @@ -81,6 +83,19 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) return IRQ_NONE; if (val & PEX_PF0_PME_MES_DR_LUD) { + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + + /* + * The values of the Maximum Link Width and Supported Link + * Speed from the Link Capabilities Register will be lost + * during link down or hot reset. Restore initial value + * that configured by the Reset Configuration Word (RCW). + */ + dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); + dw_pcie_dbi_ro_wr_dis(pci); + cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG); cfg |= PEX_PF0_CFG_READY; ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); @@ -216,6 +231,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) struct ls_pcie_ep *pcie; struct pci_epc_features *ls_epc; struct resource *dbi_base; + u8 offset; int ret; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); @@ -252,6 +268,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie); + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + ret = dw_pcie_ep_init(&pci->ep); if (ret) return ret;