From patchwork Wed Jul 19 09:22:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 13318637 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B12D1101F9 for ; Wed, 19 Jul 2023 09:11:21 +0000 (UTC) Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C2EE19B2 for ; Wed, 19 Jul 2023 02:11:18 -0700 (PDT) X-QQ-mid: bizesmtp74t1689757774tex72mil Received: from wxdbg.localdomain.com ( [122.235.243.13]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 19 Jul 2023 17:09:25 +0800 (CST) X-QQ-SSF: 01400000000000K0Z000000A0000000 X-QQ-FEAT: dDyohfujUnn7RWEIvF/XOujWJsRn6j+OVbFkS4mDaUbv/TWsQCFisS/8vi+PP qG5F71ZEomIyMHj1JsoxyKkVPrBW6ALjWV81TxH8PE96SIV/30Y0oHNM0BWduRaBWFBk0IU 3yBUFcgOPknPBqso3ELvWWNx89Wev042DKvADTtvASw7EeRngx1pSCaUFP+2ylVIHyi4JDO c2Nb8S0QwrcMzROvQ8m7r2HtZe7XXPH4QwrirklSi0ixoyQESe/t5pXEC0GmZINKU3webIu NUZnIqXpYIByClhl3PLFp23qoym/xBUDHtMfG61D2+Uwalzte2vl4/3pOibU1/ypIkBUdlH ZbdI/EoKakujyHnoDFC0wi6M97ePWSKJhk+UXby2xKD6uxqEh8= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 4837342564142934633 From: Jiawen Wu To: linux@armlinux.org.uk, kabel@kernel.org, andrew@lunn.ch, hkallweit1@gmail.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, netdev@vger.kernel.org Cc: Jiawen Wu Subject: [PATCH net v2] net: phy: marvell10g: fix 88x3310 power up Date: Wed, 19 Jul 2023 17:22:33 +0800 Message-Id: <20230719092233.137844-1-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Clear MV_V2_PORT_CTRL_PWRDOWN bit to set power up for 88x3310 PHY, it sometimes does not take effect immediately. And a read of this register causes the bit not to clear. This will cause mv3310_reset() to time out, which will fail the config initialization. So add a delay before the next access. Fixes: c9cc1c815d36 ("net: phy: marvell10g: place in powersave mode at probe") Signed-off-by: Jiawen Wu Reviewed-by: Russell King (Oracle) --- v1 -> v2: - change poll-bit-clear to time delay --- drivers/net/phy/marvell10g.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c index 55d9d7acc32e..d4bb90d76881 100644 --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c @@ -328,6 +328,13 @@ static int mv3310_power_up(struct phy_device *phydev) ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, MV_V2_PORT_CTRL_PWRDOWN); + /* Sometimes, the power down bit doesn't clear immediately, and + * a read of this register causes the bit not to clear. Delay + * 100us to allow the PHY to come out of power down mode before + * the next access. + */ + udelay(100); + if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || priv->firmware_ver < 0x00030000) return ret;