From patchwork Thu Jul 20 08:26:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shuijing Li X-Patchwork-Id: 13320068 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65EF7EB64DC for ; Thu, 20 Jul 2023 08:27:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=E+EQrFItPnWqXw+UGJS4AeooNsHJARYkbvVK2BfredU=; b=pZw8h6Es5F67rp cfjrr005Upd3h5hl0A1V3/Z3NWbY46QNzhBQIgLgrPBMPgIzI/2lZGVcRHEEnm/5PMtta+JWk5+mI SMSOFA8f2D9GqnMHGQ1mUzwxjRq3QYQGz7j6SZ4A+eflNIALbr58BdXwH4xoQJ2G+/ta0aXKVcVn2 4HfPIoyiz10Jr7/ttgbpxjLx0M8P9lFrARC2V4h6MEa1eajwbjG6T9iJ//IOwMv71UM4JsiOSeIx1 wi/MxbMyYE5VcS/OfrXHsPWkiYN/kplbWV2X+tttBx+vh8EjqzWFwFUPKXj2WJU/nrOiC/Yfcb1ec ENjUJIPf5M8q9biR6Ctg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qMOzn-00AIsz-13; Thu, 20 Jul 2023 08:26:47 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qMOzf-00AIqs-29; Thu, 20 Jul 2023 08:26:41 +0000 X-UUID: 226f7d4e26d711ee83ed1395ce914268-20230720 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Qm5KdnmI2NQxAsRiyAJeJgT+IiS3U8R2/O6sl1QAf1E=; b=aUSwjlLLoYd3oUL+Cu0MSVu8KhimAlGTkgUb9lt3+85K8gxjDDXhyij1MSZ/W7wYRC5+rXwAPsnTbJklDo7b+Ye+KHZDVwNk2PYYOWYrCoX1ZGiI68n1tanrbErF90XJBMiNrMX3RtLzLVKgWb9Iz1ND4x4snGsDkOLgNJWLG9o=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.28,REQID:29cc02a9-bd0f-4808-a46d-93b8cc6f2b3b,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:176cd25,CLOUDID:db19e18e-7caa-48c2-8dbb-206f0389473c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 226f7d4e26d711ee83ed1395ce914268-20230720 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1837283769; Thu, 20 Jul 2023 01:26:33 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 20 Jul 2023 16:25:56 +0800 Received: from mszsdhlt06.gcn.mediatek.inc (10.16.6.206) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 20 Jul 2023 16:25:56 +0800 From: Shuijing Li To: , , , , , , , , , CC: , , , , , , Shuijing Li , Krzysztof Kozlowski Subject: [PATCH v3,1/3] dt-bindings: display: mediatek: dp: Add compatible for MediaTek MT8188 Date: Thu, 20 Jul 2023 16:26:02 +0800 Message-ID: <20230720082604.18618-2-shuijing.li@mediatek.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230720082604.18618-1-shuijing.li@mediatek.com> References: <20230720082604.18618-1-shuijing.li@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230720_012639_709487_7E6B757B X-CRM114-Status: UNSURE ( 9.06 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add dt-binding documentation of dp-tx for MediaTek MT8188 SoC. Signed-off-by: Shuijing Li Signed-off-by: Jitao Shi Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- Changes in v2: add a mediatek,mt8188-edp-tx compatible per suggestion from the previous thread: https://lore.kernel.org/lkml/c4a4a900-c80d-b110-f10e-7fa2dae8b7b5@collabora.com/ --- .../devicetree/bindings/display/mediatek/mediatek,dp.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml index ff781f2174a0..2aef1eb32e11 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml @@ -21,6 +21,8 @@ description: | properties: compatible: enum: + - mediatek,mt8188-dp-tx + - mediatek,mt8188-edp-tx - mediatek,mt8195-dp-tx - mediatek,mt8195-edp-tx From patchwork Thu Jul 20 08:26:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shuijing Li X-Patchwork-Id: 13320067 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D82EEB64DA for ; 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Thu, 20 Jul 2023 01:26:30 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 20 Jul 2023 16:25:57 +0800 Received: from mszsdhlt06.gcn.mediatek.inc (10.16.6.206) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 20 Jul 2023 16:25:56 +0800 From: Shuijing Li To: , , , , , , , , , CC: , , , , , , Shuijing Li Subject: [PATCH v3,2/3] drm/mediatek: dp: Add the audio packet flag to mtk_dp_data struct Date: Thu, 20 Jul 2023 16:26:03 +0800 Message-ID: <20230720082604.18618-3-shuijing.li@mediatek.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230720082604.18618-1-shuijing.li@mediatek.com> References: <20230720082604.18618-1-shuijing.li@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230720_012636_435920_7677E3E2 X-CRM114-Status: GOOD ( 16.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The audio packet arrangement function is to only arrange audio. packets into the Hblanking area. In order to align with the HW default setting of mt8195, this function needs to be turned off. Signed-off-by: Shuijing Li Signed-off-by: Jitao Shi Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- Changes in v3: Separate these two things into two different patches. per suggestion from the previous thread: https://lore.kernel.org/lkml/e2ad22bcba31797f38a12a488d4246a01bf0cb2e.camel@mediatek.com/ Changes in v2: - change the variables' name to be more descriptive - add a comment that describes the function of mtk_dp_audio_sample_arrange - reduce indentation by doing the inverse check - add a definition of some bits - add support for mediatek, mt8188-edp-tx per suggestion from the previous thread: https://lore.kernel.org/lkml/ac0fcec9-a2fe-06cc-c727-189ef7babe9c@collabora.com/ --- drivers/gpu/drm/mediatek/mtk_dp.c | 40 +++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dp_reg.h | 5 ++++ 2 files changed, 45 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index 64eee77452c0..d8cda83d6fef 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -139,6 +139,7 @@ struct mtk_dp_data { unsigned int smc_cmd; const struct mtk_dp_efuse_fmt *efuse_fmt; bool audio_supported; + bool audio_pkt_in_hblank_area; }; static const struct mtk_dp_efuse_fmt mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = { @@ -1362,6 +1363,18 @@ static void mtk_dp_sdp_set_down_cnt_init_in_hblank(struct mtk_dp *mtk_dp) SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK); } +static void mtk_dp_audio_sample_arrange(struct mtk_dp *mtk_dp) +{ + /* arrange audio packets into the Hblanking and Vblanking area */ + if (!mtk_dp->data->audio_pkt_in_hblank_area) + return; + + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0, + SDP_ASP_INSERT_IN_HBLANK_DP_ENC1_P0_MASK); + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0, + SDP_DOWN_ASP_CNT_INIT_DP_ENC1_P0_MASK); +} + static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp) { u32 sram_read_start = min_t(u32, MTK_DP_TBC_BUF_READ_START_ADDR, @@ -1371,6 +1384,7 @@ static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp) MTK_DP_PIX_PER_ADDR); mtk_dp_set_sram_read_start(mtk_dp, sram_read_start); mtk_dp_setup_encoder(mtk_dp); + mtk_dp_audio_sample_arrange(mtk_dp); mtk_dp_sdp_set_down_cnt_init_in_hblank(mtk_dp); mtk_dp_sdp_set_down_cnt_init(mtk_dp, sram_read_start); } @@ -2616,11 +2630,28 @@ static int mtk_dp_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops, mtk_dp_suspend, mtk_dp_resume); +static const struct mtk_dp_data mt8188_edp_data = { + .bridge_type = DRM_MODE_CONNECTOR_eDP, + .smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE, + .efuse_fmt = mt8195_edp_efuse_fmt, + .audio_supported = false, + .audio_pkt_in_hblank_area = false, +}; + +static const struct mtk_dp_data mt8188_dp_data = { + .bridge_type = DRM_MODE_CONNECTOR_DisplayPort, + .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE, + .efuse_fmt = mt8195_dp_efuse_fmt, + .audio_supported = true, + .audio_pkt_in_hblank_area = true, +}; + static const struct mtk_dp_data mt8195_edp_data = { .bridge_type = DRM_MODE_CONNECTOR_eDP, .smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE, .efuse_fmt = mt8195_edp_efuse_fmt, .audio_supported = false, + .audio_pkt_in_hblank_area = false, }; static const struct mtk_dp_data mt8195_dp_data = { @@ -2628,9 +2659,18 @@ static const struct mtk_dp_data mt8195_dp_data = { .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE, .efuse_fmt = mt8195_dp_efuse_fmt, .audio_supported = true, + .audio_pkt_in_hblank_area = false, }; static const struct of_device_id mtk_dp_of_match[] = { + { + .compatible = "mediatek,mt8188-edp-tx", + .data = &mt8188_edp_data, + }, + { + .compatible = "mediatek,mt8188-dp-tx", + .data = &mt8188_dp_data, + }, { .compatible = "mediatek,mt8195-edp-tx", .data = &mt8195_edp_data, diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h index 84e38cef03c2..f38d6ff12afe 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h @@ -228,6 +228,11 @@ VIDEO_STABLE_CNT_THRD_DP_ENC1_P0 | \ SDP_DP13_EN_DP_ENC1_P0 | \ BS2BS_MODE_DP_ENC1_P0) + +#define MTK_DP_ENC1_P0_3374 0x3374 +#define SDP_ASP_INSERT_IN_HBLANK_DP_ENC1_P0_MASK BIT(12) +#define SDP_DOWN_ASP_CNT_INIT_DP_ENC1_P0_MASK GENMASK(11, 0) + #define MTK_DP_ENC1_P0_33F4 0x33f4 #define DP_ENC_DUMMY_RW_1_AUDIO_RST_EN BIT(0) #define DP_ENC_DUMMY_RW_1 BIT(9) From patchwork Thu Jul 20 08:26:04 2023 Content-Type: text/plain; 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Thu, 20 Jul 2023 16:25:58 +0800 Received: from mszsdhlt06.gcn.mediatek.inc (10.16.6.206) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 20 Jul 2023 16:25:57 +0800 From: Shuijing Li To: , , , , , , , , , CC: , , , , , , Shuijing Li Subject: [PATCH v3,3/3] drm/mediatek: dp: Add the audio divider to mtk_dp_data struct Date: Thu, 20 Jul 2023 16:26:04 +0800 Message-ID: <20230720082604.18618-4-shuijing.li@mediatek.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230720082604.18618-1-shuijing.li@mediatek.com> References: <20230720082604.18618-1-shuijing.li@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230720_012608_563449_17F7B725 X-CRM114-Status: GOOD ( 15.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Due to the difference of HW, different dividers need to be set. Signed-off-by: Shuijing Li Signed-off-by: Jitao Shi Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- Changes in v3: Separate these two things into two different patches. per suggestion from the previous thread: https://lore.kernel.org/lkml/e2ad22bcba31797f38a12a488d4246a01bf0cb2e.camel@mediatek.com/ Changes in v2: - change the variables' name to be more descriptive - add a comment that describes the function of mtk_dp_audio_sample_arrange - reduce indentation by doing the inverse check - add a definition of some bits - add support for mediatek, mt8188-edp-tx per suggestion from the previous thread: https://lore.kernel.org/lkml/ac0fcec9-a2fe-06cc-c727-189ef7babe9c@collabora.com/ --- drivers/gpu/drm/mediatek/mtk_dp.c | 7 ++++++- drivers/gpu/drm/mediatek/mtk_dp_reg.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index d8cda83d6fef..8e1a13ab2ba2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -140,6 +140,7 @@ struct mtk_dp_data { const struct mtk_dp_efuse_fmt *efuse_fmt; bool audio_supported; bool audio_pkt_in_hblank_area; + u16 audio_m_div2_bit; }; static const struct mtk_dp_efuse_fmt mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = { @@ -648,7 +649,7 @@ static void mtk_dp_audio_sdp_asp_set_channels(struct mtk_dp *mtk_dp, static void mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp) { mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC, - AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, + mtk_dp->data->audio_m_div2_bit, AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK); } @@ -2636,6 +2637,7 @@ static const struct mtk_dp_data mt8188_edp_data = { .efuse_fmt = mt8195_edp_efuse_fmt, .audio_supported = false, .audio_pkt_in_hblank_area = false, + .audio_m_div2_bit = MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, }; static const struct mtk_dp_data mt8188_dp_data = { @@ -2644,6 +2646,7 @@ static const struct mtk_dp_data mt8188_dp_data = { .efuse_fmt = mt8195_dp_efuse_fmt, .audio_supported = true, .audio_pkt_in_hblank_area = true, + .audio_m_div2_bit = MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, }; static const struct mtk_dp_data mt8195_edp_data = { @@ -2652,6 +2655,7 @@ static const struct mtk_dp_data mt8195_edp_data = { .efuse_fmt = mt8195_edp_efuse_fmt, .audio_supported = false, .audio_pkt_in_hblank_area = false, + .audio_m_div2_bit = AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, }; static const struct mtk_dp_data mt8195_dp_data = { @@ -2660,6 +2664,7 @@ static const struct mtk_dp_data mt8195_dp_data = { .efuse_fmt = mt8195_dp_efuse_fmt, .audio_supported = true, .audio_pkt_in_hblank_area = false, + .audio_m_div2_bit = AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, }; static const struct of_device_id mtk_dp_of_match[] = { diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h index f38d6ff12afe..6d7f0405867e 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h @@ -162,6 +162,7 @@ #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8) #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8) #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8 (3 << 8) +#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (4 << 8) #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (5 << 8) #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (6 << 8) #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8)