From patchwork Fri Jul 21 07:54:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 13321533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E598EB64DD for ; Fri, 21 Jul 2023 07:55:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DBSKsCVLJIsF4TgsfMdzeGz30bA1MeB+i9ZhOowc7/E=; b=k6W35OMzQcl30u K2SCixXKBSUsgqGbyNZo8hG8rxJ0fPoK7v5j9baOBllS2wYiwyMG2yblEOwrAxoHmGpaCBsNmk71V sLeq8sKyVQlEEsXfmFpDAp/xejAVSpSxSy30rtlfbQkILVR1kk+k+2AlGKV+ysnyxQCTIHk2kLTW3 EOLUO7cFVXqRfOPeh6HZuha8WHPlDDsyJfKEscD3bWA45NNNerURefc0MKkeemjRrF9H6KOrxzcwL MFIc7/vBz3gxC1Oa7/G2l3mngwTE4LfK9bHt2cShlWyvMBHfuxIUGuedpRbuRNEvMV4IaCY9EUQf1 NVJURFVd/K9sN4xtoRRQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qMkyV-00DG5U-1K; Fri, 21 Jul 2023 07:54:55 +0000 Received: from mail-qk1-x72d.google.com ([2607:f8b0:4864:20::72d]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qMkyT-00DG2s-08 for linux-riscv@lists.infradead.org; Fri, 21 Jul 2023 07:54:54 +0000 Received: by mail-qk1-x72d.google.com with SMTP id af79cd13be357-765a1690003so159036185a.0 for ; Fri, 21 Jul 2023 00:54:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689926091; x=1690530891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s3u1lOqcX+rFr/12ZO+V0mL4AJbG+0yajCeAol8veJU=; b=ihe51+EG+C60YUxB7AocvCGuMa7zYMTuYaCjxA5WrAb+BpsUg9E4ce/9rtN4xmom9j 5iSdLKNgtVmv+mQkSlsWAw+0LqESqtrg6HJQVMZsP3tJHKwfqQmqBJuNw2/kGIKA/laJ x304IZPTrtv+f5nz8zp8/D0RQV8bzBPPoUpaNKeuBBBQptJKT5yJb8Fng9kqX8/7iDkA JpM/+4louXVnjU+lrgn2yv9AsT3O0Mz3kzkUrjGId/HSFetgYZ8QctbDAqbae8LPlikk 2HowdbEZu6HdzaAEANGzoO5L7xaLDXlFktgV5nIArIIVimB125rOg1FKhyWo+CgVVVqA ayog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689926091; x=1690530891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s3u1lOqcX+rFr/12ZO+V0mL4AJbG+0yajCeAol8veJU=; b=hmt9c1df1oEniDsr8hFtrFW5xVGMNhssKY9zFc4pkf1DbBAnr2VXTeppAQjuC5GnR9 AKy62sQu2j0zSa1sFlBaNEoN6ZTb+QHQhtKs3NW4H9zdfgLlMdPl5nCBkkY9GOruLuAb RiaFlSydnaHLsBh5phXFAeC70OXHzuqoyDF4EAB1eYcKtenosgBx40pVsIflm0U8Zd1B d0rbpLF+x6dUwgkjD2UCbSe90yXnxqRoWavyhy8kbNg4f9s0Iu52yBIW3ZjnQ/TqJJw2 9gptCjJ+E4kdXfrpmZMOTg8VRdWHmjvfEUELxdVbJ0QPYYqmbPg9VhmCe1nTqhD6GRoJ tZTg== X-Gm-Message-State: ABy/qLZ1FOps2HKXYHAmhzsUyY+X23Hzl8ri/I7ggHE/jPluQFSMzTVJ r8mNBRgHJOyCE4RK/ucQlfdMqw== X-Google-Smtp-Source: APBJJlHR5erD7wTV3lBrLRpvo3ypVzl5teqtGuyMa0LtCPD5Gkvmp6di/L4g2VyrLXQlCODMUW6leg== X-Received: by 2002:a05:620a:4085:b0:768:1572:ebd0 with SMTP id f5-20020a05620a408500b007681572ebd0mr1635854qko.31.1689926090685; Fri, 21 Jul 2023 00:54:50 -0700 (PDT) Received: from mchitale-vm.. ([117.99.250.48]) by smtp.googlemail.com with ESMTPSA id gw15-20020a17090b0a4f00b00267bb769652sm2026354pjb.6.2023.07.21.00.54.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 00:54:50 -0700 (PDT) From: Mayuresh Chitale To: Palmer Dabbelt , Anup Patel Cc: Mayuresh Chitale , Andrew Jones , Atish Patra , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 1/6] RISC-V: Detect Smstateen extension Date: Fri, 21 Jul 2023 13:24:34 +0530 Message-Id: <20230721075439.454473-2-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721075439.454473-1-mchitale@ventanamicro.com> References: <20230721075439.454473-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230721_005453_101973_2A1EB9FD X-CRM114-Status: GOOD ( 10.19 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Extend the ISA string parsing to detect the Smstateen extension Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 1 + 4 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index cc1f546fdbdc..1e6d0e182be1 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -128,6 +128,12 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + - const: smstateen + description: | + The standard Smstateen extension for controlling accesss to CSRs + added by other Risc-V extensions in H/S/VS/U/VU modes and as + ratified at commit a28bfae (Ratified (#7)). + - const: ssaia description: | The standard Ssaia supervisor-level extension for the advanced diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index f041bfa7f6a0..fad1fd1fcd05 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -53,6 +53,7 @@ #define RISCV_ISA_EXT_ZICSR 40 #define RISCV_ISA_EXT_ZIFENCEI 41 #define RISCV_ISA_EXT_ZIHPM 42 +#define RISCV_ISA_EXT_SMSTATEEN 43 #define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index a2fc952318e9..fb0df651bc48 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -217,6 +217,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = { __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index bdcf460ea53d..ddca31160637 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -301,6 +301,7 @@ void __init riscv_fill_hwcap(void) } else { /* sorted alphabetically */ SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); + SET_ISA_EXT_MAP("smstateen", RISCV_ISA_EXT_SMSTATEEN); SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); From patchwork Fri Jul 21 07:54:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 13321532 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E024FEB64DC for ; Fri, 21 Jul 2023 07:55:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nAJkGayy8dnvCHgAT0Ks0VviUxsrCMUlsiosD9FrgSE=; b=SSfVZVp+iCjm4d mQp9mTixogovjtVQAfpV/cqNyoRcVimucxxrK1R6U2pUUomXPwQu4xOXSQKowhMH59iBeY8oA3CBJ 42VoJPxwHGTptZcaIkqWjhvdl+5NaZJMpuXXgZUTEXjRCCDr/sujmDWVH3uEIVveDqcPe96ijArW/ VoOaM+dt70rUg9980fA0PFJYCdPjGO6M7L6qTvknsSBvggdfRb+U7jSe0eHb0z5rdqm830ZVf9jtg IPl9vn5YVS+gZlX4y2cwSLl6Fi1DnOfvYT1dUYw4t5O1BlzxcZwnNHsp3e0/juG7I1hWpGZDAXNK4 PFfm4PBqj79Fj3DrhvTw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qMkya-00DG8F-1u; Fri, 21 Jul 2023 07:55:00 +0000 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qMkyY-00DG4x-02 for linux-riscv@lists.infradead.org; Fri, 21 Jul 2023 07:54:59 +0000 Received: by mail-oi1-x22e.google.com with SMTP id 5614622812f47-3a3c77e0154so1175361b6e.1 for ; Fri, 21 Jul 2023 00:54:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689926094; x=1690530894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HlB+T7yzO9OziPQ1iUKQmwo9q1VQUiAhA5RgkQ17Yds=; b=BymmVUgtZ4M1uDHMF6FPUgtQUO4JSKtkMw3EOCivaFnfR+JyN3PuAVGURTy7ZgegSo cmJ1RTrN6wbtYjPEzCcRXyqqN8c7g5+yWq4VIFclECe773m4qZZ9vUPcbrwdZu5I3hCM aIFfBqtAeyfyujmMYpg51suGIVfohN0y3oRO/nBn6NEBT+JmVuBOoTb1YS8ZJ4/B1gsN 2JJ/IigAjenh+5cw7/tLnQOZD/DCYRZDQHwOK80C4hJjRgEmRe0qXpVUmUol4yKj/GiS KtLFg1qi9Mq+G9xC55n5pT71rhBise4+so4Q47RA6/F1K7DERJL/vMmscyksjwtsnQJH TcgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689926094; x=1690530894; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HlB+T7yzO9OziPQ1iUKQmwo9q1VQUiAhA5RgkQ17Yds=; b=B9eljI8CjMaRbfyZrKl9ZNoCKifGmeA1p4HvxFVtUDanZ1/rNCjHOuYZrsTv/u5pKk EqbqtODXjoL37PHheLZpFjhcQG3eCcuZ8jmwVdtHmBL9nGF9zG8fJ364lIo9ss98Bn6t Bca13GIHpto/xZDkEQGxRLxF1EbI7i7dRUyRkvMGSLOUnTWL6E4Q1LZ0bkK0oO1QHAMQ pi2Kdw2cj9LxokmiBAzxB8GdYTVezgpKboox9lphVllF/yG0T2MZIWvdeDMrUtxcipMJ P6ggrrVgIbfVJsG2wdLkKyEW7gwYw1jbhb82mvkTz8MYAPXlMlQo/AaK6mIrrUIv6RB2 f7Sg== X-Gm-Message-State: ABy/qLaJq0GAEZdFs/No1nHMZe4fot6lRXXioNJriKV9Ajzjs9HAB2gh Gg2HV2GeGggHkBrrOIM7xxCqqg== X-Google-Smtp-Source: APBJJlGYTpJtaWwlhs8n0NzK55RLP7Drr3jY9wVN3NIGLZPTFNkmJWbEwzWdzLxR7VmTtiI5wBJMGA== X-Received: by 2002:a54:4784:0:b0:3a3:7b77:bb2d with SMTP id o4-20020a544784000000b003a37b77bb2dmr1293180oic.13.1689926094109; Fri, 21 Jul 2023 00:54:54 -0700 (PDT) Received: from mchitale-vm.. ([117.99.250.48]) by smtp.googlemail.com with ESMTPSA id gw15-20020a17090b0a4f00b00267bb769652sm2026354pjb.6.2023.07.21.00.54.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 00:54:53 -0700 (PDT) From: Mayuresh Chitale To: Palmer Dabbelt , Anup Patel Cc: Mayuresh Chitale , Andrew Jones , Atish Patra , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 2/6] RISC-V: KVM: Add kvm_vcpu_config Date: Fri, 21 Jul 2023 13:24:35 +0530 Message-Id: <20230721075439.454473-3-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721075439.454473-1-mchitale@ventanamicro.com> References: <20230721075439.454473-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230721_005458_049292_D4AED0A9 X-CRM114-Status: GOOD ( 13.30 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add a placeholder for all registers such as henvcfg, hstateen etc which have 'static' configurations depending on extensions supported by the guest. The values are derived once and are then subsequently written to the corresponding CSRs while switching to the vcpu. Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_host.h | 7 +++++++ arch/riscv/kvm/vcpu.c | 27 ++++++++++++++------------- 2 files changed, 21 insertions(+), 13 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 2d8ee53b66c7..c0c50b4b3394 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -164,6 +164,10 @@ struct kvm_vcpu_csr { unsigned long scounteren; }; +struct kvm_vcpu_config { + u64 henvcfg; +}; + struct kvm_vcpu_arch { /* VCPU ran at least once */ bool ran_atleast_once; @@ -244,6 +248,9 @@ struct kvm_vcpu_arch { /* Performance monitoring context */ struct kvm_pmu pmu_context; + + /* 'static' configurations which are set only once */ + struct kvm_vcpu_config cfg; }; static inline void kvm_arch_sync_events(struct kvm *kvm) {} diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index d12ef99901fc..e01f47bb636f 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -980,31 +980,28 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, return -EINVAL; } -static void kvm_riscv_vcpu_update_config(const unsigned long *isa) +static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu) { - u64 henvcfg = 0; + const unsigned long *isa = vcpu->arch.isa; + struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; if (riscv_isa_extension_available(isa, SVPBMT)) - henvcfg |= ENVCFG_PBMTE; + cfg->henvcfg |= ENVCFG_PBMTE; if (riscv_isa_extension_available(isa, SSTC)) - henvcfg |= ENVCFG_STCE; + cfg->henvcfg |= ENVCFG_STCE; if (riscv_isa_extension_available(isa, ZICBOM)) - henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE); + cfg->henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE); if (riscv_isa_extension_available(isa, ZICBOZ)) - henvcfg |= ENVCFG_CBZE; - - csr_write(CSR_HENVCFG, henvcfg); -#ifdef CONFIG_32BIT - csr_write(CSR_HENVCFGH, henvcfg >> 32); -#endif + cfg->henvcfg |= ENVCFG_CBZE; } void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; csr_write(CSR_VSSTATUS, csr->vsstatus); csr_write(CSR_VSIE, csr->vsie); @@ -1015,8 +1012,9 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) csr_write(CSR_VSTVAL, csr->vstval); csr_write(CSR_HVIP, csr->hvip); csr_write(CSR_VSATP, csr->vsatp); - - kvm_riscv_vcpu_update_config(vcpu->arch.isa); + csr_write(CSR_HENVCFG, cfg->henvcfg); + if (IS_ENABLED(CONFIG_32BIT)) + csr_write(CSR_HENVCFGH, cfg->henvcfg >> 32); kvm_riscv_gstage_update_hgatp(vcpu); @@ -1136,6 +1134,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) struct kvm_cpu_trap trap; struct kvm_run *run = vcpu->run; + if (!vcpu->arch.ran_atleast_once) + kvm_riscv_vcpu_setup_config(vcpu); + /* Mark this VCPU ran at least once */ vcpu->arch.ran_atleast_once = true; From patchwork Fri Jul 21 07:54:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 13321534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70A12EB64DC for ; Fri, 21 Jul 2023 07:55:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IxUEKDGv15KznNPLo7ZTmUz1cwFEBWL0mFa9aefySUk=; b=khVt/m2uPFzyLx 3yqtSPOcPzyRw2eLwiB4klmvN5HP/60O8vm7SORun35LoRZ/NwSrHdrDI47clq4atdg+Q0mi9K6Qn t2xLY+uCDqVu6I41C2U51W7lFi7hm7FnkoSkeJIYNtPwGAYzsPxxFvjQo7nJ72dfxBdlPTbESNtTk 4OuhwOQwnFO/b61cb/0A6DnHqXn7fT9jpj9grIaPd6yAiJBimVSDG9Gg5Qadd4ND64jVg1OlSMxAv j1WmRDTw8liDFGC/67DrHVL2eyjBL6eSSH0xWqOG9Y5zMf5EROXSLYOJ+XcEwT9pr1d86E0IxTDWz LSJRXc6idftaBTQUgDHw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qMkye-00DGB5-0z; Fri, 21 Jul 2023 07:55:04 +0000 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qMkyZ-00DG78-24 for linux-riscv@lists.infradead.org; Fri, 21 Jul 2023 07:55:01 +0000 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-263374f2f17so788053a91.0 for ; Fri, 21 Jul 2023 00:54:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689926098; x=1690530898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F6URFlWvIburf3cR9HtAr9E2Sh/GiXynH5eeSEzuJxs=; b=g6eVzbur7N5OQwGKWU4xOXSsBuUHVlOZBiazQBvBqS8ljMjDSNpMuZBnSXnxMOpVbI JKXg9cOdca11E3NxcHEWV9J0GK9MCMoi6/74aQI2hiAUgI8ona9ICMXmQd3pQ2XiBnN6 1D4nADPGiA181lgkMr5nOulQnOfZiqfb3mgqItN6HDwAZJFfu3wgWU1RoIej+rs5UKaY wjYABZYEoKpRLzhRHQXcNd67Exvpr4H1umlh7iRPgZdujcLIocCs/Chcv7uFbjWrwnOw zV1pxPpsrFMcp49Y5A/Q71O57EgOzRbhbgRzaa3jOhstGDXhKYc/7DJx4vQE5cY6KA4g Rjvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689926098; x=1690530898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F6URFlWvIburf3cR9HtAr9E2Sh/GiXynH5eeSEzuJxs=; b=CBCcsHavqKLtYAMyLbM5pd/O7yP0CKNTT47dWhTC+pWtsrfoRvuqhFhjW0VKbm1uAe h4dLAhtcOkVn7YjwshktFXEeuct2zPRzkaPYr4RRdjAPl+7IvuMe9j89ml322pNN3Ri+ J6p426D3BG6RNe8XDP71Ra4vqsQKsy8sFJQhFj7wxj8VTZ0capmF4K73ZrVbECBvbUML gAWyHbmAkowaFqMuRWy8ko/hP7Y901ybjqai02+wGti0hnVWhJir/zOGRipSfEbxgyyB tiob5yxo+VZSBsWKUlkJ3eUVN18g4iZTSvJ5EiuNyd1NAmGGNxXegZbFBVx/3i1g2C7r efDw== X-Gm-Message-State: ABy/qLYZ+KxFSvlv+0CmgC2STJgLGa0M5LCRBu3INy2DXVsWTH0swQDA vCGNUA7sKDe0wNBhFiqFxYnzWg== X-Google-Smtp-Source: APBJJlEBmHCRgnhAHXvit81djKdQy7LdYCIoiEcGc1skML726y8vbCjMQEz/JM3FugmIqtTXS8NLZA== X-Received: by 2002:a17:90b:a55:b0:265:7719:b83e with SMTP id gw21-20020a17090b0a5500b002657719b83emr744753pjb.43.1689926097563; Fri, 21 Jul 2023 00:54:57 -0700 (PDT) Received: from mchitale-vm.. ([117.99.250.48]) by smtp.googlemail.com with ESMTPSA id gw15-20020a17090b0a4f00b00267bb769652sm2026354pjb.6.2023.07.21.00.54.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 00:54:57 -0700 (PDT) From: Mayuresh Chitale To: Palmer Dabbelt , Anup Patel Cc: Mayuresh Chitale , Andrew Jones , Atish Patra , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 3/6] RISC-V: KVM: Enable Smstateen accesses Date: Fri, 21 Jul 2023 13:24:36 +0530 Message-Id: <20230721075439.454473-4-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721075439.454473-1-mchitale@ventanamicro.com> References: <20230721075439.454473-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230721_005459_704105_F83100AE X-CRM114-Status: GOOD ( 12.38 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Configure hstateen0 register so that the AIA state and envcfg are accessible to the vcpus. This includes registers such as siselect, sireg, siph, sieh and all the IMISC registers. Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones --- arch/riscv/include/asm/csr.h | 16 ++++++++++++++++ arch/riscv/include/asm/kvm_host.h | 1 + arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu.c | 16 ++++++++++++++++ 4 files changed, 34 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 7bac43a3176e..38730677dcd5 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -201,6 +201,18 @@ #define ENVCFG_CBIE_INV _AC(0x3, UL) #define ENVCFG_FIOM _AC(0x1, UL) +/* Smstateen bits */ +#define SMSTATEEN0_AIA_IMSIC_SHIFT 58 +#define SMSTATEEN0_AIA_IMSIC (_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT) +#define SMSTATEEN0_AIA_SHIFT 59 +#define SMSTATEEN0_AIA (_ULL(1) << SMSTATEEN0_AIA_SHIFT) +#define SMSTATEEN0_AIA_ISEL_SHIFT 60 +#define SMSTATEEN0_AIA_ISEL (_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT) +#define SMSTATEEN0_HSENVCFG_SHIFT 62 +#define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) +#define SMSTATEEN0_SSTATEEN0_SHIFT 63 +#define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) + /* symbolic CSR names: */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 @@ -347,6 +359,10 @@ #define CSR_VSIEH 0x214 #define CSR_VSIPH 0x254 +/* Hypervisor stateen CSRs */ +#define CSR_HSTATEEN0 0x60c +#define CSR_HSTATEEN0H 0x61c + #define CSR_MSTATUS 0x300 #define CSR_MISA 0x301 #define CSR_MIDELEG 0x303 diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index c0c50b4b3394..ee55e5fc8b84 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -166,6 +166,7 @@ struct kvm_vcpu_csr { struct kvm_vcpu_config { u64 henvcfg; + u64 hstateen0; }; struct kvm_vcpu_arch { diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 930fdc4101cd..7bc1634b0a89 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -124,6 +124,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_SSAIA, KVM_RISCV_ISA_EXT_V, KVM_RISCV_ISA_EXT_SVNAPOT, + KVM_RISCV_ISA_EXT_SMSTATEEN, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index e01f47bb636f..d3166b676430 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -70,6 +70,7 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(ZIHINTPAUSE), KVM_ISA_EXT_ARR(ZICBOM), KVM_ISA_EXT_ARR(ZICBOZ), + KVM_ISA_EXT_ARR(SMSTATEEN), }; static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext) @@ -996,6 +997,16 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu) if (riscv_isa_extension_available(isa, ZICBOZ)) cfg->henvcfg |= ENVCFG_CBZE; + + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { + cfg->hstateen0 |= SMSTATEEN0_HSENVCFG; + if (riscv_isa_extension_available(isa, SSAIA)) + cfg->hstateen0 |= SMSTATEEN0_AIA_IMSIC | + SMSTATEEN0_AIA | + SMSTATEEN0_AIA_ISEL; + if (riscv_isa_extension_available(isa, SMSTATEEN)) + cfg->hstateen0 |= SMSTATEEN0_SSTATEEN0; + } } void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) @@ -1015,6 +1026,11 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) csr_write(CSR_HENVCFG, cfg->henvcfg); if (IS_ENABLED(CONFIG_32BIT)) csr_write(CSR_HENVCFGH, cfg->henvcfg >> 32); + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { + csr_write(CSR_HSTATEEN0, cfg->hstateen0); + if (IS_ENABLED(CONFIG_32BIT)) + csr_write(CSR_HSTATEEN0H, cfg->hstateen0 >> 32); + } kvm_riscv_gstage_update_hgatp(vcpu); From patchwork Fri Jul 21 07:54:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 13321535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4687EB64DD for ; Fri, 21 Jul 2023 07:55:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Nj/x6yp85SEMlaoDuYKVe/hw80lM6ouxAmUuJeiABLs=; b=j2li/gRL/4bWV0 Gb1LuwdP8i0hDYVNfMnD2CD3A38QJBkc9bvBUGbuOY2TXywZ99fjirfQNmk9x3RAn5rXY2P/TgIR4 bBJZ+Lebuo5LR97f57lYGWhJeixMs+VwvVhF8pQw9jxVZKirDBKXxe1SzGPf4RXOB/qPCEtRg7idh g006YByBKy4jMAm59xihRKhGMaqp3OGqpe8OUDUua2gEmrNCwmq2w6vy4Eme4Gk8+wK5lIay6PdRh AOBIWXldrPEEjJJC2Un7tx5AMmE/AIBnQMaqVfFntFhf/wnteT9wyEAo71FEjQz3a6QaGQJn2/PrH TI9czW9qgPEaPmlmY4gQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qMkyh-00DGEG-1b; Fri, 21 Jul 2023 07:55:07 +0000 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qMkyd-00DG94-1s for linux-riscv@lists.infradead.org; Fri, 21 Jul 2023 07:55:05 +0000 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1b8b318c5cfso12301955ad.1 for ; Fri, 21 Jul 2023 00:55:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689926101; x=1690530901; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CGBsjC7R6pFZ8BRmiJjujTJrCojG0NvQ+VqCGQxFEb8=; b=RnYza+kyjQyxCAyVAxBY2RUUF67emk/2HKI8+NDy6jj2xeuaEPS9N1UlbFyXkJD9WZ E9LJhQllA1750VprhrUF8OCOg73OmalUAiO1IntMWESCZj5dKA/FAOaea17Eu2Gr8kPm yptUsaSa5f4oWu8ffMDgrDMRWtTN+BLVdKMrawVN37ETioRCKGLProts2wF08p/Bd3sf fLJJKTzZsyD8R3A7j9jfys6Xq2hHF08XZu+N+fdHDtM9YF9F65gfBSpe6xcbiDFDMb7Z KF81zKoI5GbkU+UovILz7A349OhSdCNEUoAHR49KXcMTl7nz0AzfSZeMJWqlA9d2mvDi BhAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689926101; x=1690530901; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CGBsjC7R6pFZ8BRmiJjujTJrCojG0NvQ+VqCGQxFEb8=; b=jXiPinOebOKxZYHyDtiUjvyHCpifCmX649pAVnE5EK6MRbgz0Unbaa33X5hHMkJtBO 0/cze1cmGNr026zOnQbaHSsphtDyZMRFBJbVYDPLj8ksLF1N8ieOqdyh8+9/fT/ZbbxQ A89FOD+H6ZHWvpv3WxrrZRAsP0eXKVSleR+vqthRg8LBAcdjqVN0tibVn6wNb/dS756D vv3w8ee75lfL9ZUGP4BkhdzemTM6ucPT5tqDUWeZAqHQB2pKUxERLY8lXs2ku3V1rT90 6EKOvgKv9BAbUGvJ7qqXhe0nB9992dYf0rha9LJECbrHf7TCE/qzzfpb0s/ciLf95g6b UUhA== X-Gm-Message-State: ABy/qLb97qfNHcO5Ld//9LuYsxcn2bbtwcgaywzQynY2sIyE2wIyPaKH UzV76zsl5cXVvHjeLOAZkHmrZQ== X-Google-Smtp-Source: APBJJlFskkMmdMiIC4jkpeNR1u8Qiu0tCLX7ktYilZ+2f4tbI5hilxVC5cF1N9Od4zXXQvpmRPpT9g== X-Received: by 2002:a17:90a:77cc:b0:25b:ea12:a2f5 with SMTP id e12-20020a17090a77cc00b0025bea12a2f5mr810046pjs.35.1689926101134; Fri, 21 Jul 2023 00:55:01 -0700 (PDT) Received: from mchitale-vm.. ([117.99.250.48]) by smtp.googlemail.com with ESMTPSA id gw15-20020a17090b0a4f00b00267bb769652sm2026354pjb.6.2023.07.21.00.54.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 00:55:00 -0700 (PDT) From: Mayuresh Chitale To: Palmer Dabbelt , Anup Patel Cc: Mayuresh Chitale , Andrew Jones , Atish Patra , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 4/6] RISCV: KVM: Add senvcfg context save/restore Date: Fri, 21 Jul 2023 13:24:37 +0530 Message-Id: <20230721075439.454473-5-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721075439.454473-1-mchitale@ventanamicro.com> References: <20230721075439.454473-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230721_005503_628322_02746C6A X-CRM114-Status: GOOD ( 11.63 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add senvcfg context save/restore for guest VCPUs and also add it to the ONE_REG interface to allow its access from user space. Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones --- arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/kvm_host.h | 2 ++ arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu.c | 4 ++++ 4 files changed, 8 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 38730677dcd5..b52270278733 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -285,6 +285,7 @@ #define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 +#define CSR_SENVCFG 0x10a #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index ee55e5fc8b84..c3cc0cb39cf8 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -162,6 +162,7 @@ struct kvm_vcpu_csr { unsigned long hvip; unsigned long vsatp; unsigned long scounteren; + unsigned long senvcfg; }; struct kvm_vcpu_config { @@ -188,6 +189,7 @@ struct kvm_vcpu_arch { unsigned long host_sscratch; unsigned long host_stvec; unsigned long host_scounteren; + unsigned long host_senvcfg; /* CPU context of Host */ struct kvm_cpu_context host_context; diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 7bc1634b0a89..74c7f42de29d 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -79,6 +79,7 @@ struct kvm_riscv_csr { unsigned long sip; unsigned long satp; unsigned long scounteren; + unsigned long senvcfg; }; /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index d3166b676430..37f1ed70d782 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -1138,10 +1138,14 @@ static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu) */ static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu) { + struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + + vcpu->arch.host_senvcfg = csr_swap(CSR_SENVCFG, csr->senvcfg); guest_state_enter_irqoff(); __kvm_riscv_switch_to(&vcpu->arch); vcpu->arch.last_exit_cpu = vcpu->cpu; guest_state_exit_irqoff(); + csr->senvcfg = csr_swap(CSR_SENVCFG, vcpu->arch.host_senvcfg); } int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) From patchwork Fri Jul 21 07:54:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 13321536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 292B4C0015E for ; Fri, 21 Jul 2023 07:55:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9iZ8CHpXEFwg8OAxE3hfcZuDnCgIMvrwot2RJCQWNxA=; b=kGx58cDvDJFz79 Liw+bYHgRTXC81FYnrpKE5l/l8MattRkP99i8BfBY+kqORNFhd3/NIzRWUlVmMxyjPHwtYzJSXknx P2129epzMhCDLA2Jaw6FmnDjyHjAauVIGyX5oEZFOiqZkAp9ib79cWhQe3yG5DYVbxFJhSwZTBYPJ cirY/bf+Ke7YaGx4Vja9j1tChyk26L/vTuChhlfic/76DEmoBCUkB2XO/jMlwy/wIkMfiDCMkJ2To bRX9hqwBOsV0TlZSi8ho8gq8AvUZIz7Bw7jeqmHsMbGZWFfhW8OS3yVZolVRBVXiaqLqyB67oTy3a DUh1b/8/VxexrbxeoAUA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qMkyj-00DGGp-2R; Fri, 21 Jul 2023 07:55:09 +0000 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qMkyf-00DGBq-10 for linux-riscv@lists.infradead.org; Fri, 21 Jul 2023 07:55:06 +0000 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-2657d405ad5so976464a91.1 for ; Fri, 21 Jul 2023 00:55:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689926105; x=1690530905; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z6aeGGP2x/C4YQl5Th+aPcXB0i2yZ1ORWC7FX4YYM9c=; b=RxIf5r8Mi5cE3V8zR7uYPMPaKGtoLs5d1q9Jk/xHh56GGVcxVRd/zIkizLfowmbAuk Bt8ClVDVyVh2s8ouxDvbIXDchhIp3M8AMSgLcbQOAXdbasUDi9cMBdARODR4WvdWSE/u rr00U8GeSrRiKJKihRnIzIKL8fOtsrRZ3HtnS9qQRBNYLlNFmF+WdvsOCbmUCcLRtybq nk6tiEe3fvDhD56eL0FwvFGRlp6fy14aMOVAEg/Dzt+j5HX+EtjgVCl61q2QcOjzSahC fgdPrphzoaz6740Vv0iryVCrKuaxZmkMzuWGENjw2hmATf13Ldr+X0UpPTPHAWUxkSg1 8mXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689926105; x=1690530905; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z6aeGGP2x/C4YQl5Th+aPcXB0i2yZ1ORWC7FX4YYM9c=; b=eoWXhdhJOaUfuxsrt4VPQY5tiQcNMIG6w3wiQIbkYxd88QJxjZxTWLwlA3DlfzfH+4 0Vis/BBkH8xXnSdgNbY2u/kYDR53lR9uAD3v05w373w/UeBvoZlKjwUznvBWvw+fsppa RsC5jFEdoQ77DkpQT2iarx3jDDCXxwvJnxWxnMshuM+OMaGV1/+lz71aDWOyPuEvE/DD 30MqKBY43KBvkb+J759hrq4fk6/xYIJc10az/hEtQBbCPNWdZwG1+Dky2Z4mIxjFWhCt Fl9VHwdUUR6szXDsyOgG1xxOBCic01OJxHjbnGfgBcQ/L2IJo43AK96Ztb1er982muUu yKVw== X-Gm-Message-State: ABy/qLbUkHffD9WPkuVMmpPLqzrZ2mqsCXhXSK5U4E+pOxbI4tWjBDpr ql9BbVksZRLgw+iLDhsUE2CPBA== X-Google-Smtp-Source: APBJJlFlaCCjo3ica43J3v2eS9XgiorY1FVzcb095X10s0Ma8S3UGsVrdtP+9HARJosg9BMb2amXpQ== X-Received: by 2002:a17:90a:db09:b0:25c:1138:d97c with SMTP id g9-20020a17090adb0900b0025c1138d97cmr963165pjv.24.1689926104662; Fri, 21 Jul 2023 00:55:04 -0700 (PDT) Received: from mchitale-vm.. ([117.99.250.48]) by smtp.googlemail.com with ESMTPSA id gw15-20020a17090b0a4f00b00267bb769652sm2026354pjb.6.2023.07.21.00.55.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 00:55:04 -0700 (PDT) From: Mayuresh Chitale To: Palmer Dabbelt , Anup Patel Cc: Mayuresh Chitale , Andrew Jones , Atish Patra , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 5/6] RISCV: KVM: Add sstateen0 context save/restore Date: Fri, 21 Jul 2023 13:24:38 +0530 Message-Id: <20230721075439.454473-6-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721075439.454473-1-mchitale@ventanamicro.com> References: <20230721075439.454473-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230721_005505_388188_E326D5A0 X-CRM114-Status: GOOD ( 12.59 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Define sstateen0 and add sstateen0 save/restore for guest VCPUs. Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones --- arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/kvm_host.h | 8 ++++++++ arch/riscv/kvm/vcpu.c | 10 ++++++++++ 3 files changed, 19 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index b52270278733..5168f37d8e75 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -286,6 +286,7 @@ #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 #define CSR_SENVCFG 0x10a +#define CSR_SSTATEEN0 0x10c #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index c3cc0cb39cf8..c9837772b109 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -170,6 +170,10 @@ struct kvm_vcpu_config { u64 hstateen0; }; +struct kvm_vcpu_smstateen_csr { + unsigned long sstateen0; +}; + struct kvm_vcpu_arch { /* VCPU ran at least once */ bool ran_atleast_once; @@ -190,6 +194,7 @@ struct kvm_vcpu_arch { unsigned long host_stvec; unsigned long host_scounteren; unsigned long host_senvcfg; + unsigned long host_sstateen0; /* CPU context of Host */ struct kvm_cpu_context host_context; @@ -200,6 +205,9 @@ struct kvm_vcpu_arch { /* CPU CSR context of Guest VCPU */ struct kvm_vcpu_csr guest_csr; + /* CPU Smstateen CSR context of Guest VCPU */ + struct kvm_vcpu_smstateen_csr smstateen_csr; + /* CPU context upon Guest VCPU reset */ struct kvm_cpu_context guest_reset_context; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 37f1ed70d782..ae750decbefe 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -1138,14 +1138,24 @@ static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu) */ static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu) { + struct kvm_vcpu_smstateen_csr *smcsr = &vcpu->arch.smstateen_csr; struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; + struct kvm_vcpu_config *cfg = &vcpu->arch.cfg; vcpu->arch.host_senvcfg = csr_swap(CSR_SENVCFG, csr->senvcfg); + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) && + (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0)) + vcpu->arch.host_sstateen0 = csr_swap(CSR_SSTATEEN0, + smcsr->sstateen0); guest_state_enter_irqoff(); __kvm_riscv_switch_to(&vcpu->arch); vcpu->arch.last_exit_cpu = vcpu->cpu; guest_state_exit_irqoff(); csr->senvcfg = csr_swap(CSR_SENVCFG, vcpu->arch.host_senvcfg); + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN) && + (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0)) + smcsr->sstateen0 = csr_swap(CSR_SSTATEEN0, + vcpu->arch.host_sstateen0); } int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) From patchwork Fri Jul 21 07:54:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 13321537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5517BC001DE for ; Fri, 21 Jul 2023 07:55:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aN5FdEvnD9Dn5INZiOZdvWvETXwSLEmZWGYZeSODJGM=; b=JgkEzcF5APQEuh I97BrkbtnjVbNE3YQATDeuGFoWIW6QtJ0EmPW+Yuetgtrl0xdzWd/ddBmtNz8M8SVlrl/1TTlondJ ZqZWuEEJ8IB1FZohcD/9aR+xtgfJtQq+RzIka/dsE+xQ/kGmOeUfAqCPbQUd9bq5t96ugm8HfdjKK MbQ34SHGqsRxlFk0IUI1gmAdfwrjAOICqoe/sZLqTzwfyXr5oFNjT757TQYe0ezIJXkcpIw9oLaCA 2OQvH9SZaBRFw9sN+GSvVDlN58eJGLpfZqZgIwN/po3IsCOo5t8m1zY6WN4YVATv4XnfS2ieCkvZe k5oXDd8N30Ake4ho1eGg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qMkym-00DGKb-2r; Fri, 21 Jul 2023 07:55:12 +0000 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qMkyi-00DGF3-1w for linux-riscv@lists.infradead.org; Fri, 21 Jul 2023 07:55:10 +0000 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-2633b669f5fso892684a91.2 for ; Fri, 21 Jul 2023 00:55:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689926108; x=1690530908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U6Ksr06UW7Dx/X9GfjFaRawS2ArEeJDwaLwbdE4Z+oI=; b=Ja/9rqUcR8mguD9SerxDWAbqKtWAu6RjjRsr2AeiDMvODUQZujXzQYXuUn/b4fj/uv oJew2Ebd4XM+fwYGJEP1Y3WcH6PwukQkxgYGhZSE6Mku82auaTl4UgitpvZRS2fs6B4A ADL12DH2PszuH/dWJy5BLCnCckXJIFunkhQLQ8hgRFdr9Vo2VRKNb7a1Mae7grfaO2XC o4jmP0Gg/RouywZtpGDT4kn6EphzOpVArtgO/OkYivuMqj6GkF1kt+cW7ljacwjzIv3t aR50eaCv59fZ6oNMS+cnnVfASbro9hWYc3/XoPrAzO1PJ/lz2Y7UfhiTNhixevZYbI1o B03g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689926108; x=1690530908; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U6Ksr06UW7Dx/X9GfjFaRawS2ArEeJDwaLwbdE4Z+oI=; b=i80TWw1Djb+jRLwufnVBOKzksXvMrg81CAVRStSZxPFAwBXumgTHYx5bwLND+27AhM Nj8Sx6Q7JUqWoc+WfwcyWKsufB2pEEzGHtveoGSQxR4JVek1Z3g7SEddUYd42IC3a7RA sZAm5GqjWY9YEQ/6uZY4dCsh1evokLeATKOGLPehLxZqw1zUT3jjgRHK7sZ233y6/36Z +1bWyJc/o6fD337k9yWcAzZv/hUqAl10zAI7Go1prv8mNcHFaymSsuSKaDnJFeYSqqsd M/MRmj99GWYAVL7GjQZbm77gFJ2EADJrjpF40yXCurUBA2T5vnAacItUdsqMoAuCM59U ZwkA== X-Gm-Message-State: ABy/qLYBLVlNCk7HgE/wMwyZGLGWqnYRtZ/X2do2/Z1+YSrjWedVd6fQ YOXCFYYHVeK+lu1vcafNp0olMg== X-Google-Smtp-Source: APBJJlGE29fF9otfzxTa+Yc4pCr9JKSbe3hHM4bYDxgEMtQhDF2xwHv5P89OKxXsFtp5FJcLnbfCOw== X-Received: by 2002:a17:90a:7642:b0:263:41ae:8163 with SMTP id s2-20020a17090a764200b0026341ae8163mr759011pjl.12.1689926108062; Fri, 21 Jul 2023 00:55:08 -0700 (PDT) Received: from mchitale-vm.. ([117.99.250.48]) by smtp.googlemail.com with ESMTPSA id gw15-20020a17090b0a4f00b00267bb769652sm2026354pjb.6.2023.07.21.00.55.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 00:55:07 -0700 (PDT) From: Mayuresh Chitale To: Palmer Dabbelt , Anup Patel Cc: Mayuresh Chitale , Andrew Jones , Atish Patra , Paul Walmsley , Albert Ou , linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Subject: [PATCH v2 6/6] RISCV: KVM: Add sstateen0 to ONE_REG Date: Fri, 21 Jul 2023 13:24:39 +0530 Message-Id: <20230721075439.454473-7-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230721075439.454473-1-mchitale@ventanamicro.com> References: <20230721075439.454473-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230721_005508_654795_09CE2AD9 X-CRM114-Status: GOOD ( 11.99 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add support for sstateen0 CSR to the ONE_REG interface to allow its access from user space. Signed-off-by: Mayuresh Chitale Reviewed-by: Andrew Jones --- arch/riscv/include/uapi/asm/kvm.h | 9 +++++++ arch/riscv/kvm/vcpu.c | 40 +++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 74c7f42de29d..bdddfb20299a 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -93,6 +93,11 @@ struct kvm_riscv_aia_csr { unsigned long iprio2h; }; +/* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ +struct kvm_riscv_smstateen_csr { + unsigned long sstateen0; +}; + /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ struct kvm_riscv_timer { __u64 frequency; @@ -173,10 +178,14 @@ enum KVM_RISCV_SBI_EXT_ID { #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) +#define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) + #define KVM_REG_RISCV_CSR_REG(name) \ (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) #define KVM_REG_RISCV_CSR_AIA_REG(name) \ (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) +#define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \ + (offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long)) /* Timer registers are mapped as type 4 */ #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index ae750decbefe..af7549374c4b 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -507,6 +507,34 @@ static int kvm_riscv_vcpu_general_get_csr(struct kvm_vcpu *vcpu, return 0; } +static inline int kvm_riscv_vcpu_smstateen_set_csr(struct kvm_vcpu *vcpu, + unsigned long reg_num, + unsigned long reg_val) +{ + struct kvm_vcpu_smstateen_csr *csr = &vcpu->arch.smstateen_csr; + + if (reg_num >= sizeof(struct kvm_riscv_smstateen_csr) / + sizeof(unsigned long)) + return -EINVAL; + + ((unsigned long *)csr)[reg_num] = reg_val; + return 0; +} + +static int kvm_riscv_vcpu_smstateen_get_csr(struct kvm_vcpu *vcpu, + unsigned long reg_num, + unsigned long *out_val) +{ + struct kvm_vcpu_smstateen_csr *csr = &vcpu->arch.smstateen_csr; + + if (reg_num >= sizeof(struct kvm_riscv_smstateen_csr) / + sizeof(unsigned long)) + return -EINVAL; + + *out_val = ((unsigned long *)csr)[reg_num]; + return 0; +} + static inline int kvm_riscv_vcpu_general_set_csr(struct kvm_vcpu *vcpu, unsigned long reg_num, unsigned long reg_val) @@ -552,6 +580,12 @@ static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu, case KVM_REG_RISCV_CSR_AIA: rc = kvm_riscv_vcpu_aia_get_csr(vcpu, reg_num, ®_val); break; + case KVM_REG_RISCV_CSR_SMSTATEEN: + rc = -EINVAL; + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) + rc = kvm_riscv_vcpu_smstateen_get_csr(vcpu, reg_num, + ®_val); + break; default: rc = -EINVAL; break; @@ -591,6 +625,12 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu, case KVM_REG_RISCV_CSR_AIA: rc = kvm_riscv_vcpu_aia_set_csr(vcpu, reg_num, reg_val); break; + case KVM_REG_RISCV_CSR_SMSTATEEN: + rc = -EINVAL; + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) + rc = kvm_riscv_vcpu_smstateen_set_csr(vcpu, reg_num, + reg_val); + break; default: rc = -EINVAL; break;