From patchwork Fri Jul 21 17:02:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Anastasio X-Patchwork-Id: 13322387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F3ABEB64DC for ; Fri, 21 Jul 2023 17:03:35 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.567667.887002 (Exim 4.92) (envelope-from ) id 1qMtX6-0002wk-9a; Fri, 21 Jul 2023 17:03:12 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 567667.887002; Fri, 21 Jul 2023 17:03:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qMtX6-0002vi-5g; Fri, 21 Jul 2023 17:03:12 +0000 Received: by outflank-mailman (input) for mailman id 567667; Fri, 21 Jul 2023 17:03:11 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qMtX5-0002su-2M for xen-devel@lists.xenproject.org; Fri, 21 Jul 2023 17:03:11 +0000 Received: from raptorengineering.com (mail.raptorengineering.com [23.155.224.40]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 7735ddd6-27e8-11ee-8611-37d641c3527e; Fri, 21 Jul 2023 19:03:08 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by mail.rptsys.com (Postfix) with ESMTP id A9EF38285A38; Fri, 21 Jul 2023 12:03:07 -0500 (CDT) Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id l0yDkxV9icTe; Fri, 21 Jul 2023 12:03:06 -0500 (CDT) Received: from localhost (localhost [127.0.0.1]) by mail.rptsys.com (Postfix) with ESMTP id A766C82854B9; Fri, 21 Jul 2023 12:03:06 -0500 (CDT) Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 48LnXrMlU6Zm; Fri, 21 Jul 2023 12:03:06 -0500 (CDT) Received: from raptor-ewks-026.lan (5.edge.rptsys.com [23.155.224.38]) by mail.rptsys.com (Postfix) with ESMTPSA id 45715828595C; Fri, 21 Jul 2023 12:03:06 -0500 (CDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7735ddd6-27e8-11ee-8611-37d641c3527e DKIM-Filter: OpenDKIM Filter v2.10.3 mail.rptsys.com A766C82854B9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raptorengineering.com; s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1689958986; bh=5BKPx6suFK1+ADUkLZOgesyhysDJmQwNfyKldiRHhA4=; h=From:To:Date:Message-Id:MIME-Version; b=SURVH41qAVPMC5b5EA14Bdc9QA9CBTpegQPILnyETN2hFEBtoNjwhatpgAtHh9OF6 xlBHXdEU9UhAMWhij8jPkceWcAKRtSwa2MdY86Lpu5U7uaL2tID+GBXVjXdJ6D0a8k iF5lXhKKalAfyN8KS0vVOHS8iP+p7MyENxEH8hK0= X-Virus-Scanned: amavisd-new at rptsys.com From: Shawn Anastasio To: xen-devel@lists.xenproject.org Cc: Timothy Pearson , Andrew Cooper , Jan Beulich , Julien Grall , Shawn Anastasio Subject: [PATCH v5 1/4] common: Move a few more standalone macros from xen/lib.h to xen/macros.h Date: Fri, 21 Jul 2023 12:02:52 -0500 Message-Id: <4f4d87438933b39859f8e3e8009092056fe8c885.1689958538.git.sanastasio@raptorengineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: References: MIME-Version: 1.0 Move a few more macros which have no dependencies on other headers from xen/lib.h to xen/macros.h. Notably, this includes BUILD_BUG_ON* and ARRAY_SIZE. Signed-off-by: Shawn Anastasio Reviewed-by: Jan Beulich --- xen/include/xen/lib.h | 28 ---------------------------- xen/include/xen/macros.h | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 28 deletions(-) diff --git a/xen/include/xen/lib.h b/xen/include/xen/lib.h index dae2a1f085..359cfdc784 100644 --- a/xen/include/xen/lib.h +++ b/xen/include/xen/lib.h @@ -21,24 +21,6 @@ unlikely(ret_warn_on_); \ }) -/* All clang versions supported by Xen have _Static_assert. */ -#if defined(__clang__) || \ - (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6)) -/* Force a compilation error if condition is true */ -#define BUILD_BUG_ON(cond) ({ _Static_assert(!(cond), "!(" #cond ")"); }) - -/* Force a compilation error if condition is true, but also produce a - result (of value 0 and type size_t), so the expression can be used - e.g. in a structure initializer (or where-ever else comma expressions - aren't permitted). */ -#define BUILD_BUG_ON_ZERO(cond) \ - (sizeof(struct { char c; _Static_assert(!(cond), "!(" #cond ")"); }) & 0) -#else -#define BUILD_BUG_ON_ZERO(cond) \ - (sizeof(struct { unsigned u : !(cond); }) & 0) -#define BUILD_BUG_ON(cond) ((void)BUILD_BUG_ON_ZERO(cond)) -#endif - #ifndef NDEBUG #define ASSERT(p) \ do { if ( unlikely(!(p)) ) assert_failed(#p); } while (0) @@ -48,16 +30,6 @@ #define ASSERT_UNREACHABLE() do { } while (0) #endif -#define ABS(_x) ({ \ - typeof(_x) __x = (_x); \ - (__x < 0) ? -__x : __x; \ -}) - -#define SWAP(_a, _b) \ - do { typeof(_a) _t = (_a); (_a) = (_b); (_b) = _t; } while ( 0 ) - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]) + __must_be_array(x)) - #define __ACCESS_ONCE(x) ({ \ (void)(typeof(x))0; /* Scalar typecheck. */ \ (volatile typeof(x) *)&(x); }) diff --git a/xen/include/xen/macros.h b/xen/include/xen/macros.h index 7b92d34504..d0caae7db2 100644 --- a/xen/include/xen/macros.h +++ b/xen/include/xen/macros.h @@ -22,6 +22,40 @@ #define __STR(...) #__VA_ARGS__ #define STR(...) __STR(__VA_ARGS__) +#ifndef __ASSEMBLY__ + +/* All clang versions supported by Xen have _Static_assert. */ +#if defined(__clang__) || \ + (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 6)) +/* Force a compilation error if condition is true */ +#define BUILD_BUG_ON(cond) ({ _Static_assert(!(cond), "!(" #cond ")"); }) + +/* + * Force a compilation error if condition is true, but also produce a + * result (of value 0 and type size_t), so the expression can be used + * e.g. in a structure initializer (or where-ever else comma expressions + * aren't permitted). + */ +#define BUILD_BUG_ON_ZERO(cond) \ + (sizeof(struct { char c; _Static_assert(!(cond), "!(" #cond ")"); }) & 0) +#else +#define BUILD_BUG_ON_ZERO(cond) \ + (sizeof(struct { unsigned u : !(cond); }) & 0) +#define BUILD_BUG_ON(cond) ((void)BUILD_BUG_ON_ZERO(cond)) +#endif + +#define ABS(x) ({ \ + typeof(x) x_ = (x); \ + (x_ < 0) ? -x_ : x_; \ +}) + +#define SWAP(a, b) \ + do { typeof(a) t_ = (a); (a) = (b); (b) = t_; } while ( 0 ) + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]) + __must_be_array(x)) + +#endif /* __ASSEMBLY__ */ + #endif /* __MACROS_H__ */ /* From patchwork Fri Jul 21 17:02:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Anastasio X-Patchwork-Id: 13322388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C5DCC001DC for ; Fri, 21 Jul 2023 17:03:36 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.567669.887023 (Exim 4.92) (envelope-from ) id 1qMtX7-0003Pr-Pi; Fri, 21 Jul 2023 17:03:13 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 567669.887023; Fri, 21 Jul 2023 17:03:13 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qMtX7-0003PL-L9; Fri, 21 Jul 2023 17:03:13 +0000 Received: by outflank-mailman (input) for mailman id 567669; Fri, 21 Jul 2023 17:03:11 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qMtX5-0002su-Nx for xen-devel@lists.xenproject.org; Fri, 21 Jul 2023 17:03:11 +0000 Received: from raptorengineering.com (mail.raptorengineering.com [23.155.224.40]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 778727c0-27e8-11ee-8611-37d641c3527e; Fri, 21 Jul 2023 19:03:09 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by mail.rptsys.com (Postfix) with ESMTP id 568D98285A06; Fri, 21 Jul 2023 12:03:08 -0500 (CDT) Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id KqJ-kWF68Ul5; Fri, 21 Jul 2023 12:03:07 -0500 (CDT) Received: from localhost (localhost [127.0.0.1]) by mail.rptsys.com (Postfix) with ESMTP id 15E41828595C; Fri, 21 Jul 2023 12:03:07 -0500 (CDT) Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id D5wmjkLXSz4k; Fri, 21 Jul 2023 12:03:06 -0500 (CDT) Received: from raptor-ewks-026.lan (5.edge.rptsys.com [23.155.224.38]) by mail.rptsys.com (Postfix) with ESMTPSA id 9F92882859FC; Fri, 21 Jul 2023 12:03:06 -0500 (CDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 778727c0-27e8-11ee-8611-37d641c3527e DKIM-Filter: OpenDKIM Filter v2.10.3 mail.rptsys.com 15E41828595C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raptorengineering.com; s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1689958987; bh=ot5Ie8UdNaBUzL6s4Mi2/vuXyjwBSH6uhSdPEOjpn9g=; h=From:To:Date:Message-Id:MIME-Version; b=RRiv+VvCP3dHBFwfujo6kiiJo/OT/XamwmEcBq654mWbgKxTOcNUPMPmLMFfqRh6V VanEdHWFIdM06YGvIay0AL2LRVfYgg3pnlNDH9RLbNIjJN6p1ch8Nyxvv+Kkyxl6Ag tHtY8m+30eMqLe8hJ0rlYFvqPO5hyQW8IV1iMgAU= X-Virus-Scanned: amavisd-new at rptsys.com From: Shawn Anastasio To: xen-devel@lists.xenproject.org Cc: Timothy Pearson , Andrew Cooper , Jan Beulich , Julien Grall , Shawn Anastasio Subject: [PATCH v5 2/4] xen/ppc: Set up a basic C environment Date: Fri, 21 Jul 2023 12:02:53 -0500 Message-Id: <27548375e29c56d87f08be800e38fb85c650568a.1689958538.git.sanastasio@raptorengineering.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: References: MIME-Version: 1.0 Update ppc64/head.S to set up an initial boot stack, zero the .bss section, and jump to C. The required setup is done using 32-bit immediate address loads for now, but they will be changed to TOC-relative loads once the position-independent code model is enabled. Additionally, move the cpu0_boot_stack declaration to setup.c and change STACK_ORDER from 2 to 0. For now, ppc64 is using 64k pages and thus the larger STACK_ORDER is unnecessary. Finally, refactor the endian fixup trampoline into its own macro, since it will need to be used in multiple places, including every time we make a call into firmware. Signed-off-by: Shawn Anastasio Acked-by: Jan Beulich --- xen/arch/ppc/Makefile | 2 ++ xen/arch/ppc/include/asm/asm-defns.h | 40 ++++++++++++++++++++++++++++ xen/arch/ppc/include/asm/config.h | 2 +- xen/arch/ppc/ppc64/head.S | 38 +++++++++++++------------- xen/arch/ppc/setup.c | 19 +++++++++++++ 5 files changed, 80 insertions(+), 21 deletions(-) create mode 100644 xen/arch/ppc/include/asm/asm-defns.h create mode 100644 xen/arch/ppc/setup.c diff --git a/xen/arch/ppc/Makefile b/xen/arch/ppc/Makefile index 98220648af..530fba2121 100644 --- a/xen/arch/ppc/Makefile +++ b/xen/arch/ppc/Makefile @@ -1,5 +1,7 @@ obj-$(CONFIG_PPC64) += ppc64/ +obj-y += setup.o + $(TARGET): $(TARGET)-syms cp -f $< $@ diff --git a/xen/arch/ppc/include/asm/asm-defns.h b/xen/arch/ppc/include/asm/asm-defns.h new file mode 100644 index 0000000000..6ea35f6edb --- /dev/null +++ b/xen/arch/ppc/include/asm/asm-defns.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef _ASM_PPC_ASM_DEFNS_H +#define _ASM_PPC_ASM_DEFNS_H + +/* + * Load a 64-bit immediate value into the specified GPR. + */ +#define LOAD_IMM64(reg, val) \ + lis reg, (val) @highest; \ + ori reg, reg, (val) @higher; \ + rldicr reg, reg, 32, 31; \ + oris reg, reg, (val) @h; \ + ori reg, reg, (val) @l; + +#define LOAD_IMM32(reg, val) \ + lis reg, (val) @h; \ + ori reg, reg, (val) @l; \ + +/* + * Depending on how we were booted, the CPU could be running in either + * Little Endian or Big Endian mode. The following trampoline from Linux + * cleverly uses an instruction that encodes to a NOP if the CPU's + * endianness matches the assumption of the assembler (LE, in our case) + * or a branch to code that performs the endian switch in the other case. + */ +#define FIXUP_ENDIAN \ + tdi 0, 0, 0x48; /* Reverse endian of b . + 8 */ \ + b . + 44; /* Skip trampoline if endian is good */ \ + .long 0xa600607d; /* mfmsr r11 */ \ + .long 0x01006b69; /* xori r11,r11,1 */ \ + .long 0x00004039; /* li r10,0 */ \ + .long 0x6401417d; /* mtmsrd r10,1 */ \ + .long 0x05009f42; /* bcl 20,31,$+4 */ \ + .long 0xa602487d; /* mflr r10 */ \ + .long 0x14004a39; /* addi r10,r10,20 */ \ + .long 0xa6035a7d; /* mtsrr0 r10 */ \ + .long 0xa6037b7d; /* mtsrr1 r11 */ \ + .long 0x2400004c /* rfid */ + +#endif /* _ASM_PPC_ASM_DEFNS_H */ diff --git a/xen/arch/ppc/include/asm/config.h b/xen/arch/ppc/include/asm/config.h index b9a6814f00..01ca5d0803 100644 --- a/xen/arch/ppc/include/asm/config.h +++ b/xen/arch/ppc/include/asm/config.h @@ -43,7 +43,7 @@ #define SMP_CACHE_BYTES (1 << 6) -#define STACK_ORDER 2 +#define STACK_ORDER 0 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER) /* 288 bytes below the stack pointer must be preserved by interrupt handlers */ diff --git a/xen/arch/ppc/ppc64/head.S b/xen/arch/ppc/ppc64/head.S index 2fcefb40d8..49b3066396 100644 --- a/xen/arch/ppc/ppc64/head.S +++ b/xen/arch/ppc/ppc64/head.S @@ -1,30 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include + .section .text.header, "ax", %progbits ENTRY(start) /* - * Depending on how we were booted, the CPU could be running in either - * Little Endian or Big Endian mode. The following trampoline from Linux - * cleverly uses an instruction that encodes to a NOP if the CPU's - * endianness matches the assumption of the assembler (LE, in our case) - * or a branch to code that performs the endian switch in the other case. + * NOTE: argument registers (r3-r9) must be preserved until the C entrypoint */ - tdi 0, 0, 0x48 /* Reverse endian of b . + 8 */ - b . + 44 /* Skip trampoline if endian is good */ - .long 0xa600607d /* mfmsr r11 */ - .long 0x01006b69 /* xori r11,r11,1 */ - .long 0x00004039 /* li r10,0 */ - .long 0x6401417d /* mtmsrd r10,1 */ - .long 0x05009f42 /* bcl 20,31,$+4 */ - .long 0xa602487d /* mflr r10 */ - .long 0x14004a39 /* addi r10,r10,20 */ - .long 0xa6035a7d /* mtsrr0 r10 */ - .long 0xa6037b7d /* mtsrr1 r11 */ - .long 0x2400004c /* rfid */ - - /* Now that the endianness is confirmed, continue */ -1: b 1b + FIXUP_ENDIAN + + /* set up the TOC pointer */ + LOAD_IMM32(%r2, .TOC.) + + /* set up the initial stack */ + LOAD_IMM32(%r1, cpu0_boot_stack) + li %r11, 0 + stdu %r11, -STACK_FRAME_OVERHEAD(%r1) + + /* call the C entrypoint */ + bl start_xen + + /* should never return */ + trap .size start, . - start .type start, %function diff --git a/xen/arch/ppc/setup.c b/xen/arch/ppc/setup.c new file mode 100644 index 0000000000..9e90a6179a --- /dev/null +++ b/xen/arch/ppc/setup.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include + +/* Xen stack for bringing up the first CPU. */ +unsigned char __initdata cpu0_boot_stack[STACK_SIZE] __aligned(STACK_SIZE); + +/* Macro to adjust thread priority for hardware multithreading */ +#define HMT_very_low() asm volatile ( "or %r31, %r31, %r31" ) + +void __init noreturn start_xen(unsigned long r3, unsigned long r4, + unsigned long r5, unsigned long r6, + unsigned long r7) +{ + for ( ; ; ) + /* Set current hardware thread to very low priority */ + HMT_very_low(); + + unreachable(); +} From patchwork Fri Jul 21 17:02:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Anastasio X-Patchwork-Id: 13322391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6337AEB64DC for ; Fri, 21 Jul 2023 17:03:46 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.567670.887031 (Exim 4.92) (envelope-from ) id 1qMtX8-0003bT-A1; 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Fri, 21 Jul 2023 12:03:10 -0500 (CDT) Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id LWZtriQeiBlq; Fri, 21 Jul 2023 12:03:07 -0500 (CDT) Received: from localhost (localhost [127.0.0.1]) by mail.rptsys.com (Postfix) with ESMTP id B67A48285A3C; Fri, 21 Jul 2023 12:03:07 -0500 (CDT) Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id tKj-fC7cowRt; Fri, 21 Jul 2023 12:03:07 -0500 (CDT) Received: from raptor-ewks-026.lan (5.edge.rptsys.com [23.155.224.38]) by mail.rptsys.com (Postfix) with ESMTPSA id 216818285A06; Fri, 21 Jul 2023 12:03:07 -0500 (CDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 78ae5832-27e8-11ee-b23a-6b7b168915f2 DKIM-Filter: OpenDKIM Filter v2.10.3 mail.rptsys.com B67A48285A3C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raptorengineering.com; s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1689958987; bh=49thkP8FJpYosT0RNEvML+dgM4MKq2ZDLUB0IJ8Se+s=; h=From:To:Date:Message-Id:MIME-Version; b=EeE1KqJuVCFuVditieVBUEpDrbxOD4Wh7GJne68/wsAFGZcSaxsX9PTL9V8C9NA9x Romc0zmu0B7wZnbCnckRhe7T0+naSBG+pfAgcTlZCTW2wUP0xkofv9X7NhoFJmwmqA tnlzF07ZItTc78/oA05XlJSO5voqva8eAm3Nf4jE= X-Virus-Scanned: amavisd-new at rptsys.com From: Shawn Anastasio To: xen-devel@lists.xenproject.org Cc: Timothy Pearson , Andrew Cooper , Jan Beulich , Julien Grall , Shawn Anastasio Subject: [PATCH v5 3/4] xen/ppc: Implement early serial printk on pseries Date: Fri, 21 Jul 2023 12:02:54 -0500 Message-Id: X-Mailer: git-send-email 2.30.2 In-Reply-To: References: MIME-Version: 1.0 On typical Power VMs (e.g. QEMU's -M pseries), a variety of services including an early serial console are provided by Open Firmware. Implement the required interfaces to call into Open Firmware and write to the serial console. Since Open Firmware runs in 32-bit Big Endian mode and Xen runs in 64-bit Little Endian mode, a thunk is required to save/restore any potentially-clobbered registers as well as to perform the required endianness switch. Thankfully, linux already has such a routine, which was imported into ppc64/of-call.S. Support for bare metal (PowerNV) will be implemented in a future patch. Signed-off-by: Shawn Anastasio Acked-by: Jan Beulich --- xen/arch/ppc/Kconfig.debug | 5 + xen/arch/ppc/Makefile | 2 + xen/arch/ppc/boot-of.c | 113 +++++++++++++++++++ xen/arch/ppc/configs/ppc64_defconfig | 1 + xen/arch/ppc/early_printk.c | 28 +++++ xen/arch/ppc/include/asm/asm-defns.h | 17 +++ xen/arch/ppc/include/asm/boot.h | 23 ++++ xen/arch/ppc/include/asm/byteorder.h | 12 +++ xen/arch/ppc/include/asm/config.h | 3 + xen/arch/ppc/include/asm/early_printk.h | 15 +++ xen/arch/ppc/include/asm/msr.h | 51 +++++++++ xen/arch/ppc/include/asm/processor.h | 138 ++++++++++++++++++++++++ xen/arch/ppc/include/asm/types.h | 21 ++++ xen/arch/ppc/ppc64/Makefile | 1 + xen/arch/ppc/ppc64/asm-offsets.c | 58 ++++++++++ xen/arch/ppc/ppc64/head.S | 9 ++ xen/arch/ppc/ppc64/of-call.S | 83 ++++++++++++++ xen/arch/ppc/setup.c | 19 +++- 18 files changed, 596 insertions(+), 3 deletions(-) create mode 100644 xen/arch/ppc/boot-of.c create mode 100644 xen/arch/ppc/early_printk.c create mode 100644 xen/arch/ppc/include/asm/boot.h create mode 100644 xen/arch/ppc/include/asm/byteorder.h create mode 100644 xen/arch/ppc/include/asm/early_printk.h create mode 100644 xen/arch/ppc/include/asm/msr.h create mode 100644 xen/arch/ppc/include/asm/processor.h create mode 100644 xen/arch/ppc/include/asm/types.h create mode 100644 xen/arch/ppc/ppc64/of-call.S diff --git a/xen/arch/ppc/Kconfig.debug b/xen/arch/ppc/Kconfig.debug index e69de29bb2..608c9ff832 100644 --- a/xen/arch/ppc/Kconfig.debug +++ b/xen/arch/ppc/Kconfig.debug @@ -0,0 +1,5 @@ +config EARLY_PRINTK + bool "Enable early printk" + default DEBUG + help + Enables early printk debug messages diff --git a/xen/arch/ppc/Makefile b/xen/arch/ppc/Makefile index 530fba2121..098a4dd0a9 100644 --- a/xen/arch/ppc/Makefile +++ b/xen/arch/ppc/Makefile @@ -1,5 +1,7 @@ obj-$(CONFIG_PPC64) += ppc64/ +obj-y += boot-of.init.o +obj-$(CONFIG_EARLY_PRINTK) += early_printk.init.o obj-y += setup.o $(TARGET): $(TARGET)-syms diff --git a/xen/arch/ppc/boot-of.c b/xen/arch/ppc/boot-of.c new file mode 100644 index 0000000000..a06546871e --- /dev/null +++ b/xen/arch/ppc/boot-of.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * This file was derived from Xen 3.2's xen/arch/powerpc/boot_of.c, + * originally licensed under GPL version 2 or later. + * + * Copyright IBM Corp. 2005, 2006, 2007 + * Copyright Raptor Engineering, LLC + * + * Authors: Jimi Xenidis + * Hollis Blanchard + * Shawn Anastasio + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * The Open Firmware client interface is called in 32-bit mode with the MMU off, + * so any addresses passed to it must be physical addresses under 4GB. + * + * Since the client interface is only used during early boot before the MMU is on + * and Xen itself was loaded by Open Firmware (and therefore resides below 4GB), + * we can achieve the desired result with a simple cast to uint32_t. + */ +#define ADDR(x) ((uint32_t)(unsigned long)(x)) + +/* OF entrypoint*/ +static unsigned long __initdata of_vec; + +static int __initdata of_out; + +static int __init of_call(const char *service, uint32_t nargs, uint32_t nrets, + int32_t rets[], ...) +{ + int rc; + va_list args; + unsigned int i; + struct of_service s = { 0 }; + + s.ofs_service = cpu_to_be32(ADDR(service)); + s.ofs_nargs = cpu_to_be32(nargs); + s.ofs_nrets = cpu_to_be32(nrets); + + /* Copy all the params into the args array */ + va_start(args, rets); + + for ( i = 0; i < nargs; i++ ) + s.ofs_args[i] = cpu_to_be32(va_arg(args, uint32_t)); + + va_end(args); + + rc = enter_of(&s, of_vec); + + /* Copy all return values to the output rets array */ + for ( i = 0; i < nrets; i++ ) + rets[i] = be32_to_cpu(s.ofs_args[i + nargs]); + + return rc; +} + +static int __init of_finddevice(const char *devspec) +{ + int32_t rets[1] = { OF_FAILURE }; + + of_call("finddevice", 1, ARRAY_SIZE(rets), rets, ADDR(devspec)); + return rets[0]; +} + +static int __init of_getprop(int ph, const char *name, void *buf, uint32_t buflen) +{ + int32_t rets[1] = { OF_FAILURE }; + + of_call("getprop", 4, ARRAY_SIZE(rets), rets, ph, ADDR(name), ADDR(buf), + buflen); + return rets[0]; +} + +int __init of_write(int ih, const char *addr, uint32_t len) +{ + int32_t rets[1] = { OF_FAILURE }; + + of_call("write", 3, ARRAY_SIZE(rets), rets, ih, ADDR(addr), len); + return rets[0]; +} + +static void __init of_putchar(char c) +{ + if ( c == '\n' ) + { + char buf = '\r'; + of_write(of_out, &buf, 1); + } + of_write(of_out, &c, 1); +} + +void __init boot_of_init(unsigned long vec) +{ + int bof_chosen; + + of_vec = vec; + + /* Get a handle to the default console */ + bof_chosen = of_finddevice("/chosen"); + of_getprop(bof_chosen, "stdout", &of_out, sizeof(of_out)); + of_out = be32_to_cpu(of_out); + + early_printk_init(of_putchar); +} diff --git a/xen/arch/ppc/configs/ppc64_defconfig b/xen/arch/ppc/configs/ppc64_defconfig index 8783eb3488..f7cc075e45 100644 --- a/xen/arch/ppc/configs/ppc64_defconfig +++ b/xen/arch/ppc/configs/ppc64_defconfig @@ -10,4 +10,5 @@ CONFIG_PPC64=y CONFIG_DEBUG=y CONFIG_DEBUG_INFO=y +CONFIG_EARLY_PRINTK=y CONFIG_EXPERT=y diff --git a/xen/arch/ppc/early_printk.c b/xen/arch/ppc/early_printk.c new file mode 100644 index 0000000000..781f82133e --- /dev/null +++ b/xen/arch/ppc/early_printk.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include + +static void __initdata (*putchar_func)(char); + +void __init early_printk_init(void (*putchar)(char)) +{ + putchar_func = putchar; +} + +void __init early_puts(const char *s, size_t nr) +{ + if ( !putchar_func ) + return; + + while ( nr-- > 0 ) + putchar_func(*s++); +} + +void __init early_printk(const char *s) +{ + if ( !putchar_func ) + return; + + while ( *s ) + putchar_func(*s++); +} diff --git a/xen/arch/ppc/include/asm/asm-defns.h b/xen/arch/ppc/include/asm/asm-defns.h index 6ea35f6edb..9d7328f4a2 100644 --- a/xen/arch/ppc/include/asm/asm-defns.h +++ b/xen/arch/ppc/include/asm/asm-defns.h @@ -37,4 +37,21 @@ .long 0xa6037b7d; /* mtsrr1 r11 */ \ .long 0x2400004c /* rfid */ + +/* Taken from Linux kernel source (arch/powerpc/boot/crt0.S) */ +.macro OP_REGS op, width, start, end, base, offset + .Lreg=\start + .rept (\end - \start + 1) + \op .Lreg,\offset+\width*.Lreg(\base) + .Lreg=.Lreg+1 + .endr +.endm + +#define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, 0 +#define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, 0 +#define SAVE_GPR(n, base) SAVE_GPRS(n, n, base) +#define REST_GPR(n, base) REST_GPRS(n, n, base) +#define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base) +#define REST_NVGPRS(base) REST_GPRS(14, 31, base) + #endif /* _ASM_PPC_ASM_DEFNS_H */ diff --git a/xen/arch/ppc/include/asm/boot.h b/xen/arch/ppc/include/asm/boot.h new file mode 100644 index 0000000000..9b8a7c43c2 --- /dev/null +++ b/xen/arch/ppc/include/asm/boot.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_PPC_BOOT_H +#define _ASM_PPC_BOOT_H + +#include + +/* a collection of interfaces used during boot. */ +enum { + OF_FAILURE = -1, + OF_SUCCESS = 0, +}; + +struct of_service { + __be32 ofs_service; + __be32 ofs_nargs; + __be32 ofs_nrets; + __be32 ofs_args[10]; +}; + +int enter_of(struct of_service *args, unsigned long entry); +void boot_of_init(unsigned long vec); + +#endif /* _ASM_PPC_BOOT_H */ diff --git a/xen/arch/ppc/include/asm/byteorder.h b/xen/arch/ppc/include/asm/byteorder.h new file mode 100644 index 0000000000..2b5f6b9f63 --- /dev/null +++ b/xen/arch/ppc/include/asm/byteorder.h @@ -0,0 +1,12 @@ +#ifndef _ASM_PPC_BYTEORDER_H +#define _ASM_PPC_BYTEORDER_H + +#define __arch__swab16 __builtin_bswap16 +#define __arch__swab32 __builtin_bswap32 +#define __arch__swab64 __builtin_bswap64 + +#define __BYTEORDER_HAS_U64__ + +#include + +#endif /* _ASM_PPC_BYTEORDER_H */ diff --git a/xen/arch/ppc/include/asm/config.h b/xen/arch/ppc/include/asm/config.h index 01ca5d0803..cb27d2781e 100644 --- a/xen/arch/ppc/include/asm/config.h +++ b/xen/arch/ppc/include/asm/config.h @@ -52,6 +52,9 @@ /* size of minimum stack frame; C code can write into the caller's stack */ #define STACK_FRAME_OVERHEAD 32 +/* ELFv2 ABI mandates 16 byte alignment */ +#define STACK_ALIGN 16 + #endif /* __PPC_CONFIG_H__ */ /* * Local variables: diff --git a/xen/arch/ppc/include/asm/early_printk.h b/xen/arch/ppc/include/asm/early_printk.h new file mode 100644 index 0000000000..d1d8b416f4 --- /dev/null +++ b/xen/arch/ppc/include/asm/early_printk.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_PPC_EARLY_PRINTK_H +#define _ASM_PPC_EARLY_PRINTK_H + +#include + +#ifdef CONFIG_EARLY_PRINTK +void early_printk_init(void (*putchar)(char)); +void early_printk(const char *s); +#else +static inline void early_printk_init(void (*putchar)(char)) {} +static inline void early_printk(const char *s) {} +#endif + +#endif /* _ASM_PPC_EARLY_PRINTK_H */ diff --git a/xen/arch/ppc/include/asm/msr.h b/xen/arch/ppc/include/asm/msr.h new file mode 100644 index 0000000000..144511e5c3 --- /dev/null +++ b/xen/arch/ppc/include/asm/msr.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) IBM Corp. 2005 + * Copyright Raptor Engineering, LLC + * + * Authors: Jimi Xenidis + * Shawn Anastasio + */ + +#ifndef _ASM_PPC_MSR_H +#define _ASM_PPC_MSR_H + +#include + +/* Flags in MSR: */ +#define MSR_SF _AC(0x8000000000000000, ULL) +#define MSR_TA _AC(0x4000000000000000, ULL) +#define MSR_ISF _AC(0x2000000000000000, ULL) +#define MSR_HV _AC(0x1000000000000000, ULL) +#define MSR_VMX _AC(0x0000000002000000, ULL) +#define MSR_MER _AC(0x0000000000200000, ULL) +#define MSR_POW _AC(0x0000000000040000, ULL) +#define MSR_ILE _AC(0x0000000000010000, ULL) +#define MSR_EE _AC(0x0000000000008000, ULL) +#define MSR_PR _AC(0x0000000000004000, ULL) +#define MSR_FP _AC(0x0000000000002000, ULL) +#define MSR_ME _AC(0x0000000000001000, ULL) +#define MSR_FE0 _AC(0x0000000000000800, ULL) +#define MSR_SE _AC(0x0000000000000400, ULL) +#define MSR_BE _AC(0x0000000000000200, ULL) +#define MSR_FE1 _AC(0x0000000000000100, ULL) +#define MSR_IP _AC(0x0000000000000040, ULL) +#define MSR_IR _AC(0x0000000000000020, ULL) +#define MSR_DR _AC(0x0000000000000010, ULL) +#define MSR_PMM _AC(0x0000000000000004, ULL) +#define MSR_RI _AC(0x0000000000000002, ULL) +#define MSR_LE _AC(0x0000000000000001, ULL) + +/* MSR bits set on the systemsim simulator */ +#define MSR_SIM _AC(0x0000000020000000, ULL) +#define MSR_SYSTEMSIM _AC(0x0000000010000000, ULL) + +/* On a trap, srr1's copy of msr defines some bits as follows: */ +#define MSR_TRAP_FE _AC(0x0000000000100000, ULL) /* Floating Point Exception */ +#define MSR_TRAP_IOP _AC(0x0000000000080000, ULL) /* Illegal Instruction */ +#define MSR_TRAP_PRIV _AC(0x0000000000040000, ULL) /* Privileged Instruction */ +#define MSR_TRAP _AC(0x0000000000020000, ULL) /* Trap Instruction */ +#define MSR_TRAP_NEXT _AC(0x0000000000010000, ULL) /* PC is next instruction */ +#define MSR_TRAP_BITS (MSR_TRAP_FE|MSR_TRAP_IOP|MSR_TRAP_PRIV|MSR_TRAP) + +#endif /* _ASM_PPC_MSR_H */ diff --git a/xen/arch/ppc/include/asm/processor.h b/xen/arch/ppc/include/asm/processor.h new file mode 100644 index 0000000000..838d279508 --- /dev/null +++ b/xen/arch/ppc/include/asm/processor.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright IBM Corp. 2005, 2006, 2007 + * Copyright Raptor Engineering, LLC + * + * Authors: Hollis Blanchard + * Christian Ehrhardt + * Timothy Pearson + * Shawn Anastasio + */ + +#ifndef _ASM_PPC_PROCESSOR_H +#define _ASM_PPC_PROCESSOR_H + +#define IOBMP_BYTES 8192 +#define IOBMP_INVALID_OFFSET 0x8000 + +/* Processor Version Register (PVR) field extraction */ + +#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ +#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ + +#define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv)) + +/* + * IBM has further subdivided the standard PowerPC 16-bit version and + * revision subfields of the PVR for the PowerPC 403s into the following: + */ + +#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ +#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ +#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ +#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ +#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ +#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ + +/* Processor Version Numbers */ + +#define PVR_403GA 0x00200000 +#define PVR_403GB 0x00200100 +#define PVR_403GC 0x00200200 +#define PVR_403GCX 0x00201400 +#define PVR_405GP 0x40110000 +#define PVR_STB03XXX 0x40310000 +#define PVR_NP405H 0x41410000 +#define PVR_NP405L 0x41610000 +#define PVR_601 0x00010000 +#define PVR_602 0x00050000 +#define PVR_603 0x00030000 +#define PVR_603e 0x00060000 +#define PVR_603ev 0x00070000 +#define PVR_603r 0x00071000 +#define PVR_604 0x00040000 +#define PVR_604e 0x00090000 +#define PVR_604r 0x000A0000 +#define PVR_620 0x00140000 +#define PVR_740 0x00080000 +#define PVR_750 PVR_740 +#define PVR_740P 0x10080000 +#define PVR_750P PVR_740P +#define PVR_7400 0x000C0000 +#define PVR_7410 0x800C0000 +#define PVR_7450 0x80000000 +#define PVR_8540 0x80200000 +#define PVR_8560 0x80200000 +/* + * For the 8xx processors, all of them report the same PVR family for + * the PowerPC core. The various versions of these processors must be + * differentiated by the version number in the Communication Processor + * Module (CPM). + */ +#define PVR_821 0x00500000 +#define PVR_823 PVR_821 +#define PVR_850 PVR_821 +#define PVR_860 PVR_821 +#define PVR_8240 0x00810100 +#define PVR_8245 0x80811014 +#define PVR_8260 PVR_8240 + +/* 64-bit processors */ +#define PVR_NORTHSTAR 0x0033 +#define PVR_PULSAR 0x0034 +#define PVR_POWER4 0x0035 +#define PVR_ICESTAR 0x0036 +#define PVR_SSTAR 0x0037 +#define PVR_POWER4p 0x0038 +#define PVR_970 0x0039 +#define PVR_POWER5 0x003A +#define PVR_POWER5p 0x003B +#define PVR_970FX 0x003C +#define PVR_POWER6 0x003E +#define PVR_POWER7 0x003F +#define PVR_630 0x0040 +#define PVR_630p 0x0041 +#define PVR_970MP 0x0044 +#define PVR_970GX 0x0045 +#define PVR_POWER7p 0x004A +#define PVR_POWER8E 0x004B +#define PVR_POWER8NVL 0x004C +#define PVR_POWER8 0x004D +#define PVR_POWER9 0x004E +#define PVR_POWER10 0x0080 +#define PVR_BE 0x0070 +#define PVR_PA6T 0x0090 + +#ifndef __ASSEMBLY__ + +#include + +/* Macro to adjust thread priority for hardware multithreading */ +#define HMT_very_low() asm volatile ( "or %r31, %r31, %r31" ) + +/* + * User-accessible registers: most of these need to be saved/restored + * for every nested Xen invocation. + */ +struct cpu_user_regs +{ + uint64_t gprs[32]; + uint64_t lr; + uint64_t ctr; + uint64_t srr0; + uint64_t srr1; + uint64_t pc; + uint64_t msr; + uint64_t fpscr; + uint64_t xer; + uint64_t hid4; /* debug only */ + uint64_t dar; /* debug only */ + uint32_t dsisr; /* debug only */ + uint32_t cr; + uint32_t __pad; /* good spot for another 32bit reg */ + uint32_t entry_vector; +}; + +#endif + +#endif /* _ASM_PPC_PROCESSOR_H */ diff --git a/xen/arch/ppc/include/asm/types.h b/xen/arch/ppc/include/asm/types.h new file mode 100644 index 0000000000..cee08e111a --- /dev/null +++ b/xen/arch/ppc/include/asm/types.h @@ -0,0 +1,21 @@ +/* from xen/arch/x86/include/asm/types.h */ + +#ifndef _ASM_PPC_TYPES_H +#define _ASM_PPC_TYPES_H + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long s64; +typedef unsigned long u64; +typedef unsigned long paddr_t; +#define INVALID_PADDR (~0UL) +#define PRIpaddr "016lx" + +#endif /* _ASM_PPC_TYPES_H */ diff --git a/xen/arch/ppc/ppc64/Makefile b/xen/arch/ppc/ppc64/Makefile index 3340058c08..f4956daaa9 100644 --- a/xen/arch/ppc/ppc64/Makefile +++ b/xen/arch/ppc/ppc64/Makefile @@ -1 +1,2 @@ obj-y += head.o +obj-y += of-call.o diff --git a/xen/arch/ppc/ppc64/asm-offsets.c b/xen/arch/ppc/ppc64/asm-offsets.c index e69de29bb2..e1129cb0f4 100644 --- a/xen/arch/ppc/ppc64/asm-offsets.c +++ b/xen/arch/ppc/ppc64/asm-offsets.c @@ -0,0 +1,58 @@ +/* + * Generate definitions needed by assembly language modules. + * This code generates raw asm output which is post-processed + * to extract and format the required data. + */ + +#include +#include + +#define DEFINE(_sym, _val) \ + asm volatile ( "\n.ascii\"==>#define " #_sym " %0 /* " #_val " */<==\"" \ + : : "i" (_val) ) +#define BLANK() \ + asm volatile ( "\n.ascii\"==><==\"" : : ) +#define OFFSET(_sym, _str, _mem) \ + DEFINE(_sym, offsetof(_str, _mem)); + +/* base-2 logarithm */ +#define __L2(_x) (((_x) & 0x00000002) ? 1 : 0) +#define __L4(_x) (((_x) & 0x0000000c) ? ( 2 + __L2( (_x)>> 2)) : __L2( _x)) +#define __L8(_x) (((_x) & 0x000000f0) ? ( 4 + __L4( (_x)>> 4)) : __L4( _x)) +#define __L16(_x) (((_x) & 0x0000ff00) ? ( 8 + __L8( (_x)>> 8)) : __L8( _x)) +#define LOG_2(_x) (((_x) & 0xffff0000) ? (16 + __L16((_x)>>16)) : __L16(_x)) + +void __dummy__(void) +{ + BUILD_BUG_ON(!IS_ALIGNED(sizeof(struct cpu_user_regs), STACK_ALIGN)); + + DEFINE(GPR_WIDTH, sizeof(unsigned long)); + DEFINE(FPR_WIDTH, sizeof(double)); + + OFFSET(UREGS_gprs, struct cpu_user_regs, gprs); + OFFSET(UREGS_r0, struct cpu_user_regs, gprs[0]); + OFFSET(UREGS_r1, struct cpu_user_regs, gprs[1]); + OFFSET(UREGS_r13, struct cpu_user_regs, gprs[13]); + OFFSET(UREGS_srr0, struct cpu_user_regs, srr0); + OFFSET(UREGS_srr1, struct cpu_user_regs, srr1); + OFFSET(UREGS_pc, struct cpu_user_regs, pc); + OFFSET(UREGS_msr, struct cpu_user_regs, msr); + OFFSET(UREGS_lr, struct cpu_user_regs, lr); + OFFSET(UREGS_ctr, struct cpu_user_regs, ctr); + OFFSET(UREGS_xer, struct cpu_user_regs, xer); + OFFSET(UREGS_hid4, struct cpu_user_regs, hid4); + OFFSET(UREGS_dar, struct cpu_user_regs, dar); + OFFSET(UREGS_dsisr, struct cpu_user_regs, dsisr); + OFFSET(UREGS_cr, struct cpu_user_regs, cr); + OFFSET(UREGS_fpscr, struct cpu_user_regs, fpscr); + DEFINE(UREGS_sizeof, sizeof(struct cpu_user_regs)); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/ppc/ppc64/head.S b/xen/arch/ppc/ppc64/head.S index 49b3066396..02ff520458 100644 --- a/xen/arch/ppc/ppc64/head.S +++ b/xen/arch/ppc/ppc64/head.S @@ -18,6 +18,15 @@ ENTRY(start) li %r11, 0 stdu %r11, -STACK_FRAME_OVERHEAD(%r1) + /* clear .bss */ + LOAD_IMM32(%r14, __bss_start) + LOAD_IMM32(%r15, __bss_end) +1: + std %r11, 0(%r14) + addi %r14, %r14, 8 + cmpld %r14, %r15 + blt 1b + /* call the C entrypoint */ bl start_xen diff --git a/xen/arch/ppc/ppc64/of-call.S b/xen/arch/ppc/ppc64/of-call.S new file mode 100644 index 0000000000..2a2e308f6b --- /dev/null +++ b/xen/arch/ppc/ppc64/of-call.S @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Adapted from Linux's arch/powerpc/kernel/entry_64.S, with the + * following copyright notice: + * + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP + * Copyright (C) 1996 Cort Dougan + * Adapted for Power Macintosh by Paul Mackerras. + * Low-level exception handlers and MMU support + * rewritten by Paul Mackerras. + * Copyright (C) 1996 Paul Mackerras. + * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). + */ + +#include +#include +#include + +/* size of minimum stack frame that can hold an entire cpu_user_regs struct */ +#define STACK_SWITCH_FRAME_SIZE UREGS_sizeof + + .section .init.text, "ax", @progbits + +ENTRY(enter_of) + mflr %r0 + std %r0, 16(%r1) + stdu %r1, -STACK_SWITCH_FRAME_SIZE(%r1) /* Save SP and create stack space */ + + /* + * Because PROM is running in 32b mode, it clobbers the high order half + * of all registers that it saves. We therefore save those registers + * PROM might touch to the stack. (%r0, %r3-%r13 are caller saved) + */ + SAVE_GPR(2, %r1) + SAVE_GPR(13, %r1) + SAVE_NVGPRS(%r1) + mfcr %r10 + mfmsr %r11 + std %r10, UREGS_cr(%r1) + std %r11, UREGS_msr(%r1) + + /* Put PROM address in SRR0 */ + mtsrr0 %r4 + + /* Setup our trampoline return addr in LR */ + bcl 20, 31, .+4 +0: mflr %r4 + addi %r4, %r4, 1f - 0b + mtlr %r4 + + /* Prepare a 32-bit mode big endian MSR */ + LOAD_IMM64(%r12, MSR_SF | MSR_LE) + andc %r11, %r11, %r12 + mtsrr1 %r11 + rfid + +1: /* Return from OF */ + FIXUP_ENDIAN + + /* Just make sure that %r1 top 32 bits didn't get corrupt by OF */ + rldicl %r1, %r1, 0, 32 + + /* Restore the MSR (back to 64 bits) */ + ld %r0, UREGS_msr(%r1) + mtmsrd %r0 + isync + + /* Restore other registers */ + REST_GPR(2, %r1) + REST_GPR(13, %r1) + REST_NVGPRS(%r1) + ld %r4, UREGS_cr(%r1) + mtcr %r4 + + addi %r1, %r1, STACK_SWITCH_FRAME_SIZE + ld %r0, 16(%r1) + mtlr %r0 + blr + + .size enter_of, . - enter_of + .type enter_of, %function diff --git a/xen/arch/ppc/setup.c b/xen/arch/ppc/setup.c index 9e90a6179a..7c623a49f5 100644 --- a/xen/arch/ppc/setup.c +++ b/xen/arch/ppc/setup.c @@ -1,16 +1,29 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include +#include +#include /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] __aligned(STACK_SIZE); -/* Macro to adjust thread priority for hardware multithreading */ -#define HMT_very_low() asm volatile ( "or %r31, %r31, %r31" ) - void __init noreturn start_xen(unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7) { + if ( r5 ) + { + /* OpenFirmware boot protocol */ + boot_of_init(r5); + } + else + { + /* kexec boot: Unimplemented */ + __builtin_trap(); + } + + early_printk("Hello, ppc64le!\n"); + for ( ; ; ) /* Set current hardware thread to very low priority */ HMT_very_low(); From patchwork Fri Jul 21 17:02:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Anastasio X-Patchwork-Id: 13322389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DA0DEB64DC for ; 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a=rsa-sha256; c=relaxed/relaxed; d=raptorengineering.com; s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1689958988; bh=t2XSxlE4JcYvYurr+9ZptgwwCybbDwha+GFsOD84g3s=; h=From:To:Date:Message-Id:MIME-Version; b=HkptPHndv8brZtUT0MonN0Vk8eZkwp+Y2J6DlfOsvTzvPaAAZq+8IYcmrK8ByL/fb JqurN/Q8baZqQt6XQZz3szbNwCLYcoFN8jB2QO10mTucK7SwwkKeGtOjHDQO+i+QeJ YUhCNu/NMCYau+fDCrTxjXKdXxc5uKMDfRG8ZyPU= X-Virus-Scanned: amavisd-new at rptsys.com From: Shawn Anastasio To: xen-devel@lists.xenproject.org Cc: Timothy Pearson , Andrew Cooper , Jan Beulich , Julien Grall , Shawn Anastasio , Stefano Stabellini Subject: [PATCH v5 4/4] automation: Add smoke test for ppc64le Date: Fri, 21 Jul 2023 12:02:55 -0500 Message-Id: X-Mailer: git-send-email 2.30.2 In-Reply-To: References: MIME-Version: 1.0 Add an initial smoke test that boots xen on a ppc64/pseries machine and checks for a magic string. Based on the riscv smoke test. Eventually the powernv9 (POWER9 bare metal) machine type will want to be tested as well, but for now we only boot on pseries. Signed-off-by: Shawn Anastasio Reviewed-by: Stefano Stabellini Reviewed-by: Jiamei Xie Signed-off-by: Shawn Anastasio Reviewed-by: Stefano Stabellini Reviewed-by: Jiamei Xie > --- automation/gitlab-ci/test.yaml | 20 ++++++++++++++++++ automation/scripts/qemu-smoke-ppc64le.sh | 27 ++++++++++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100755 automation/scripts/qemu-smoke-ppc64le.sh diff --git a/automation/gitlab-ci/test.yaml b/automation/gitlab-ci/test.yaml index d5cb238b0a..45e8ddb7a3 100644 --- a/automation/gitlab-ci/test.yaml +++ b/automation/gitlab-ci/test.yaml @@ -71,6 +71,19 @@ tags: - x86_64 +.qemu-ppc64le: + extends: .test-jobs-common + variables: + CONTAINER: debian:bullseye-ppc64le + LOGFILE: qemu-smoke-ppc64le.log + artifacts: + paths: + - smoke.serial + - '*.log' + when: always + tags: + - x86_64 + .xilinx-arm64: extends: .test-jobs-common variables: @@ -444,3 +457,10 @@ qemu-smoke-riscv64-gcc: - ./automation/scripts/qemu-smoke-riscv64.sh 2>&1 | tee ${LOGFILE} needs: - archlinux-current-gcc-riscv64-debug + +qemu-smoke-ppc64le-pseries-gcc: + extends: .qemu-ppc64le + script: + - ./automation/scripts/qemu-smoke-ppc64le.sh pseries-5.2 2>&1 | tee ${LOGFILE} + needs: + - debian-bullseye-gcc-ppc64le-debug diff --git a/automation/scripts/qemu-smoke-ppc64le.sh b/automation/scripts/qemu-smoke-ppc64le.sh new file mode 100755 index 0000000000..eb55221221 --- /dev/null +++ b/automation/scripts/qemu-smoke-ppc64le.sh @@ -0,0 +1,27 @@ +#!/bin/bash + +set -ex + +# machine type from first arg passed directly to qemu -M +machine=$1 + +# Run the test +rm -f smoke.serial +set +e + +touch smoke.serial + +timeout -k 1 20 \ +qemu-system-ppc64 \ + -M $machine \ + -m 2g \ + -smp 1 \ + -vga none \ + -monitor none \ + -nographic \ + -serial file:smoke.serial \ + -kernel binaries/xen + +set -e +(grep -q "Hello, ppc64le!" smoke.serial) || exit 1 +exit 0