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Ignore the microcode loading interface in that case. Signed-off-by: Alejandro Vallejo Reviewed-by: Jan Beulich --- v6: * Change message content and move severity WARNING -> INFO (Andrew) NOTE: It has a convoluted argument to simplify the last patch, that uses the same printk() --- xen/arch/x86/cpu/microcode/core.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index bec8b55db2..71e3944cf2 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -867,10 +867,23 @@ int __init early_microcode_init(unsigned long *module_map, return -ENODEV; } - microcode_grab_module(module_map, mbi); - ucode_ops.collect_cpu_info(); + /* + * Some hypervisors deliberately report a microcode revision of -1 to + * mean that they will not accept microcode updates. We take the hint + * and ignore the microcode interface in that case. + */ + if ( this_cpu(cpu_sig).rev == ~0 ) + { + printk(XENLOG_INFO "Microcode loading disabled due to: %s", + "HW toggle"); + ucode_ops.apply_microcode = NULL; + return -ENODEV; + } + + microcode_grab_module(module_map, mbi); + if ( ucode_mod.mod_end || ucode_blob.size ) rc = early_microcode_update_cpu(); From patchwork Mon Jul 24 16:52:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13325022 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1EDEC0015E for ; Mon, 24 Jul 2023 16:52:55 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.569162.889457 (Exim 4.92) (envelope-from ) id 1qNynb-0000wI-In; Mon, 24 Jul 2023 16:52:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 569162.889457; Mon, 24 Jul 2023 16:52:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qNynb-0000w9-F9; Mon, 24 Jul 2023 16:52:43 +0000 Received: by outflank-mailman (input) for mailman id 569162; Mon, 24 Jul 2023 16:52:42 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qNyna-0000gc-8n for xen-devel@lists.xenproject.org; Mon, 24 Jul 2023 16:52:42 +0000 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [2a00:1450:4864:20::42d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 8007e9d6-2a42-11ee-8612-37d641c3527e; Mon, 24 Jul 2023 18:52:40 +0200 (CEST) Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3144bf65ce9so3489430f8f.3 for ; Mon, 24 Jul 2023 09:52:40 -0700 (PDT) Received: from EMEAENGAAD19049.citrite.net (default-46-102-197-194.interdsl.co.uk. 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Because microcode updates might make them that MSR to appear/have different values we also must reload it after a microcode update in early_microcode_init(). Signed-off-by: Alejandro Vallejo Reviewed-by: Jan Beulich --- v6: * Invert logic of a verbosity-guard to reduce diff (Jan) * Reflow last printk in v5/patch3:early_cpu_init() for line length (Jan) * Rewrite comment for the early_cpu_init(false) statement (Jan) --- xen/arch/x86/cpu/common.c | 20 +++++++++++++++----- xen/arch/x86/cpu/microcode/core.c | 9 +++++++++ xen/arch/x86/include/asm/setup.h | 2 +- xen/arch/x86/setup.c | 2 +- xen/arch/x86/tsx.c | 16 ++++------------ 5 files changed, 30 insertions(+), 19 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index cfcdaace12..2b9cc680ac 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -303,7 +303,7 @@ static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb) WARNING: this function is only called on the BP. Don't add code here that is supposed to run on all CPUs. */ -void __init early_cpu_init(void) +void __init early_cpu_init(bool verbose) { struct cpuinfo_x86 *c = &boot_cpu_data; u32 eax, ebx, ecx, edx; @@ -324,6 +324,8 @@ void __init early_cpu_init(void) case X86_VENDOR_SHANGHAI: this_cpu = &shanghai_cpu_dev; break; case X86_VENDOR_HYGON: this_cpu = &hygon_cpu_dev; break; default: + if (!verbose) + break; printk(XENLOG_ERR "Unrecognised or unsupported CPU vendor '%.12s'\n", c->x86_vendor_id); @@ -340,10 +342,13 @@ void __init early_cpu_init(void) c->x86_capability[FEATURESET_1d] = edx; c->x86_capability[FEATURESET_1c] = ecx; - printk(XENLOG_INFO - "CPU Vendor: %s, Family %u (%#x), Model %u (%#x), Stepping %u (raw %08x)\n", - x86_cpuid_vendor_to_str(c->x86_vendor), c->x86, c->x86, - c->x86_model, c->x86_model, c->x86_mask, eax); + if (verbose) + printk(XENLOG_INFO + "CPU Vendor: %s, Family %u (%#x), " + "Model %u (%#x), Stepping %u (raw %08x)\n", + x86_cpuid_vendor_to_str(c->x86_vendor), c->x86, + c->x86, c->x86_model, c->x86_model, c->x86_mask, + eax); if (c->cpuid_level >= 7) { uint32_t max_subleaf; @@ -352,6 +357,11 @@ void __init early_cpu_init(void) &c->x86_capability[FEATURESET_7c0], &c->x86_capability[FEATURESET_7d0]); + if (test_bit(X86_FEATURE_ARCH_CAPS, c->x86_capability)) + rdmsr(MSR_ARCH_CAPABILITIES, + c->x86_capability[FEATURESET_m10Al], + c->x86_capability[FEATURESET_m10Ah]); + if (max_subleaf >= 1) cpuid_count(7, 1, &eax, &ebx, &ecx, &c->x86_capability[FEATURESET_7d1]); diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index 71e3944cf2..44bc0fafa3 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -887,5 +887,14 @@ int __init early_microcode_init(unsigned long *module_map, if ( ucode_mod.mod_end || ucode_blob.size ) rc = early_microcode_update_cpu(); + /* + * Some CPUID leaves and MSRs are only present after microcode updates + * on some processors. We take the chance here to make sure what little + * state we have already probed is re-probed in order to ensure we do + * not use stale values. tsx_init() in particular needs to have up to + * date MSR_ARCH_CAPS. + */ + early_cpu_init(false); + return rc; } diff --git a/xen/arch/x86/include/asm/setup.h b/xen/arch/x86/include/asm/setup.h index ae0dd3915a..df59a4cd28 100644 --- a/xen/arch/x86/include/asm/setup.h +++ b/xen/arch/x86/include/asm/setup.h @@ -15,7 +15,7 @@ extern uint64_t boot_tsc_stamp; extern void *stack_start; -void early_cpu_init(void); +void early_cpu_init(bool verbose); void early_time_init(void); void set_nr_cpu_ids(unsigned int max_cpus); diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 74e3915a4d..bdf66e80ac 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -1211,7 +1211,7 @@ void __init noreturn __start_xen(unsigned long mbi_p) panic("Bootloader provided no memory information\n"); /* This must come before e820 code because it sets paddr_bits. */ - early_cpu_init(); + early_cpu_init(true); /* Choose shadow stack early, to set infrastructure up appropriately. */ if ( !boot_cpu_has(X86_FEATURE_CET_SS) ) diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c index 80c6f4cedd..50d8059f23 100644 --- a/xen/arch/x86/tsx.c +++ b/xen/arch/x86/tsx.c @@ -39,9 +39,10 @@ void tsx_init(void) static bool __read_mostly once; /* - * This function is first called between microcode being loaded, and CPUID - * being scanned generally. Read into boot_cpu_data.x86_capability[] for - * the cpu_has_* bits we care about using here. + * This function is first called between microcode being loaded, and + * CPUID being scanned generally. early_cpu_init() has already prepared + * the feature bits needed here. And early_microcode_init() has ensured + * they are not stale after the microcode update. */ if ( unlikely(!once) ) { @@ -49,15 +50,6 @@ void tsx_init(void) once = true; - if ( boot_cpu_data.cpuid_level >= 7 ) - boot_cpu_data.x86_capability[FEATURESET_7d0] - = cpuid_count_edx(7, 0); - - if ( cpu_has_arch_caps ) - rdmsr(MSR_ARCH_CAPABILITIES, - boot_cpu_data.x86_capability[FEATURESET_m10Al], - boot_cpu_data.x86_capability[FEATURESET_m10Ah]); - has_rtm_always_abort = cpu_has_rtm_always_abort; if ( cpu_has_tsx_ctrl && cpu_has_srbds_ctrl ) From patchwork Mon Jul 24 16:52:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13325023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89494C001DF for ; Mon, 24 Jul 2023 16:53:03 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.569163.889467 (Exim 4.92) (envelope-from ) id 1qNync-0001CH-PI; Mon, 24 Jul 2023 16:52:44 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 569163.889467; Mon, 24 Jul 2023 16:52:44 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qNync-0001C6-Lr; Mon, 24 Jul 2023 16:52:44 +0000 Received: by outflank-mailman (input) for mailman id 569163; Mon, 24 Jul 2023 16:52:42 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1qNyna-0000gc-Ty for xen-devel@lists.xenproject.org; Mon, 24 Jul 2023 16:52:42 +0000 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [2a00:1450:4864:20::42d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 8077ee23-2a42-11ee-8612-37d641c3527e; Mon, 24 Jul 2023 18:52:40 +0200 (CEST) Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-31758eb5db8so1531798f8f.2 for ; Mon, 24 Jul 2023 09:52:40 -0700 (PDT) Received: from EMEAENGAAD19049.citrite.net (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id x13-20020a5d60cd000000b0030ada01ca78sm13480777wrt.10.2023.07.24.09.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 09:52:39 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 8077ee23-2a42-11ee-8612-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1690217560; x=1690822360; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FQrfrX/9YiZ+DtYGqTJdty4w9Ag9CCl3bmUTiKKBqx4=; b=NleyQ1Kylc04W1xqGCWqUrYVCY060mcMc97m19FGOqMDCkwr5Lal13M+XnJSv3v+0J YyDVLE5OSkdWKJxFrRXhoH+fleYHOO+T+OQRbW5C2YP9Z1uQ4U24Br6/r2U8a1ItW2s3 Nm3QE8qXMPwwspb2sYXZGc8ayB6FPWVgRECQU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690217560; x=1690822360; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FQrfrX/9YiZ+DtYGqTJdty4w9Ag9CCl3bmUTiKKBqx4=; b=aUhgIJ9PhaOD1l/RaBzoeD2XYmxhwAJOb5lGZrCLRtY+xLF2ST2DsswcH946P0rSHU It18urNp8CJQXGg72RRbnYLsI6Ee+tTGWeM+zWtHYhqItvZ2fN87/X6RlzQ7dzLzplJB djW877Oigd5luDLnhZ+4M5bNtpoz4qkNpKZc5RC8LXB8Ql0b5ccO/VgBjHGNr96fCNdI lMTtun229AmlfZfTJoRJZ1DJAd8hEAIEvm7JGHpdF3vIdIzcYKAcvBv00TQk8C/e/vac KdxtjY6c+njRDDhTGeAmHy1zIsa8z3RjKxEwr1Bw1GBHDvQQkXbzddBrB+DyumJKzJX6 KwNw== X-Gm-Message-State: ABy/qLZ55SeULu+MtsvBx9yRAJAm6v9V8IdWFHnCXwk+F0XiBaI+ub/W YlzlmvvXAeG9BXJncNrLt7UDao0ZdT6RiVnWTtY= X-Google-Smtp-Source: APBJJlFAXSaZiAeePI7MIQoas4MEobXA1tZgPfr4bR2vIkOy4g/E9EDAEk5wNZTEIxctc74TN6fXxQ== X-Received: by 2002:adf:f5ce:0:b0:314:11f3:ca94 with SMTP id k14-20020adff5ce000000b0031411f3ca94mr8194166wrp.41.1690217560130; Mon, 24 Jul 2023 09:52:40 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH v6 3/3] x86/microcode: Disable microcode update handler if DIS_MCU_UPDATE is set Date: Mon, 24 Jul 2023 17:52:35 +0100 Message-Id: <20230724165235.25262-4-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230724165235.25262-1-alejandro.vallejo@cloud.com> References: <20230724165235.25262-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 If IA32_MSR_MCU_CONTROL exists then it's possible a CPU may be unable to perform microcode updates. This is controlled through the DIS_MCU_LOAD bit and is intended for baremetal clouds where the owner may not trust the tenant to choose the microcode version in use. If we notice that bit being set then simply disable the "apply_microcode" handler so we can't even try to perform update (as it's known to be silently dropped). While at it, remove the Intel family check, as microcode loading is supported on every Intel64 CPU. Signed-off-by: Alejandro Vallejo Reviewed-by: Jan Beulich --- v6: * Amended early exit comment to cover both !can_load and rev=~0 (Jan) --- xen/arch/x86/cpu/microcode/core.c | 20 ++++++++++++++------ xen/arch/x86/cpu/microcode/intel.c | 13 +++++++++++++ xen/arch/x86/cpu/microcode/private.h | 7 +++++++ xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/include/asm/msr-index.h | 5 +++++ 5 files changed, 40 insertions(+), 6 deletions(-) diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode/core.c index 44bc0fafa3..ec921f5b77 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -847,17 +847,21 @@ int __init early_microcode_init(unsigned long *module_map, { const struct cpuinfo_x86 *c = &boot_cpu_data; int rc = 0; + bool can_load = false; switch ( c->x86_vendor ) { case X86_VENDOR_AMD: if ( c->x86 >= 0x10 ) + { ucode_ops = amd_ucode_ops; + can_load = true; + } break; case X86_VENDOR_INTEL: - if ( c->x86 >= 6 ) - ucode_ops = intel_ucode_ops; + ucode_ops = intel_ucode_ops; + can_load = intel_can_load_microcode(); break; } @@ -871,13 +875,17 @@ int __init early_microcode_init(unsigned long *module_map, /* * Some hypervisors deliberately report a microcode revision of -1 to - * mean that they will not accept microcode updates. We take the hint - * and ignore the microcode interface in that case. + * mean that they will not accept microcode updates. + * + * It's also possible the hardware might have built-in support to disable + * updates and someone (e.g: a baremetal cloud provider) disabled them. + * + * Take the hint in either case and ignore the microcode interface. */ - if ( this_cpu(cpu_sig).rev == ~0 ) + if ( this_cpu(cpu_sig).rev == ~0 || !can_load ) { printk(XENLOG_INFO "Microcode loading disabled due to: %s", - "HW toggle"); + can_load ? "rev = ~0" : "HW toggle"); ucode_ops.apply_microcode = NULL; return -ENODEV; } diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcode/intel.c index 8d4d6574aa..060c529a6e 100644 --- a/xen/arch/x86/cpu/microcode/intel.c +++ b/xen/arch/x86/cpu/microcode/intel.c @@ -385,6 +385,19 @@ static struct microcode_patch *cf_check cpu_request_microcode( return patch; } +bool __init intel_can_load_microcode(void) +{ + uint64_t mcu_ctrl; + + if ( !cpu_has_mcu_ctrl ) + return true; + + rdmsrl(MSR_MCU_CONTROL, mcu_ctrl); + + /* If DIS_MCU_LOAD is set applying microcode updates won't work */ + return !(mcu_ctrl & MCU_CONTROL_DIS_MCU_LOAD); +} + const struct microcode_ops __initconst_cf_clobber intel_ucode_ops = { .cpu_request_microcode = cpu_request_microcode, .collect_cpu_info = collect_cpu_info, diff --git a/xen/arch/x86/cpu/microcode/private.h b/xen/arch/x86/cpu/microcode/private.h index 626aeb4d08..d80787205a 100644 --- a/xen/arch/x86/cpu/microcode/private.h +++ b/xen/arch/x86/cpu/microcode/private.h @@ -60,6 +60,13 @@ struct microcode_ops { const struct microcode_patch *new, const struct microcode_patch *old); }; +/** + * Checks whether we can perform microcode updates on this Intel system + * + * @return True iff the microcode update facilities are enabled + */ +bool intel_can_load_microcode(void); + extern const struct microcode_ops amd_ucode_ops, intel_ucode_ops; #endif /* ASM_X86_MICROCODE_PRIVATE_H */ diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index 64e1dad225..5422baed27 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -193,6 +193,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_if_pschange_mc_no boot_cpu_has(X86_FEATURE_IF_PSCHANGE_MC_NO) #define cpu_has_tsx_ctrl boot_cpu_has(X86_FEATURE_TSX_CTRL) #define cpu_has_taa_no boot_cpu_has(X86_FEATURE_TAA_NO) +#define cpu_has_mcu_ctrl boot_cpu_has(X86_FEATURE_MCU_CTRL) #define cpu_has_fb_clear boot_cpu_has(X86_FEATURE_FB_CLEAR) #define cpu_has_rrsba boot_cpu_has(X86_FEATURE_RRSBA) diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 2382fc8e11..a5f730e9a6 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -165,6 +165,11 @@ #define PASID_PASID_MASK 0x000fffff #define PASID_VALID (_AC(1, ULL) << 31) +#define MSR_MCU_CONTROL 0x00001406 +#define MCU_CONTROL_LOCK (_AC(1, ULL) << 0) +#define MCU_CONTROL_DIS_MCU_LOAD (_AC(1, ULL) << 1) +#define MCU_CONTROL_EN_SMM_BYPASS (_AC(1, ULL) << 2) + #define MSR_UARCH_MISC_CTRL 0x00001b01 #define UARCH_CTRL_DOITM (_AC(1, ULL) << 0)