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[92.145.124.62]) by smtp.gmail.com with ESMTPSA id a17-20020adffad1000000b003143cdc5949sm16619297wrs.9.2023.07.25.07.19.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 07:19:27 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Andrew Jones , Conor Dooley , Sunil V L , Song Shuai , Randy Dunlap , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , Atish Patra Subject: [PATCH v6 1/3] Documentation: arm: Add bootargs to the table of added DT parameters Date: Tue, 25 Jul 2023 16:19:23 +0200 Message-Id: <20230725141926.823153-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230725_071929_745271_B5785AFE X-CRM114-Status: GOOD ( 11.32 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The bootargs node is also added by the EFI stub in the function update_fdt(), so add it to the table. Signed-off-by: Alexandre Ghiti Reviewed-by: Atish Patra Reviewed-by: Song Shuai --- - Changes in v5: * Rebase on top of docs-next Documentation/arch/arm/uefi.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/arm/uefi.rst b/Documentation/arch/arm/uefi.rst index baebe688a006..2b7ad9bd7cd2 100644 --- a/Documentation/arch/arm/uefi.rst +++ b/Documentation/arch/arm/uefi.rst @@ -50,7 +50,7 @@ The stub populates the FDT /chosen node with (and the kernel scans for) the following parameters: ========================== ====== =========================================== -Name Size Description +Name Type Description ========================== ====== =========================================== linux,uefi-system-table 64-bit Physical address of the UEFI System Table. @@ -67,4 +67,6 @@ linux,uefi-mmap-desc-ver 32-bit Version of the mmap descriptor format. kaslr-seed 64-bit Entropy used to randomize the kernel image base address location. + +bootargs String Kernel command line ========================== ====== =========================================== From patchwork Tue Jul 25 14:19:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13326543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95ED1C04A6A for ; Tue, 25 Jul 2023 14:20:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+TvddpYSPyWaRbsEkICFHdhOrH4R6V4nwslUB5PBc4A=; b=blJldl4S85J1n8 ldr89IcajC9SMNYLkUDQXFd90jJD8N3AmuVIQUVAeiPL09Gj3FqSOYxqI5KDP0zLWFK6Z8siLHzZO pJv7wXHQ/ADmw9sQInxudJm1xZiChOfZrBr+4ZI2E143RG6d1Z2i9wILoczOnkjsbTmhAdfeOORgh oe4QA+Brg01v7i/HzWsq6466TEINrzNRpWE7Es/HFS/KXHA1KGIcOD6qynqUZ//N7YU83EwMLQumk hMQaDj+DdZXMFIHxclSdLptdiqTUMPpQd2iC6yJ3DZ6b2mrvcR40IotGEabQY0sFz0FoADoltDMeU +y3LSGyisMEgGSHc1Xig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qOItu-007lC4-1x; Tue, 25 Jul 2023 14:20:34 +0000 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qOItq-007lBB-39 for linux-riscv@lists.infradead.org; Tue, 25 Jul 2023 14:20:33 +0000 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-3fd18b1d924so45062095e9.1 for ; Tue, 25 Jul 2023 07:20:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1690294829; x=1690899629; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mUodzhlLwEwB2djl1U2rjOpAikIdHhx+oYCvR61PqC4=; b=suaL+YrsHfcpXbglKhoc3vymRL7nIn9HvfdnNG7WiJyYsYofcKfkttXITApULM2WFX ioWIkfw1ypUT+Sc912rUwODgBJbVFIUUICivfoK8qeszPBVQvtXacxJkcTvZ9RWsLvWA 2dKRld2twMsS+HkBRy9t0P5TwvjNzS3cqnfsXuJOFOylFI6Lvwk6ydbpIqDAaXMSfANI GeYwuulWHKf7kp+Nn/lwrI96pmX5KqxFvNt12wDu2Cmbb5+KyNRabzYoYZ2HJwSnec3n eQeRFRDRSoN8cku+POELKaVW3HXNBydZZ5mjj6Y9sQp7T4EtRYt0DN54CklqvwOoQRhQ oOrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690294829; x=1690899629; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mUodzhlLwEwB2djl1U2rjOpAikIdHhx+oYCvR61PqC4=; b=j7AfxtCAu94wzSZKw3bZ9em3yKkvdJCVoyY0dSqXBweJGzpiRWL+/FlOQ4q0wtyhz0 kTfYypkn0qkasM5DYo79IU5PAKKIufTaHyUnQ5zGbaijdHXq8umlCK45I6RLO3i6dZHe i132Kn4KE8Tg6LhfXLTpz3EAP3OSITfxRuJx0RoX9q3I65yOIBztMrSFqtFurcU/yx72 Eonef6MRDPxMg7wlKzefJb1X06pKsxW2bLwkaLpkjp1RPSaeWTtiR+mtnq5sVpk0tBTS hcyyriQRIAigoWlq1HM0ddkiejMjdSN09VUtLOXMcGcnCbTiWaGilE64QshsSEwv4cN6 4VUA== X-Gm-Message-State: ABy/qLb8tINXENQOhv52gNzMfdIoUqGV/sTROGdSSarcoLejYiplaVmo dYppmTAjYaslyo+EjVj7bIIBlg== X-Google-Smtp-Source: APBJJlESBSkEPLezf0y6Mhb82quzoueYP2L7j64pcs/m9IaEzVeVS2E5/xUswQEKA4FcbtsC9Kf+IA== X-Received: by 2002:a05:6000:14a:b0:314:2ba3:15dd with SMTP id r10-20020a056000014a00b003142ba315ddmr8734316wrx.16.1690294828754; Tue, 25 Jul 2023 07:20:28 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id p24-20020a1c7418000000b003fc07e17d4esm15878272wmc.2.2023.07.25.07.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 07:20:28 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Andrew Jones , Conor Dooley , Sunil V L , Song Shuai , Randy Dunlap , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , Palmer Dabbelt , Atish Patra Subject: [PATCH v6 2/3] Documentation: riscv: Add early boot document Date: Tue, 25 Jul 2023 16:19:24 +0200 Message-Id: <20230725141926.823153-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230725141926.823153-1-alexghiti@rivosinc.com> References: <20230725141926.823153-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230725_072031_013661_3CEE7E8F X-CRM114-Status: GOOD ( 33.57 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This document describes the constraints and requirements of the early boot process in a RISC-V kernel. Signed-off-by: Alexandre Ghiti Reviewed-by: Björn Töpel Reviewed-by: Conor Dooley Reviewed-by: Sunil V L Reviewed-by: Andrew Jones Reviewed-by: Palmer Dabbelt Reviewed-by: Atish Patra Reviewed-by: Song Shuai Reviewed-by: Randy Dunlap Acked-by: Palmer Dabbelt --- Changes in v6: * s/cpu/CPU as suggested by Randy * s/but/and as suggested by Randy * s/entrance/entry as suggested by Randy Changes in v5: * Rebase on top of docs-next Documentation/riscv/boot-image-header.rst | 3 - Documentation/riscv/boot.rst | 169 ++++++++++++++++++++++ Documentation/riscv/index.rst | 1 + 3 files changed, 170 insertions(+), 3 deletions(-) create mode 100644 Documentation/riscv/boot.rst diff --git a/Documentation/riscv/boot-image-header.rst b/Documentation/riscv/boot-image-header.rst index d7752533865f..a4a45310c4c4 100644 --- a/Documentation/riscv/boot-image-header.rst +++ b/Documentation/riscv/boot-image-header.rst @@ -7,9 +7,6 @@ Boot image header in RISC-V Linux This document only describes the boot image header details for RISC-V Linux. -TODO: - Write a complete booting guide. - The following 64-byte header is present in decompressed Linux kernel image:: u32 code0; /* Executable code */ diff --git a/Documentation/riscv/boot.rst b/Documentation/riscv/boot.rst new file mode 100644 index 000000000000..205075e1dee2 --- /dev/null +++ b/Documentation/riscv/boot.rst @@ -0,0 +1,169 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=============================================== +RISC-V Kernel Boot Requirements and Constraints +=============================================== + +:Author: Alexandre Ghiti +:Date: 23 May 2023 + +This document describes what the RISC-V kernel expects from bootloaders and +firmware, and also the constraints that any developer must have in mind when +touching the early boot process. For the purposes of this document, the +``early boot process`` refers to any code that runs before the final virtual +mapping is set up. + +Pre-kernel Requirements and Constraints +======================================= + +The RISC-V kernel expects the following of bootloaders and platform firmware: + +Register state +-------------- + +The RISC-V kernel expects: + + * ``$a0`` to contain the hartid of the current core. + * ``$a1`` to contain the address of the devicetree in memory. + +CSR state +--------- + +The RISC-V kernel expects: + + * ``$satp = 0``: the MMU, if present, must be disabled. + +Reserved memory for resident firmware +------------------------------------- + +The RISC-V kernel must not map any resident memory, or memory protected with +PMPs, in the direct mapping, so the firmware must correctly mark those regions +as per the devicetree specification and/or the UEFI specification. + +Kernel location +--------------- + +The RISC-V kernel expects to be placed at a PMD boundary (2MB aligned for rv64 +and 4MB aligned for rv32). Note that the EFI stub will physically relocate the +kernel if that's not the case. + +Hardware description +-------------------- + +The firmware can pass either a devicetree or ACPI tables to the RISC-V kernel. + +The devicetree is either passed directly to the kernel from the previous stage +using the ``$a1`` register, or when booting with UEFI, it can be passed using the +EFI configuration table. + +The ACPI tables are passed to the kernel using the EFI configuration table. In +this case, a tiny devicetree is still created by the EFI stub. Please refer to +"EFI stub and devicetree" section below for details about this devicetree. + +Kernel entry +------------ + +On SMP systems, there are 2 methods to enter the kernel: + +- ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kernel, one hart + wins a lottery and executes the early boot code while the other harts are + parked waiting for the initialization to finish. This method is mostly used to + support older firmwares without SBI HSM extension and M-mode RISC-V kernel. +- ``Ordered booting``: the firmware releases only one hart that will execute the + initialization phase and then will start all other harts using the SBI HSM + extension. The ordered booting method is the preferred booting method for + booting the RISC-V kernel because it can support CPU hotplug and kexec. + +UEFI +---- + +UEFI memory map +~~~~~~~~~~~~~~~ + +When booting with UEFI, the RISC-V kernel will use only the EFI memory map to +populate the system memory. + +The UEFI firmware must parse the subnodes of the ``/reserved-memory`` devicetree +node and abide by the devicetree specification to convert the attributes of +those subnodes (``no-map`` and ``reusable``) into their correct EFI equivalent +(refer to section "3.5.4 /reserved-memory and UEFI" of the devicetree +specification v0.4-rc1). + +RISCV_EFI_BOOT_PROTOCOL +~~~~~~~~~~~~~~~~~~~~~~~ + +When booting with UEFI, the EFI stub requires the boot hartid in order to pass +it to the RISC-V kernel in ``$a1``. The EFI stub retrieves the boot hartid using +one of the following methods: + +- ``RISCV_EFI_BOOT_PROTOCOL`` (**preferred**). +- ``boot-hartid`` devicetree subnode (**deprecated**). + +Any new firmware must implement ``RISCV_EFI_BOOT_PROTOCOL`` as the devicetree +based approach is deprecated now. + +Early Boot Requirements and Constraints +======================================= + +The RISC-V kernel's early boot process operates under the following constraints: + +EFI stub and devicetree +----------------------- + +When booting with UEFI, the devicetree is supplemented (or created) by the EFI +stub with the same parameters as arm64 which are described at the paragraph +"UEFI kernel support on ARM" in Documentation/arm/uefi.rst. + +Virtual mapping installation +---------------------------- + +The installation of the virtual mapping is done in 2 steps in the RISC-V kernel: + +1. ``setup_vm()`` installs a temporary kernel mapping in ``early_pg_dir`` which + allows discovery of the system memory. Only the kernel text/data are mapped + at this point. When establishing this mapping, no allocation can be done + (since the system memory is not known yet), so ``early_pg_dir`` page table is + statically allocated (using only one table for each level). + +2. ``setup_vm_final()`` creates the final kernel mapping in ``swapper_pg_dir`` + and takes advantage of the discovered system memory to create the linear + mapping. When establishing this mapping, the kernel can allocate memory but + cannot access it directly (since the direct mapping is not present yet), so + it uses temporary mappings in the fixmap region to be able to access the + newly allocated page table levels. + +For ``virt_to_phys()`` and ``phys_to_virt()`` to be able to correctly convert +direct mapping addresses to physical addresses, they need to know the start of +the DRAM. This happens after step 1, right before step 2 installs the direct +mapping (see ``setup_bootmem()`` function in arch/riscv/mm/init.c). Any usage of +those macros before the final virtual mapping is installed must be carefully +examined. + +Devicetree mapping via fixmap +----------------------------- + +As the ``reserved_mem`` array is initialized with virtual addresses established +by ``setup_vm()``, and used with the mapping established by +``setup_vm_final()``, the RISC-V kernel uses the fixmap region to map the +devicetree. This ensures that the devicetree remains accessible by both virtual +mappings. + +Pre-MMU execution +----------------- + +A few pieces of code need to run before even the first virtual mapping is +established. These are the installation of the first virtual mapping itself, +patching of early alternatives and the early parsing of the kernel command line. +That code must be very carefully compiled as: + +- ``-fno-pie``: This is needed for relocatable kernels which use ``-fPIE``, + since otherwise, any access to a global symbol would go through the GOT which + is only relocated virtually. +- ``-mcmodel=medany``: Any access to a global symbol must be PC-relative to + avoid any relocations to happen before the MMU is setup. +- *all* instrumentation must also be disabled (that includes KASAN, ftrace and + others). + +As using a symbol from a different compilation unit requires this unit to be +compiled with those flags, we advise, as much as possible, not to use external +symbols. diff --git a/Documentation/riscv/index.rst b/Documentation/riscv/index.rst index 81cf6e616476..4dab0cb4b900 100644 --- a/Documentation/riscv/index.rst +++ b/Documentation/riscv/index.rst @@ -6,6 +6,7 @@ RISC-V architecture :maxdepth: 1 acpi + boot boot-image-header vm-layout hwprobe From patchwork Tue Jul 25 14:19:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Ghiti X-Patchwork-Id: 13326544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91456C001DE for ; Tue, 25 Jul 2023 14:21:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=06WAkuaTXkrRQbXW+hpIQcNMHfBCccz0ctxRdrTZ6b0=; b=IZd2u+D5MyIQUO 0ypv9FtBAGI5wqMCoPVbcE2dozyR3SJo9WlqPnIhNApmfbpkMbjOJjtMij9tzpqpABZ3AWdGH0Uy9 nzQLjCGuwRmON7A8Ou3ZmvdnZWIrkDrOb82Dp4suEWyoaTMTuHnF5JUKVW2unjDhODp0rItVUPaNL LdFpryes7sdf6Orh083aOUjTR1PxVAno3O67xevyN569oI5ZYmnheTLDGRre0MQ75p8bIdNx2aBQg YDebwJGqU0MbkgTvZ4goG7PmMtw9PjDkNuMYQeNrHgUe5ibHQDxuPbTiDY7A/tBI53/tuLcdTu5l9 Uu+jCE0d/ZE0Z/YKF+Ng==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qOIus-007lQn-2G; Tue, 25 Jul 2023 14:21:34 +0000 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qOIuq-007lQ0-01 for linux-riscv@lists.infradead.org; Tue, 25 Jul 2023 14:21:33 +0000 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3175d5ca8dbso2032120f8f.2 for ; Tue, 25 Jul 2023 07:21:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1690294890; x=1690899690; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+UwYYe6ucZvdBvqF8iQhg0hDnshi1xav4hUdpbdxiqw=; b=WbIR7n/yzc9VAozw8Sk+VSB2504MVtOdu1vnFMj5noYjek5szstVImCB0Qp6a7sqFz Gz1gOgq/xvFNwR6NQej4DgG6nd0XEbv7N3vBqNr4x74ijnVGuP6dp2xAnyb09iyks1TD U3hriTLler5E7fm9b3s9X5Pv4EUZBMV+gFxGRvGwNfHZyV9OSzwvCZH1U0E6XOZvuUqY p07D4iEfPMttDvKhK+zGj8L1eAcWLj/Q3iN5wQ36akJ38bS8XiId2FJF9QSZk+K+/BxR fR8/8EV1BgMPvCEA5uZCfxHxHjuyY1xOUxXk1NtodoYq/XT1SGJTBfJWvqEg23Om2VK+ P3Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690294890; x=1690899690; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+UwYYe6ucZvdBvqF8iQhg0hDnshi1xav4hUdpbdxiqw=; b=WIZZ6MitJ4NdaG1IRNp3w2iUDFMurIgyxTxeR8jkSqWa/2u9aC4y9wDQDgQc1n3JgT HZaP64jOaaPqHPsFnfB2tMPcQT5sBXeYO+9zd8CdBSQAcAXMul5w0XnZkgMVDfEiMsih /e+anFEhuljG1BZ1UhCJv7dprEKnKVAr1GediSU58GI2OKB8LYFznPLmn2Yef6E7E4um kj9lIDnnFGJG6wNU5fRmG0VzaV5sBfazWRQ1HTPIaEDxsHfttDsf6JF0kJKzxNzVcuBB vibWrT6Uc7zmfKI4Gcf3liVTeqIU/oX/Ahcq3WNkVxE3OmpGZwd7FpwxSm8OvDusnF1M RldQ== X-Gm-Message-State: ABy/qLa1G+G7q/6UdwvU/QeESMsdLqYhYFUT3JMWp3bS64D4h04yJPRM eBQDwkGmPg0wmdgZExqqZX5Knw== X-Google-Smtp-Source: APBJJlHTPdf8WSeLzfqvdw+Iv3zNCwUMRolvKBj5Y5BArZHknPJjzTL9f7IYaGzso0TGmRYunEA55Q== X-Received: by 2002:a5d:45c1:0:b0:313:ee5b:d4bc with SMTP id b1-20020a5d45c1000000b00313ee5bd4bcmr9304252wrs.5.1690294889769; Tue, 25 Jul 2023 07:21:29 -0700 (PDT) Received: from alex-rivos.ba.rivosinc.com (amontpellier-656-1-456-62.w92-145.abo.wanadoo.fr. [92.145.124.62]) by smtp.gmail.com with ESMTPSA id x10-20020adff0ca000000b00314367cf43asm16503568wro.106.2023.07.25.07.21.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jul 2023 07:21:29 -0700 (PDT) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Andrew Jones , Conor Dooley , Sunil V L , Song Shuai , Randy Dunlap , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti , Atish Patra , Palmer Dabbelt Subject: [PATCH v6 3/3] Documentation: riscv: Update boot image header since EFI stub is supported Date: Tue, 25 Jul 2023 16:19:25 +0200 Message-Id: <20230725141926.823153-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230725141926.823153-1-alexghiti@rivosinc.com> References: <20230725141926.823153-1-alexghiti@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230725_072132_040133_FCF3F20C X-CRM114-Status: GOOD ( 15.35 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The EFI stub is supported on RISC-V so update the documentation that explains how the boot image header was reused to support it. Signed-off-by: Alexandre Ghiti Reviewed-by: Atish Patra Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt --- - Changes in v5: * Rebase on top of docs-next Documentation/riscv/boot-image-header.rst | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/riscv/boot-image-header.rst b/Documentation/riscv/boot-image-header.rst index a4a45310c4c4..df2ffc173e80 100644 --- a/Documentation/riscv/boot-image-header.rst +++ b/Documentation/riscv/boot-image-header.rst @@ -28,11 +28,11 @@ header in future. Notes ===== -- This header can also be reused to support EFI stub for RISC-V in future. EFI - specification needs PE/COFF image header in the beginning of the kernel image - in order to load it as an EFI application. In order to support EFI stub, - code0 should be replaced with "MZ" magic string and res3(at offset 0x3c) should - point to the rest of the PE/COFF header. +- This header is also reused to support EFI stub for RISC-V. EFI specification + needs PE/COFF image header in the beginning of the kernel image in order to + load it as an EFI application. In order to support EFI stub, code0 is replaced + with "MZ" magic string and res3(at offset 0x3c) points to the rest of the + PE/COFF header. - version field indicate header version number