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No functional change intended. Signed-off-by: Roger Pau Monné Acked-by: Jan Beulich --- Changes since v1: - Fix initializers. --- Tested on gitlab CI, builds on all compilers used there. --- xen/arch/x86/include/asm/io_apic.h | 57 +++++++++++++----------- xen/arch/x86/io_apic.c | 2 +- xen/drivers/passthrough/amd/iommu_intr.c | 4 +- xen/drivers/passthrough/vtd/intremap.c | 4 +- 4 files changed, 35 insertions(+), 32 deletions(-) diff --git a/xen/arch/x86/include/asm/io_apic.h b/xen/arch/x86/include/asm/io_apic.h index bd8cb95f46b1..4c4777b68a51 100644 --- a/xen/arch/x86/include/asm/io_apic.h +++ b/xen/arch/x86/include/asm/io_apic.h @@ -90,35 +90,38 @@ enum ioapic_irq_destination_types { }; struct IO_APIC_route_entry { - unsigned int vector:8; - unsigned int delivery_mode:3; /* - * 000: FIXED - * 001: lowest prio - * 111: ExtINT - */ - unsigned int dest_mode:1; /* 0: physical, 1: logical */ - unsigned int delivery_status:1; - unsigned int polarity:1; /* 0: low, 1: high */ - unsigned int irr:1; - unsigned int trigger:1; /* 0: edge, 1: level */ - unsigned int mask:1; /* 0: enabled, 1: disabled */ - unsigned int __reserved_2:15; - union { struct { - unsigned int __reserved_1:24; - unsigned int physical_dest:4; - unsigned int __reserved_2:4; - } physical; - - struct { - unsigned int __reserved_1:24; - unsigned int logical_dest:8; - } logical; - - /* used when Interrupt Remapping with EIM is enabled */ - unsigned int dest32; - } dest; + unsigned int vector:8; + unsigned int delivery_mode:3; /* + * 000: FIXED + * 001: lowest prio + * 111: ExtINT + */ + unsigned int dest_mode:1; /* 0: physical, 1: logical */ + unsigned int delivery_status:1; + unsigned int polarity:1; /* 0: low, 1: high */ + unsigned int irr:1; + unsigned int trigger:1; /* 0: edge, 1: level */ + unsigned int mask:1; /* 0: enabled, 1: disabled */ + unsigned int __reserved_2:15; + + union { + struct { + unsigned int __reserved_1:24; + unsigned int physical_dest:4; + unsigned int __reserved_2:4; + } physical; + + struct { + unsigned int __reserved_1:24; + unsigned int logical_dest:8; + } logical; + unsigned int dest32; + } dest; + }; + uint64_t raw; + }; }; /* diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c index 25a08b1ea6c6..aada2ef96c62 100644 --- a/xen/arch/x86/io_apic.c +++ b/xen/arch/x86/io_apic.c @@ -2360,7 +2360,7 @@ int ioapic_guest_read(unsigned long physbase, unsigned int reg, u32 *pval) int ioapic_guest_write(unsigned long physbase, unsigned int reg, u32 val) { int apic, pin, irq, ret, pirq; - struct IO_APIC_route_entry rte = { 0 }; + struct IO_APIC_route_entry rte = { }; unsigned long flags; struct irq_desc *desc; diff --git a/xen/drivers/passthrough/amd/iommu_intr.c b/xen/drivers/passthrough/amd/iommu_intr.c index f4de09f43180..9e6be3be3515 100644 --- a/xen/drivers/passthrough/amd/iommu_intr.c +++ b/xen/drivers/passthrough/amd/iommu_intr.c @@ -352,8 +352,8 @@ static int update_intremap_entry_from_ioapic( void cf_check amd_iommu_ioapic_update_ire( unsigned int apic, unsigned int reg, unsigned int value) { - struct IO_APIC_route_entry old_rte = { 0 }; - struct IO_APIC_route_entry new_rte = { 0 }; + struct IO_APIC_route_entry old_rte = { }; + struct IO_APIC_route_entry new_rte = { }; unsigned int rte_lo = (reg & 1) ? reg - 1 : reg; unsigned int pin = (reg - 0x10) / 2; int seg, bdf, rc; diff --git a/xen/drivers/passthrough/vtd/intremap.c b/xen/drivers/passthrough/vtd/intremap.c index b39bc832821a..786388b4d9c7 100644 --- a/xen/drivers/passthrough/vtd/intremap.c +++ b/xen/drivers/passthrough/vtd/intremap.c @@ -419,7 +419,7 @@ unsigned int cf_check io_apic_read_remap_rte( { unsigned int ioapic_pin = (reg - 0x10) / 2; int index; - struct IO_xAPIC_route_entry old_rte = { 0 }; + struct IO_xAPIC_route_entry old_rte = { }; int rte_upper = (reg & 1) ? 1 : 0; struct vtd_iommu *iommu = ioapic_to_iommu(IO_APIC_ID(apic)); @@ -442,7 +442,7 @@ void cf_check io_apic_write_remap_rte( unsigned int apic, unsigned int reg, unsigned int value) { unsigned int ioapic_pin = (reg - 0x10) / 2; - struct IO_xAPIC_route_entry old_rte = { 0 }; + struct IO_xAPIC_route_entry old_rte = { }; struct IO_APIC_route_remap_entry *remap_rte; unsigned int rte_upper = (reg & 1) ? 1 : 0; struct vtd_iommu *iommu = ioapic_to_iommu(IO_APIC_ID(apic)); From patchwork Wed Jul 26 12:55:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Roger_Pau_Monn=C3=A9?= X-Patchwork-Id: 13327985 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 236A6C001DC for ; Wed, 26 Jul 2023 12:55:58 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.570453.892238 (Exim 4.92) (envelope-from ) id 1qOe3K-0001lW-OE; Wed, 26 Jul 2023 12:55:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 570453.892238; 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This is in preparation for passing the full contents of the RTE to the IOMMU interrupt remapping handlers, so remapping entries for IO-APIC RTEs can be updated atomically when possible. While immediately this commit might expand the number of MMIO accesses in order to update an IO-APIC RTE, further changes will benefit from getting the full RTE value passed to the IOMMU handlers, as the logic is greatly simplified when the IOMMU handlers can get the complete RTE value in one go. Signed-off-by: Roger Pau Monné Reviewed-by: Jan Beulich --- Changes since v2: - Also adjust __ioapic_read_entry(). Changes since v1: - Reinstate io_apic_modify(). - Expand commit message. --- xen/arch/x86/include/asm/io_apic.h | 8 ++--- xen/arch/x86/io_apic.c | 43 ++++++++++++------------ xen/drivers/passthrough/amd/iommu_intr.c | 6 ---- 3 files changed, 25 insertions(+), 32 deletions(-) diff --git a/xen/arch/x86/include/asm/io_apic.h b/xen/arch/x86/include/asm/io_apic.h index 4c4777b68a51..9165da2281ae 100644 --- a/xen/arch/x86/include/asm/io_apic.h +++ b/xen/arch/x86/include/asm/io_apic.h @@ -162,8 +162,8 @@ static inline void __io_apic_write(unsigned int apic, unsigned int reg, unsigned static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) { - if ( ioapic_reg_remapped(reg) ) - return iommu_update_ire_from_apic(apic, reg, value); + /* RTE writes must use ioapic_write_entry. */ + BUG_ON(reg >= 0x10); __io_apic_write(apic, reg, value); } @@ -173,8 +173,8 @@ static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned i */ static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) { - if ( ioapic_reg_remapped(reg) ) - return iommu_update_ire_from_apic(apic, reg, value); + /* RTE writes must use ioapic_write_entry. */ + BUG_ON(reg >= 0x10); *(IO_APIC_BASE(apic) + 4) = value; } diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c index aada2ef96c62..041233b9b706 100644 --- a/xen/arch/x86/io_apic.c +++ b/xen/arch/x86/io_apic.c @@ -237,15 +237,15 @@ struct IO_APIC_route_entry __ioapic_read_entry( { union entry_union eu; - if ( raw ) + if ( raw || !iommu_intremap ) { eu.w1 = __io_apic_read(apic, 0x10 + 2 * pin); eu.w2 = __io_apic_read(apic, 0x11 + 2 * pin); } else { - eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); - eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); + eu.w1 = iommu_read_apic_from_ire(apic, 0x10 + 2 * pin); + eu.w2 = iommu_read_apic_from_ire(apic, 0x11 + 2 * pin); } return eu.entry; @@ -269,15 +269,15 @@ void __ioapic_write_entry( { union entry_union eu = { .entry = e }; - if ( raw ) + if ( raw || !iommu_intremap ) { __io_apic_write(apic, 0x11 + 2 * pin, eu.w2); __io_apic_write(apic, 0x10 + 2 * pin, eu.w1); } else { - io_apic_write(apic, 0x11 + 2 * pin, eu.w2); - io_apic_write(apic, 0x10 + 2 * pin, eu.w1); + iommu_update_ire_from_apic(apic, 0x11 + 2 * pin, eu.w2); + iommu_update_ire_from_apic(apic, 0x10 + 2 * pin, eu.w1); } } @@ -433,16 +433,17 @@ static void modify_IO_APIC_irq(unsigned int irq, unsigned int enable, unsigned int disable) { struct irq_pin_list *entry = irq_2_pin + irq; - unsigned int pin, reg; for (;;) { - pin = entry->pin; + unsigned int pin = entry->pin; + struct IO_APIC_route_entry rte; + if (pin == -1) break; - reg = io_apic_read(entry->apic, 0x10 + pin*2); - reg &= ~disable; - reg |= enable; - io_apic_modify(entry->apic, 0x10 + pin*2, reg); + rte = __ioapic_read_entry(entry->apic, pin, false); + rte.raw &= ~(uint64_t)disable; + rte.raw |= enable; + __ioapic_write_entry(entry->apic, pin, false, rte); if (!entry->next) break; entry = irq_2_pin + entry->next; @@ -584,16 +585,16 @@ set_ioapic_affinity_irq(struct irq_desc *desc, const cpumask_t *mask) dest = SET_APIC_LOGICAL_ID(dest); entry = irq_2_pin + irq; for (;;) { - unsigned int data; + struct IO_APIC_route_entry rte; + pin = entry->pin; if (pin == -1) break; - io_apic_write(entry->apic, 0x10 + 1 + pin*2, dest); - data = io_apic_read(entry->apic, 0x10 + pin*2); - data &= ~IO_APIC_REDIR_VECTOR_MASK; - data |= MASK_INSR(desc->arch.vector, IO_APIC_REDIR_VECTOR_MASK); - io_apic_modify(entry->apic, 0x10 + pin*2, data); + rte = __ioapic_read_entry(entry->apic, pin, false); + rte.dest.dest32 = dest; + rte.vector = desc->arch.vector; + __ioapic_write_entry(entry->apic, pin, false, rte); if (!entry->next) break; @@ -2127,10 +2128,8 @@ void ioapic_resume(void) reg_00.bits.ID = mp_ioapics[apic].mpc_apicid; __io_apic_write(apic, 0, reg_00.raw); } - for (i = 0; i < nr_ioapic_entries[apic]; i++, entry++) { - __io_apic_write(apic, 0x11+2*i, *(((int *)entry)+1)); - __io_apic_write(apic, 0x10+2*i, *(((int *)entry)+0)); - } + for (i = 0; i < nr_ioapic_entries[apic]; i++, entry++) + __ioapic_write_entry(apic, i, true, *entry); } spin_unlock_irqrestore(&ioapic_lock, flags); } diff --git a/xen/drivers/passthrough/amd/iommu_intr.c b/xen/drivers/passthrough/amd/iommu_intr.c index 9e6be3be3515..f32c418a7e49 100644 --- a/xen/drivers/passthrough/amd/iommu_intr.c +++ b/xen/drivers/passthrough/amd/iommu_intr.c @@ -361,12 +361,6 @@ void cf_check amd_iommu_ioapic_update_ire( struct amd_iommu *iommu; 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Signed-off-by: Roger Pau Monné Reviewed-by: Kevin Tian --- Changes since v1: - New in this version. --- xen/drivers/passthrough/vtd/intremap.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/xen/drivers/passthrough/vtd/intremap.c b/xen/drivers/passthrough/vtd/intremap.c index 786388b4d9c7..05df6d5759b1 100644 --- a/xen/drivers/passthrough/vtd/intremap.c +++ b/xen/drivers/passthrough/vtd/intremap.c @@ -441,14 +441,14 @@ unsigned int cf_check io_apic_read_remap_rte( void cf_check io_apic_write_remap_rte( unsigned int apic, unsigned int reg, unsigned int value) { - unsigned int ioapic_pin = (reg - 0x10) / 2; + unsigned int pin = (reg - 0x10) / 2; struct IO_xAPIC_route_entry old_rte = { }; struct IO_APIC_route_remap_entry *remap_rte; unsigned int rte_upper = (reg & 1) ? 1 : 0; struct vtd_iommu *iommu = ioapic_to_iommu(IO_APIC_ID(apic)); int saved_mask; - old_rte = __ioapic_read_entry(apic, ioapic_pin, true); + old_rte = __ioapic_read_entry(apic, pin, true); remap_rte = (struct IO_APIC_route_remap_entry *) &old_rte; @@ -458,7 +458,7 @@ void cf_check io_apic_write_remap_rte( __io_apic_write(apic, reg & ~1, *(u32 *)&old_rte); remap_rte->mask = saved_mask; - if ( ioapic_rte_to_remap_entry(iommu, apic, ioapic_pin, + if ( ioapic_rte_to_remap_entry(iommu, apic, pin, &old_rte, rte_upper, value) ) { __io_apic_write(apic, reg, value); @@ -468,7 +468,7 @@ void cf_check io_apic_write_remap_rte( __io_apic_write(apic, reg & ~1, *(u32 *)&old_rte); } else - __ioapic_write_entry(apic, ioapic_pin, true, old_rte); + __ioapic_write_entry(apic, pin, true, old_rte); } static void set_msi_source_id(struct pci_dev *pdev, struct iremap_entry *ire) From patchwork Wed Jul 26 12:55:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Roger_Pau_Monn=C3=A9?= X-Patchwork-Id: 13327986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D831C0015E for ; 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Doing such update atomically will avoid Xen having to mask the IO-APIC pin prior to performing any interrupt movements (ie: changing the destination and vector fields), as the interrupt remapping entry is always consistent. This also simplifies some of the logic on both VT-d and AMD-Vi implementations, as having the full RTE available instead of half of it avoids to possibly read and update the missing other half from hardware. While there remove the explicit zeroing of new_ire fields in ioapic_rte_to_remap_entry() and initialize the variable at definition so all fields are zeroed. Note fields could be also initialized with final values at definition, but I found that likely too much to be done at this time. Signed-off-by: Roger Pau Monné --- Changes since v2: - Remove unneeded initialization. - Use 'rte' as parameter name for update_ire_from_apic() implementations. - Fix comment style in ioapic_rte_to_remap_entry(). - Fix requirement for atomic write in update_irte() call from ioapic_rte_to_remap_entry(). - Remove remap_rte from io_apic_write_remap_rte(). --- Note that certain combination of changes to the RTE are impossible to handle atomically. For example changing the vector and/or destination fields together with the triggering mode is impossible to be performed atomically (as the destination and vector is set in the IRTE, but the triggering mode is set in the RTE). Xen doesn't attempt to perform such changes in a single update to the RTE anyway, so it's fine. Naming the iommu_update_ire_from_apic() parameter RTE is not really correct, as the format of the passed value expands the destination field to be 32bits (in order to fit an x2APIC ID). Passing an IO_APIC_route_entry struct is not possible due to the circular dependency that would create between io_apic.h and iommu.h. It might be possible to move IO_APIC_route_entry declaration to a different header, but I haven't looked into it. --- xen/arch/x86/include/asm/iommu.h | 3 +- xen/arch/x86/io_apic.c | 5 +- xen/drivers/passthrough/amd/iommu.h | 2 +- xen/drivers/passthrough/amd/iommu_intr.c | 100 ++--------------- xen/drivers/passthrough/vtd/extern.h | 2 +- xen/drivers/passthrough/vtd/intremap.c | 136 +++++++++++------------ xen/drivers/passthrough/x86/iommu.c | 4 +- xen/include/xen/iommu.h | 3 +- 8 files changed, 86 insertions(+), 169 deletions(-) diff --git a/xen/arch/x86/include/asm/iommu.h b/xen/arch/x86/include/asm/iommu.h index 0540cd9faa87..eb720205e25e 100644 --- a/xen/arch/x86/include/asm/iommu.h +++ b/xen/arch/x86/include/asm/iommu.h @@ -84,7 +84,8 @@ struct iommu_init_ops { extern const struct iommu_init_ops *iommu_init_ops; -void iommu_update_ire_from_apic(unsigned int apic, unsigned int reg, unsigned int value); +void iommu_update_ire_from_apic(unsigned int apic, unsigned int pin, + uint64_t rte); unsigned int iommu_read_apic_from_ire(unsigned int apic, unsigned int reg); int iommu_setup_hpet_msi(struct msi_desc *); diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c index 041233b9b706..b3afef8933d7 100644 --- a/xen/arch/x86/io_apic.c +++ b/xen/arch/x86/io_apic.c @@ -275,10 +275,7 @@ void __ioapic_write_entry( __io_apic_write(apic, 0x10 + 2 * pin, eu.w1); } else - { - iommu_update_ire_from_apic(apic, 0x11 + 2 * pin, eu.w2); - iommu_update_ire_from_apic(apic, 0x10 + 2 * pin, eu.w1); - } + iommu_update_ire_from_apic(apic, pin, e.raw); } static void ioapic_write_entry( diff --git a/xen/drivers/passthrough/amd/iommu.h b/xen/drivers/passthrough/amd/iommu.h index 8bc3c35b1bb1..5429ada58ef5 100644 --- a/xen/drivers/passthrough/amd/iommu.h +++ b/xen/drivers/passthrough/amd/iommu.h @@ -300,7 +300,7 @@ int cf_check amd_iommu_free_intremap_table( unsigned int amd_iommu_intremap_table_order( const void *irt, const struct amd_iommu *iommu); void cf_check amd_iommu_ioapic_update_ire( - unsigned int apic, unsigned int reg, unsigned int value); + unsigned int apic, unsigned int pin, uint64_t rte); unsigned int cf_check amd_iommu_read_ioapic_from_ire( unsigned int apic, unsigned int reg); int cf_check amd_iommu_msi_msg_update_ire( diff --git a/xen/drivers/passthrough/amd/iommu_intr.c b/xen/drivers/passthrough/amd/iommu_intr.c index f32c418a7e49..e83a2a932af8 100644 --- a/xen/drivers/passthrough/amd/iommu_intr.c +++ b/xen/drivers/passthrough/amd/iommu_intr.c @@ -247,11 +247,6 @@ static void update_intremap_entry(const struct amd_iommu *iommu, } } -static inline int get_rte_index(const struct IO_APIC_route_entry *rte) -{ - return rte->vector | (rte->delivery_mode << 8); -} - static inline void set_rte_index(struct IO_APIC_route_entry *rte, int offset) { rte->vector = (u8)offset; @@ -267,7 +262,6 @@ static int update_intremap_entry_from_ioapic( int bdf, struct amd_iommu *iommu, struct IO_APIC_route_entry *rte, - bool_t lo_update, u16 *index) { unsigned long flags; @@ -315,31 +309,6 @@ static int update_intremap_entry_from_ioapic( spin_lock(lock); } - if ( fresh ) - /* nothing */; - else if ( !lo_update ) - { - /* - * Low half of incoming RTE is already in remapped format, - * so need to recover vector and delivery mode from IRTE. - */ - ASSERT(get_rte_index(rte) == offset); - if ( iommu->ctrl.ga_en ) - vector = entry.ptr128->full.vector; - else - vector = entry.ptr32->flds.vector; - /* The IntType fields match for both formats. */ - delivery_mode = entry.ptr32->flds.int_type; - } - else if ( x2apic_enabled ) - { - /* - * High half of incoming RTE was read from the I/O APIC and hence may - * not hold the full destination, so need to recover full destination - * from IRTE. - */ - dest = get_full_dest(entry.ptr128); - } update_intremap_entry(iommu, entry, vector, delivery_mode, dest_mode, dest); spin_unlock_irqrestore(lock, flags); @@ -350,14 +319,11 @@ static int update_intremap_entry_from_ioapic( } void cf_check amd_iommu_ioapic_update_ire( - unsigned int apic, unsigned int reg, unsigned int value) + unsigned int apic, unsigned int pin, uint64_t rte) { - struct IO_APIC_route_entry old_rte = { }; - struct IO_APIC_route_entry new_rte = { }; - unsigned int rte_lo = (reg & 1) ? reg - 1 : reg; - unsigned int pin = (reg - 0x10) / 2; + struct IO_APIC_route_entry old_rte; + struct IO_APIC_route_entry new_rte = { .raw = rte }; int seg, bdf, rc; - bool saved_mask, fresh = false; struct amd_iommu *iommu; unsigned int idx; @@ -373,58 +339,23 @@ void cf_check amd_iommu_ioapic_update_ire( { AMD_IOMMU_WARN("failed to find IOMMU for IO-APIC @ %04x:%04x\n", seg, bdf); - __io_apic_write(apic, reg, value); + __ioapic_write_entry(apic, pin, true, new_rte); return; } - /* save io-apic rte lower 32 bits */ - *((u32 *)&old_rte) = __io_apic_read(apic, rte_lo); - saved_mask = old_rte.mask; - - if ( reg == rte_lo ) - { - *((u32 *)&new_rte) = value; - /* read upper 32 bits from io-apic rte */ - *(((u32 *)&new_rte) + 1) = __io_apic_read(apic, reg + 1); - } - else - { - *((u32 *)&new_rte) = *((u32 *)&old_rte); - *(((u32 *)&new_rte) + 1) = value; - } - - if ( ioapic_sbdf[idx].pin_2_idx[pin] >= INTREMAP_MAX_ENTRIES ) - { - ASSERT(saved_mask); - - /* - * There's nowhere except the IRTE to store a full 32-bit destination, - * so we may not bypass entry allocation and updating of the low RTE - * half in the (usual) case of the high RTE half getting written first. - */ - if ( new_rte.mask && !x2apic_enabled ) - { - __io_apic_write(apic, reg, value); - return; - } - - fresh = true; - } - + old_rte = __ioapic_read_entry(apic, pin, true); /* mask the interrupt while we change the intremap table */ - if ( !saved_mask ) + if ( !old_rte.mask ) { old_rte.mask = 1; - __io_apic_write(apic, rte_lo, *((u32 *)&old_rte)); + __ioapic_write_entry(apic, pin, true, old_rte); } /* Update interrupt remapping entry */ rc = update_intremap_entry_from_ioapic( - bdf, iommu, &new_rte, reg == rte_lo, + bdf, iommu, &new_rte, &ioapic_sbdf[idx].pin_2_idx[pin]); - __io_apic_write(apic, reg, ((u32 *)&new_rte)[reg != rte_lo]); - if ( rc ) { /* Keep the entry masked. */ @@ -433,20 +364,7 @@ void cf_check amd_iommu_ioapic_update_ire( return; } - /* For lower bits access, return directly to avoid double writes */ - if ( reg == rte_lo ) - return; - - /* - * Unmask the interrupt after we have updated the intremap table. Also - * write the low half if a fresh entry was allocated for a high half - * update in x2APIC mode. - */ - if ( !saved_mask || (x2apic_enabled && fresh) ) - { - old_rte.mask = saved_mask; - __io_apic_write(apic, rte_lo, *((u32 *)&old_rte)); - } + __ioapic_write_entry(apic, pin, true, new_rte); } unsigned int cf_check amd_iommu_read_ioapic_from_ire( diff --git a/xen/drivers/passthrough/vtd/extern.h b/xen/drivers/passthrough/vtd/extern.h index 39602d1f88f8..b684e9393d1a 100644 --- a/xen/drivers/passthrough/vtd/extern.h +++ b/xen/drivers/passthrough/vtd/extern.h @@ -92,7 +92,7 @@ int cf_check intel_iommu_get_reserved_device_memory( unsigned int cf_check io_apic_read_remap_rte( unsigned int apic, unsigned int reg); void cf_check io_apic_write_remap_rte( - unsigned int apic, unsigned int reg, unsigned int value); + unsigned int apic, unsigned int ioapic_pin, uint64_t rte); struct msi_desc; struct msi_msg; diff --git a/xen/drivers/passthrough/vtd/intremap.c b/xen/drivers/passthrough/vtd/intremap.c index 05df6d5759b1..4101fd6bccaf 100644 --- a/xen/drivers/passthrough/vtd/intremap.c +++ b/xen/drivers/passthrough/vtd/intremap.c @@ -328,15 +328,14 @@ static int remap_entry_to_ioapic_rte( static int ioapic_rte_to_remap_entry(struct vtd_iommu *iommu, int apic, unsigned int ioapic_pin, struct IO_xAPIC_route_entry *old_rte, - unsigned int rte_upper, unsigned int value) + struct IO_xAPIC_route_entry new_rte) { struct iremap_entry *iremap_entry = NULL, *iremap_entries; - struct iremap_entry new_ire; + struct iremap_entry new_ire = { }; struct IO_APIC_route_remap_entry *remap_rte; - struct IO_xAPIC_route_entry new_rte; int index; unsigned long flags; - bool init = false; + bool init = false, masked = old_rte->mask; remap_rte = (struct IO_APIC_route_remap_entry *) old_rte; spin_lock_irqsave(&iommu->intremap.lock, flags); @@ -364,48 +363,40 @@ static int ioapic_rte_to_remap_entry(struct vtd_iommu *iommu, new_ire = *iremap_entry; - if ( rte_upper ) - { - if ( x2apic_enabled ) - new_ire.remap.dst = value; - else - new_ire.remap.dst = (value >> 24) << 8; - } + if ( x2apic_enabled ) + new_ire.remap.dst = new_rte.dest.dest32; else - { - *(((u32 *)&new_rte) + 0) = value; - new_ire.remap.fpd = 0; - new_ire.remap.dm = new_rte.dest_mode; - new_ire.remap.tm = new_rte.trigger; - new_ire.remap.dlm = new_rte.delivery_mode; - /* Hardware require RH = 1 for LPR delivery mode */ - new_ire.remap.rh = (new_ire.remap.dlm == dest_LowestPrio); - new_ire.remap.avail = 0; - new_ire.remap.res_1 = 0; - new_ire.remap.vector = new_rte.vector; - new_ire.remap.res_2 = 0; - - set_ioapic_source_id(IO_APIC_ID(apic), &new_ire); - new_ire.remap.res_3 = 0; - new_ire.remap.res_4 = 0; - new_ire.remap.p = 1; /* finally, set present bit */ - - /* now construct new ioapic rte entry */ - remap_rte->vector = new_rte.vector; - remap_rte->delivery_mode = 0; /* has to be 0 for remap format */ - remap_rte->index_15 = (index >> 15) & 0x1; - remap_rte->index_0_14 = index & 0x7fff; - - remap_rte->delivery_status = new_rte.delivery_status; - remap_rte->polarity = new_rte.polarity; - remap_rte->irr = new_rte.irr; - remap_rte->trigger = new_rte.trigger; - remap_rte->mask = new_rte.mask; - remap_rte->reserved = 0; - remap_rte->format = 1; /* indicate remap format */ - } - - update_irte(iommu, iremap_entry, &new_ire, !init); + new_ire.remap.dst = (new_rte.dest.dest32 >> 24) << 8; + + new_ire.remap.dm = new_rte.dest_mode; + new_ire.remap.tm = new_rte.trigger; + new_ire.remap.dlm = new_rte.delivery_mode; + /* Hardware require RH = 1 for LPR delivery mode. */ + new_ire.remap.rh = (new_ire.remap.dlm == dest_LowestPrio); + new_ire.remap.vector = new_rte.vector; + + set_ioapic_source_id(IO_APIC_ID(apic), &new_ire); + /* Finally, set present bit. */ + new_ire.remap.p = 1; + + /* Now construct new ioapic rte entry. */ + remap_rte->vector = new_rte.vector; + /* Has to be 0 for remap format. */ + remap_rte->delivery_mode = 0; + remap_rte->index_15 = (index >> 15) & 0x1; + remap_rte->index_0_14 = index & 0x7fff; + + remap_rte->delivery_status = new_rte.delivery_status; + remap_rte->polarity = new_rte.polarity; + remap_rte->irr = new_rte.irr; + remap_rte->trigger = new_rte.trigger; + remap_rte->mask = new_rte.mask; + remap_rte->reserved = 0; + /* Indicate remap format. */ + remap_rte->format = 1; + + /* If cmpxchg16b is not available the caller must mask the IO-APIC pin. */ + update_irte(iommu, iremap_entry, &new_ire, !init && !masked); iommu_sync_cache(iremap_entry, sizeof(*iremap_entry)); iommu_flush_iec_index(iommu, 0, index); @@ -439,36 +430,45 @@ unsigned int cf_check io_apic_read_remap_rte( } void cf_check io_apic_write_remap_rte( - unsigned int apic, unsigned int reg, unsigned int value) + unsigned int apic, unsigned int pin, uint64_t rte) { - unsigned int pin = (reg - 0x10) / 2; + struct IO_xAPIC_route_entry new_rte = { .raw = rte }; struct IO_xAPIC_route_entry old_rte = { }; - struct IO_APIC_route_remap_entry *remap_rte; - unsigned int rte_upper = (reg & 1) ? 1 : 0; struct vtd_iommu *iommu = ioapic_to_iommu(IO_APIC_ID(apic)); - int saved_mask; - - old_rte = __ioapic_read_entry(apic, pin, true); + bool masked = true; + int rc; - remap_rte = (struct IO_APIC_route_remap_entry *) &old_rte; - - /* mask the interrupt while we change the intremap table */ - saved_mask = remap_rte->mask; - remap_rte->mask = 1; - __io_apic_write(apic, reg & ~1, *(u32 *)&old_rte); - remap_rte->mask = saved_mask; - - if ( ioapic_rte_to_remap_entry(iommu, apic, pin, - &old_rte, rte_upper, value) ) + if ( !cpu_has_cx16 ) { - __io_apic_write(apic, reg, value); + /* + * Cannot atomically update the IRTE entry: mask the IO-APIC pin to + * avoid interrupts seeing an inconsistent IRTE entry. + */ + old_rte = __ioapic_read_entry(apic, pin, true); + if ( !old_rte.mask ) + { + masked = false; + old_rte.mask = 1; + __ioapic_write_entry(apic, pin, true, old_rte); + } + } - /* Recover the original value of 'mask' bit */ - if ( rte_upper ) - __io_apic_write(apic, reg & ~1, *(u32 *)&old_rte); + rc = ioapic_rte_to_remap_entry(iommu, apic, pin, &old_rte, new_rte); + if ( rc ) + { + if ( !masked ) + { + /* Recover the original value of 'mask' bit */ + old_rte.mask = 0; + __ioapic_write_entry(apic, pin, true, old_rte); + } + dprintk(XENLOG_ERR VTDPREFIX, + "failed to update IRTE for IO-APIC#%u pin %u: %d\n", + apic, pin, rc); + return; } - else - __ioapic_write_entry(apic, pin, true, old_rte); + /* old_rte will contain the updated IO-APIC RTE on success. */ + __ioapic_write_entry(apic, pin, true, old_rte); } static void set_msi_source_id(struct pci_dev *pdev, struct iremap_entry *ire) diff --git a/xen/drivers/passthrough/x86/iommu.c b/xen/drivers/passthrough/x86/iommu.c index be71a4c4641c..d290855959f2 100644 --- a/xen/drivers/passthrough/x86/iommu.c +++ b/xen/drivers/passthrough/x86/iommu.c @@ -158,9 +158,9 @@ int iommu_enable_x2apic(void) } void iommu_update_ire_from_apic( - unsigned int apic, unsigned int reg, unsigned int value) + unsigned int apic, unsigned int pin, uint64_t rte) { - iommu_vcall(&iommu_ops, update_ire_from_apic, apic, reg, value); + iommu_vcall(&iommu_ops, update_ire_from_apic, apic, pin, rte); } unsigned int iommu_read_apic_from_ire(unsigned int apic, unsigned int reg) diff --git a/xen/include/xen/iommu.h b/xen/include/xen/iommu.h index 405db59971c5..9335cd074cff 100644 --- a/xen/include/xen/iommu.h +++ b/xen/include/xen/iommu.h @@ -278,7 +278,8 @@ struct iommu_ops { int (*enable_x2apic)(void); void (*disable_x2apic)(void); - void (*update_ire_from_apic)(unsigned int apic, unsigned int reg, unsigned int value); + void (*update_ire_from_apic)(unsigned int apic, unsigned int pin, + uint64_t rte); unsigned int (*read_apic_from_ire)(unsigned int apic, unsigned int reg); int (*setup_hpet_msi)(struct msi_desc *);