From patchwork Fri Jul 28 12:46:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Animesh Manna X-Patchwork-Id: 13331877 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8475CC001DE for ; Fri, 28 Jul 2023 12:56:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D9FA610E20D; Fri, 28 Jul 2023 12:56:24 +0000 (UTC) Received: from mgamail.intel.com (unknown [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 11FE010E203 for ; Fri, 28 Jul 2023 12:56:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690548982; x=1722084982; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=z5FYXb26zisytD8XHdVF42nRd7YZjoz76b8QVxRbrKs=; b=Lh0yJjY1gz9btxOAmM6PbCBgWXelkBV/toG/0lvbJOkAphsM/hjYjk4u fOp1Cl8TB1U5oIlGjGgjrjI6OnDdupL9QEfaArhZT+ivLfOzn0UZTv8ve Ag4a9KqFKR2hvhil2v4IOc181IbT9vEP3yZfjsuT5ctlQuW12kWYOH9jc wp6GqlNJpk+oUwV8sjf1NDDwDPjRb6b2iRXRbNsPiaz1chQnIQAArkP2O Jll0D3cAr15lx9uZlcccPCEbagnzrHjj3SOC2gnA31PqUs6VQ0EGMmZ9D +Jq5TQqIQS/txs1TJpNNrDRkvvJlkOHahlnhAtd9On0s9G/NKKMiSQAZa w==; X-IronPort-AV: E=McAfee;i="6600,9927,10784"; a="358612276" X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="358612276" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2023 05:56:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10784"; a="727473063" X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="727473063" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga002.jf.intel.com with ESMTP; 28 Jul 2023 05:56:20 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Fri, 28 Jul 2023 18:16:04 +0530 Message-Id: <20230728124609.2911830-2-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20230728124609.2911830-1-animesh.manna@intel.com> References: <20230728124609.2911830-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 1/6] drm/panelreplay: dpcd register definition for panelreplay X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" DPCD register definition added to check and enable panel replay capability of the sink. Cc: Jouni Högander Signed-off-by: Animesh Manna --- include/drm/display/drm_dp.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 02f2ac4dd2df..c48696266d23 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -543,6 +543,10 @@ /* DFP Capability Extension */ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ +#define DP_PANEL_REPLAY_CAP 0x0b0 +# define DP_PANEL_REPLAY_SUPPORT (1 << 0) +# define DP_PR_SELECTIVE_UPDATE_SUPPORT (1 << 1) + /* Link Configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ @@ -716,6 +720,13 @@ #define DP_BRANCH_DEVICE_CTRL 0x1a1 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) +#define PANEL_REPLAY_CONFIG 0x1b0 +# define DP_PANEL_REPLAY_ENABLE (1 << 0) +# define DP_PR_UNRECOVERABLE_ERROR (1 << 3) +# define DP_PR_RFB_STORAGE_ERROR (1 << 4) +# define DP_PR_ACTIVE_FRAME_CRC_ERROR (1 << 5) +# define DP_PR_SELECTIVE_UPDATE_ENABLE (1 << 6) + #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 From patchwork Fri Jul 28 12:46:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Animesh Manna X-Patchwork-Id: 13331878 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0C762C001DE for ; Fri, 28 Jul 2023 12:56:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 85AFF10E20A; Fri, 28 Jul 2023 12:56:28 +0000 (UTC) Received: from mgamail.intel.com (unknown [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id D5BDD10E20A for ; Fri, 28 Jul 2023 12:56:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690548984; x=1722084984; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+N+kw0+wXk3DuWLPMRSkPIO9uEJkCJMkRcX+jmv8/WE=; b=NNDD906SyQE7hRoObkI1PZrTgVaCIe5KUzeNL7RdbKBjyMie7lm6xed7 n/m3+ecYUA4x2n3T7jaFxGJXYs5jyOqfabICNu4Oe6kMVxUuK5YA1/aTU Qcllgd77APvS2SZ3ZKg08C+5/pmTHnbmzUTxozZ0Vb/4h1BwUu7nDG2WX AvWJV1Wfdwykrhkqz2NH0tAS7sIllDlj6igtcMsfb5InURm9juVrs/puf DeMWnzLKP2pUn+ilt9Pua38j1g3P0tfdy9adf/uHw6ixqjTT6WD+Mq9HL n3X/0XuiJwutYbT53AqacJlz74f5BO1lTbbCFHTFQ0v66lK2aYVUWRauk Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10784"; a="358612279" X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="358612279" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2023 05:56:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10784"; a="727473086" X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="727473086" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga002.jf.intel.com with ESMTP; 28 Jul 2023 05:56:23 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Fri, 28 Jul 2023 18:16:05 +0530 Message-Id: <20230728124609.2911830-3-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20230728124609.2911830-1-animesh.manna@intel.com> References: <20230728124609.2911830-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 2/6] drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Platforms having Display 13 and above will support panel replay feature of DP 2.0 monitor. Added a HAS_PANEL_REPLAY() macro to check for panel replay capability. v1: Initial version. v2: DISPLAY_VER() removed as HAS_DP20() is having platform check. [Jouni] Cc: Jouni Högander Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_display_device.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 3324bd453ca7..53bc8f972a26 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -60,6 +60,7 @@ struct drm_printer; #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) #define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay) #define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr) +#define HAS_PANEL_REPLAY(dev_priv) (HAS_DP20(dev_priv)) #define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking) #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12) #define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915)) From patchwork Fri Jul 28 12:46:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Animesh Manna X-Patchwork-Id: 13331882 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38E07C001DE for ; Fri, 28 Jul 2023 12:57:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8EC2510E6D6; Fri, 28 Jul 2023 12:57:25 +0000 (UTC) Received: from mgamail.intel.com (unknown [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9330D10E6D6 for ; Fri, 28 Jul 2023 12:57:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690549043; x=1722085043; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wTzhepz2XIxVBEGwvnIjNFp6LcbqDUmHO/7sryhihcc=; b=kDZ/wB80fEMchbe9uM0uhwHWUnWMYRJ6ewCpTBMzaE6PEnI3K2e4Ie7W jSvhpNaQ6Dh+mWAV3QmKmth7Vfbxb26ehLyyEpV6hwoXGe4wuH7o12zF0 jrcYqitpZhi0whkG+V36iJyC76/k3tQu/njxEO3zKsE2LWy0REqQMNzgV KVnYWRFmPJPu8uTRyPowkryW2GK0dHRUMJmPfo+3yo7sKiGZsKY47bsRy xpqn1jwfZ4n4kqOUD8QOBYYL/ZMzLGm2Dv9WTVXfxo00AssafPyxHA4yH ZvQya+0/oL3rJFw8UYi5z4LW0ExRdY4PciWNTxM+2HRyVCunqFJI8E/D5 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10784"; a="358612291" X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="358612291" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2023 05:56:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10784"; a="727473117" X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="727473117" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga002.jf.intel.com with ESMTP; 28 Jul 2023 05:56:26 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Fri, 28 Jul 2023 18:16:06 +0530 Message-Id: <20230728124609.2911830-4-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20230728124609.2911830-1-animesh.manna@intel.com> References: <20230728124609.2911830-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 3/6] drm/i915/psr: Move psr specific dpcd init into own function X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Jouni Högander This patch is preparing adding panel replay specific dpcd init. Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 39 +++++++++++++----------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 04ab034a8d57..9fbcb4b93f11 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -472,27 +472,22 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) intel_dp->psr.su_y_granularity = y; } -void intel_psr_init_dpcd(struct intel_dp *intel_dp) +static void _psr_init_dpcd(struct intel_dp *intel_dp) { - struct drm_i915_private *dev_priv = + struct drm_i915_private *i915 = to_i915(dp_to_dig_port(intel_dp)->base.base.dev); - drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, - sizeof(intel_dp->psr_dpcd)); - - if (!intel_dp->psr_dpcd[0]) - return; - drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", + drm_dbg_kms(&i915->drm, "eDP panel supports PSR version %x\n", intel_dp->psr_dpcd[0]); if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "PSR support not currently available for this panel\n"); return; } if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(&i915->drm, "Panel lacks power state control, PSR cannot be enabled\n"); return; } @@ -501,7 +496,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) intel_dp->psr.sink_sync_latency = intel_dp_get_sink_sync_latency(intel_dp); - if (DISPLAY_VER(dev_priv) >= 9 && + if (DISPLAY_VER(i915) >= 9 && (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { bool y_req = intel_dp->psr_dpcd[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED; @@ -519,14 +514,24 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) * GTC first. */ intel_dp->psr.sink_psr2_support = y_req && alpm; - drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", + drm_dbg_kms(&i915->drm, "PSR2 %ssupported\n", intel_dp->psr.sink_psr2_support ? "" : "not "); + } +} - if (intel_dp->psr.sink_psr2_support) { - intel_dp->psr.colorimetry_support = - intel_dp_get_colorimetry_status(intel_dp); - intel_dp_get_su_granularity(intel_dp); - } +void intel_psr_init_dpcd(struct intel_dp *intel_dp) +{ + drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, + sizeof(intel_dp->psr_dpcd)); + + if (intel_dp->psr_dpcd[0]) + _psr_init_dpcd(intel_dp); + /* TODO: Add PR case here */ + + if (intel_dp->psr.sink_psr2_support) { + intel_dp->psr.colorimetry_support = + intel_dp_get_colorimetry_status(intel_dp); + intel_dp_get_su_granularity(intel_dp); } } From patchwork Fri Jul 28 12:46:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Animesh Manna X-Patchwork-Id: 13331879 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B165EC001DF for ; Fri, 28 Jul 2023 12:56:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 45BDA10E210; Fri, 28 Jul 2023 12:56:32 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 63B5110E210 for ; Fri, 28 Jul 2023 12:56:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690548991; x=1722084991; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ypHBG/tgeWY+Ho5zLPZxmDo3a1SEqN+Xwx3YGjp97PE=; b=bRvd6D/94f0NXPDZ/v+sib6ANAhnflvN806bqB55r9PkC9OnJ6xVJLMA PYpu9OmpdFnE/5PHTmafrv1cRkfwANA90BTNDN8gSaALtK2f/av66nYP/ fluDYWaVCmnfG/4q7msAcIg4ZDCNWcAe+TXpg2YRBZE6tV/SFxe+bY9Jd 4CaR+a2ZQ8/7OxMRZhXME0AwTqIn5RmCa0KX7R4Mgm3qpST8bvmvm6XJI c2YhynFqh7u2qblRUc75a5Nk18JaT2gdsiHTg3XWY8LS/IpQgTiczRJ8w 2gYBYUOAnuc4d7hgS5B+VsTKsEBf1kd8Yx2Riv/Ja1aGwcozIaI1lT6To g==; X-IronPort-AV: E=McAfee;i="6600,9927,10784"; a="358612301" X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="358612301" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2023 05:56:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10784"; a="727473135" X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="727473135" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga002.jf.intel.com with ESMTP; 28 Jul 2023 05:56:28 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Fri, 28 Jul 2023 18:16:07 +0530 Message-Id: <20230728124609.2911830-5-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20230728124609.2911830-1-animesh.manna@intel.com> References: <20230728124609.2911830-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Modify existing PSR implementation to enable panel replay feature of DP 2.0 which is similar to PSR feature of EDP panel. There is different DPCD address to check panel capability compare to PSR and vsc sdp header is different. v1: Initial version. v2: - Set source_panel_replay_support flag under HAS_PNEL_REPLAY() check. [Jouni] - Code restructured around intel_panel_replay_init and renamed to intel_panel_replay_init_dpcd. [Jouni] - Remove the initial code modification around has_psr2 flag. [Jouni] - Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to enable in intel_psr_post_plane_update. [Jouni] v3: - Initialize both psr and panel-replay. [Jouni] - Initialize both panel replay and psr if detected. [Jouni] - Refactoring psr function by introducing _psr_compute_config(). [Jouni] - Add check for !is_edp while deriving source_panel_replay_support. [Jouni] - Enable panel replay dpcd initialization in a separate patch. [Jouni] Cc: Jouni Högander Signed-off-by: Animesh Manna --- .../drm/i915/display/intel_display_types.h | 8 +- drivers/gpu/drm/i915/display/intel_dp.c | 44 ++++++++-- drivers/gpu/drm/i915/display/intel_psr.c | 88 +++++++++++++------ 3 files changed, 104 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 731f2ec04d5c..1ff7e6c03b44 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1202,6 +1202,7 @@ struct intel_crtc_state { bool has_psr2; bool enable_psr2_sel_fetch; bool req_psr2_sdp_prior_scanline; + bool has_pr; bool wm_level_disabled; u32 dc3co_exitline; u16 su_y_granularity; @@ -1693,6 +1694,8 @@ struct intel_psr { bool irq_aux_error; u16 su_w_granularity; u16 su_y_granularity; + bool source_panel_replay_support; + bool sink_panel_replay_support; u32 dc3co_exitline; u32 dc3co_exit_delay; struct delayed_work dc3co_work; @@ -1983,12 +1986,15 @@ dp_to_lspcon(struct intel_dp *intel_dp) #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ (intel_dp)->psr.source_support) +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \ + (intel_dp)->psr.source_panel_replay_support) + static inline bool intel_encoder_can_psr(struct intel_encoder *encoder) { if (!intel_encoder_is_dp(encoder)) return false; - return CAN_PSR(enc_to_intel_dp(encoder)); + return CAN_PSR(enc_to_intel_dp(encoder)) || CAN_PANEL_REPLAY(enc_to_intel_dp(encoder)); } static inline struct intel_digital_port * diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 03675620e3ea..0ba231ee6e34 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1946,12 +1946,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - /* - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ - * Colorimetry Format indication. - */ - vsc->revision = 0x5; + if (crtc_state->has_pr) { + /* + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel + * Encoding/Colorimetry Format indication. + */ + vsc->revision = 0x7; + } else { + /* + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ + * Colorimetry Format indication. + */ + vsc->revision = 0x5; + } + vsc->length = 0x13; /* DP 1.4a spec, Table 2-120 */ @@ -2060,6 +2070,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, vsc->revision = 0x4; vsc->length = 0xe; } + } else if (crtc_state->has_pr) { + if (intel_dp->psr.colorimetry_support && + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { + /* [Panel Replay with colorimetry info] */ + intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, + vsc); + } else { + /* + * [Panel Replay without colorimetry info] + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223 + * VSC SDP supporting 3D stereo + Panel Replay. + */ + vsc->revision = 0x6; + vsc->length = 0x10; + } } else { /* * [PSR1] @@ -3354,10 +3379,11 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ /* - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as - * per DP 1.4a spec. + * Other than revision 0x5 which supports Pixel Encoding/Colorimetry + * Format as per DP 1.4a spec, revision 0x7 also supports Pixel + * Encoding/Colorimetry Format as per DP 2.0 spec. */ - if (vsc->revision != 0x5) + if (vsc->revision != 0x5 || vsc->revision != 0x7) goto out; /* VSC SDP Payload for DB16 through DB18 */ diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 9fbcb4b93f11..7508e6c967e2 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -472,6 +472,27 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) intel_dp->psr.su_y_granularity = y; } +static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + u8 pr_dpcd = 0; + + if (!HAS_PANEL_REPLAY(dev_priv)) + return; + + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd); + + if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) { + drm_dbg_kms(&dev_priv->drm, + "Panel replay is not supported by panel\n"); + return; + } + + drm_dbg_kms(&dev_priv->drm, + "Panel replay is supported by panel\n"); + intel_dp->psr.sink_panel_replay_support = true; +} + static void _psr_init_dpcd(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = @@ -521,12 +542,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp) void intel_psr_init_dpcd(struct intel_dp *intel_dp) { + _panel_replay_init_dpcd(intel_dp); + drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, sizeof(intel_dp->psr_dpcd)); if (intel_dp->psr_dpcd[0]) _psr_init_dpcd(intel_dp); - /* TODO: Add PR case here */ if (intel_dp->psr.sink_psr2_support) { intel_dp->psr.colorimetry_support = @@ -1207,13 +1229,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } -void intel_psr_compute_config(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state, - struct drm_connector_state *conn_state) +static bool _psr_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - const struct drm_display_mode *adjusted_mode = - &crtc_state->hw.adjusted_mode; + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; int psr_setup_time; /* @@ -1221,10 +1241,36 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, * So if VRR is enabled, do not enable PSR. */ if (crtc_state->vrr.enable) - return; + return false; if (!CAN_PSR(intel_dp)) - return; + return false; + + psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); + if (psr_setup_time < 0) { + drm_dbg_kms(&dev_priv->drm, + "PSR condition failed: Invalid PSR setup time (0x%02x)\n", + intel_dp->psr_dpcd[1]); + return false; + } + + if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > + adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { + drm_dbg_kms(&dev_priv->drm, + "PSR condition failed: PSR setup time (%d us) too long\n", + psr_setup_time); + return false; + } + + return true; +} + +void intel_psr_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; if (!psr_global_enabled(intel_dp)) { drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); @@ -1234,7 +1280,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, if (intel_dp->psr.sink_not_reliable) { drm_dbg_kms(&dev_priv->drm, "PSR sink implementation is not reliable\n"); - return; } if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { @@ -1243,23 +1288,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, return; } - psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); - if (psr_setup_time < 0) { - drm_dbg_kms(&dev_priv->drm, - "PSR condition failed: Invalid PSR setup time (0x%02x)\n", - intel_dp->psr_dpcd[1]); - return; - } - - if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > - adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { - drm_dbg_kms(&dev_priv->drm, - "PSR condition failed: PSR setup time (%d us) too long\n", - psr_setup_time); - return; - } + if (CAN_PANEL_REPLAY(intel_dp)) + crtc_state->has_pr = true; + else + crtc_state->has_psr = _psr_compute_config(intel_dp, crtc_state); - crtc_state->has_psr = true; crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); @@ -2699,7 +2732,7 @@ void intel_psr_init(struct intel_dp *intel_dp) struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - if (!HAS_PSR(dev_priv)) + if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv))) return; /* @@ -2719,6 +2752,9 @@ void intel_psr_init(struct intel_dp *intel_dp) intel_dp->psr.source_support = true; + if (HAS_PANEL_REPLAY(dev_priv) && !intel_dp_is_edp(intel_dp)) + intel_dp->psr.source_panel_replay_support = true; + /* Set link_standby x link_off defaults */ if (DISPLAY_VER(dev_priv) < 12) /* For new platforms up to TGL let's respect VBT back again */ From patchwork Fri Jul 28 12:46:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Animesh Manna X-Patchwork-Id: 13331880 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9B70C001DE for ; Fri, 28 Jul 2023 12:56:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 777C410E214; Fri, 28 Jul 2023 12:56:35 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 59EB310E214 for ; Fri, 28 Jul 2023 12:56:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690548993; x=1722084993; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Jkyl2xTz4MosmdTyl6dc3XzBskc4+B3dF+ZFTfCZWUA=; b=R71HUqDLavuzuF5n9U4wGdnwLPUF9ANmNWsGEMmo6eWj/eJ9wd95z9kg 5G8RuR//qR2pi2tZ9u0DEpB6sKlKW3o/wyGObJ/jBjrcwzmYLFlcODVUh 4k1UEH+eiSa03LGrJFeAcUA2Vntl+oV9Innnngd+NlEiLwPbTmcbccRLn VANmfQ6AdJ0qwxAACzgnXVIKiaaabMUOyRE8K1fsQr3botHEO98AeOfYc rUk2U8Hd4c7MQ2dw2MDK4VpFlaAwSakgVpoAnbqsVVt2ltblCfQlZMpCi UghnEPuaH21Dx4LGYwTezg9dG8hYVjinlQ+rQhN/B7FZKT4JK6a8iMYbt Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10784"; a="358612310" X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="358612310" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2023 05:56:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10784"; a="727473164" X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="727473164" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga002.jf.intel.com with ESMTP; 28 Jul 2023 05:56:31 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Fri, 28 Jul 2023 18:16:08 +0530 Message-Id: <20230728124609.2911830-6-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20230728124609.2911830-1-animesh.manna@intel.com> References: <20230728124609.2911830-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 5/6] drm/i915/panelreplay: Enable panel replay dpcd initialization for DP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Due to similarity panel replay dpcd initialization got added in psr function which is specific for edp panel. This patch enables panel replay initialization for dp connector. Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7508e6c967e2..f6b00abe92d4 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2735,6 +2735,9 @@ void intel_psr_init(struct intel_dp *intel_dp) if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv))) return; + if (!intel_dp_is_edp(intel_dp)) + intel_psr_init_dpcd(intel_dp); + /* * HSW spec explicitly says PSR is tied to port A. * BDW+ platforms have a instance of PSR registers per transcoder but From patchwork Fri Jul 28 12:46:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Animesh Manna X-Patchwork-Id: 13331881 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E748BC001DE for ; Fri, 28 Jul 2023 12:56:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6FCC010E6C3; Fri, 28 Jul 2023 12:56:38 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6B20410E6C3 for ; Fri, 28 Jul 2023 12:56:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690548996; x=1722084996; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XyxM/GxR5U3mg7k7mhyEHa79IYw7xKYQjW0rvr6TD60=; b=k+/aauwnNhrszV8qjSSpNS5TRSCc2+u+2Yg22HBevZ8zh3i35tkL5hC1 NTts/j3nYAG0ZZtXokxoXAOAQpx4wOmqlZmC3IPNaA/kUT/wh3Cguzxk7 TlECVptO4l4y0W9Ivm7X0Q4DuPyV503P1gL4Lt8p42JTFkeIwYXFR90rH kNiougBRm/niDO5s9Isp80A4P3jjiSiJuPYPNNhOW/0LVfzFd1/pdW9UN botC3mMBgRlLyxKeku0uCRrvmk6I63/TRPZgYQTWIh8lF0hyltrlj2PfP Ox+g2I3uQxqa/GwRcd6fUtTLvu6BN3mpZoLVWrUnOEO94QEdt6H7LrW6m Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10784"; a="358612317" X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="358612317" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2023 05:56:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10784"; a="727473179" X-IronPort-AV: E=Sophos;i="6.01,237,1684825200"; d="scan'208";a="727473179" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orsmga002.jf.intel.com with ESMTP; 28 Jul 2023 05:56:34 -0700 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Date: Fri, 28 Jul 2023 18:16:09 +0530 Message-Id: <20230728124609.2911830-7-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20230728124609.2911830-1-animesh.manna@intel.com> References: <20230728124609.2911830-1-animesh.manna@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3 6/6] drm/i915/panelreplay: enable/disable panel replay X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" TRANS_DP2_CTL register is programmed to enable panel replay from source and sink is enabled through panel replay dpcd configuration address. Bspec: 1407940617 v1: Initial version. v2: - Use pr_* flags instead psr_* flags. [Jouni] - Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni] v3: cover letter updated and selective fetch condition check is added before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni] Note: Initial plan is to enable panel replay in full-screen live active frame update mode. In a incremental approach panel replay will be enabled in selctive update mode if there is any gap in curent implementation. Cc: Jouni Högander Signed-off-by: Animesh Manna --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 32 ++++++++++++++++--- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 1ff7e6c03b44..41fbd49393f3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1696,6 +1696,7 @@ struct intel_psr { u16 su_y_granularity; bool source_panel_replay_support; bool sink_panel_replay_support; + bool pr_enabled; u32 dc3co_exitline; u32 dc3co_exit_delay; struct delayed_work dc3co_work; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f6b00abe92d4..244fb336f6bc 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -599,8 +599,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u8 dpcd_val = DP_PSR_ENABLE; - /* Enable ALPM at sink for psr2 */ + if (intel_dp->psr.pr_enabled) { + drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, + DP_PANEL_REPLAY_ENABLE); + return; + } + if (intel_dp->psr.psr2_enabled) { + /* Enable ALPM at sink for psr2 */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); @@ -750,6 +756,18 @@ static int psr2_block_count(struct intel_dp *intel_dp) return psr2_block_count_lines(intel_dp) / 4; } +static void dg2_activate_panel_replay(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + if (intel_dp->psr.psr2_sel_fetch_enabled) + intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), + 0, ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE); + + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, + TRANS_DP2_PANEL_REPLAY_ENABLE); +} + static void hsw_activate_psr2(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -1361,8 +1379,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp) lockdep_assert_held(&intel_dp->psr.lock); - /* psr1 and psr2 are mutually exclusive.*/ - if (intel_dp->psr.psr2_enabled) + /* psr1, psr2 and panel-replay are mutually exclusive.*/ + if (intel_dp->psr.pr_enabled) + dg2_activate_panel_replay(intel_dp); + else if (intel_dp->psr.psr2_enabled) hsw_activate_psr2(intel_dp); else hsw_activate_psr1(intel_dp); @@ -1541,6 +1561,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); intel_dp->psr.psr2_enabled = crtc_state->has_psr2; + intel_dp->psr.pr_enabled = crtc_state->has_pr; intel_dp->psr.busy_frontbuffer_bits = 0; intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; intel_dp->psr.transcoder = crtc_state->cpu_transcoder; @@ -1586,7 +1607,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp) return; } - if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.pr_enabled) { + intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), + TRANS_DP2_PANEL_REPLAY_ENABLE, 0); + } else if (intel_dp->psr.psr2_enabled) { tgl_disallow_dc3co_on_psr2_exit(intel_dp); val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),