From patchwork Mon Jul 31 09:30:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13334161 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 649A5C001DF for ; Mon, 31 Jul 2023 09:31:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232260AbjGaJbL (ORCPT ); Mon, 31 Jul 2023 05:31:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231297AbjGaJa6 (ORCPT ); Mon, 31 Jul 2023 05:30:58 -0400 Received: from h1.cmg1.smtp.forpsi.com (h1.cmg1.smtp.forpsi.com [81.2.195.162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C82F199 for ; Mon, 31 Jul 2023 02:30:48 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id QPEjqwTxdPm6CQPEkqqHpc; Mon, 31 Jul 2023 11:30:46 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1690795846; bh=AQGXBy7vpP7NRtHMfFfektc5a+kpqauMMvPT8YLPz4I=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=nsYdX1EF3tJlUGI5wpKmWWRWh9E9lS8QN+v65uI/yD9w/rGE8MiyT6HGB/diG2PhS oFYBqbF2wXDwktY+7L7Xi1f0s8D90GSE5lVuFrFpSrpnW+SMJJtWuX64dS8tzgH67Q 8HXSYiHwG6yffMu4NRifCkq7yU3GRl4PFwqX7bly0uBoazx0EnaXKOF8GJf34CKHpp IbtlX+GKj8IHMjbDywETVfv+7VhsiA9udhCyXWMyC6evoOhveYndcSqNLFoC+VfdmI KEKYnJyWOnl41j512UdIvKHKcxjAtw4zT4D9EfAHHWhwyVv6YsFJB4vKpBAruYTEal TfxX3a9EVtqvA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1690795846; bh=AQGXBy7vpP7NRtHMfFfektc5a+kpqauMMvPT8YLPz4I=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=nsYdX1EF3tJlUGI5wpKmWWRWh9E9lS8QN+v65uI/yD9w/rGE8MiyT6HGB/diG2PhS oFYBqbF2wXDwktY+7L7Xi1f0s8D90GSE5lVuFrFpSrpnW+SMJJtWuX64dS8tzgH67Q 8HXSYiHwG6yffMu4NRifCkq7yU3GRl4PFwqX7bly0uBoazx0EnaXKOF8GJf34CKHpp IbtlX+GKj8IHMjbDywETVfv+7VhsiA9udhCyXWMyC6evoOhveYndcSqNLFoC+VfdmI KEKYnJyWOnl41j512UdIvKHKcxjAtw4zT4D9EfAHHWhwyVv6YsFJB4vKpBAruYTEal TfxX3a9EVtqvA== Date: Mon, 31 Jul 2023 11:30:45 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v5 1/7] usb: dwc3: dwc3-octeon: Convert to glue driver Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfLRrfpUdRpgDrOtJ/kM5h/XfOB6pfYUGb9XG11zId09rqFeJHvbxLrv0UtRpW90a5XWXP+WK/MwYsQ6f8mYW9Lp6M2V5IDrdthdETEO7X1/29MEzUMFI 7MxMOYCCdj1L+fLtjdjXJyF5S8YyNhLU8goajRbTWiIE1FFIkG54kXcqRdbOfhqmVBdIjSehvLInO6vmeqQJ81jucX/0xSIDTyza004OyXDjGSZE30g1HKp8 6CHjk+phClF6Tl7SyXqSwMpcd4BZP0OOwDlHTzasiO0ztyYDdc44wBLD4Z/UFOtHxOuf0RRzVCsEyq1VDbDEPy0TpqF9MCamq4XrhxU4/h2YvnlKZmYxZpi+ FnOleQ7a Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl DWC3 as implemented in Cavium SoC is using UCTL bridge unit between I/O interconnect and USB controller. Currently there is no bond with dwc3 core code, so if anything goes wrong in UCTL setup dwc3 is left in reset, which leads to bus error while trying to read any device register. Thus any failure in UCTL initialization ends with kernel panic. To avoid this move Octeon DWC3 glue code from arch/mips and make it proper glue driver which is used instead of dwc3-of-simple. Signed-off-by: Ladislav Michl Acked-by: Thomas Bogendoerfer Acked-by: Thinh Nguyen --- CHANGES: - v2: squashed move and glue conversion patch, fixed sparse warning and formatting issue. Set private data at the end of probe. Clear drvdata on remove. Added host mode only notice. Collected ack for move from arch/mips. - v3: more descriptive commit message, dropped unrelated changes - v4: rename dwc3_data to dwc3_octeon, collect Thinh's ack. - v5: none arch/mips/cavium-octeon/Makefile | 1 - arch/mips/cavium-octeon/octeon-platform.c | 1 - drivers/usb/dwc3/Kconfig | 10 ++ drivers/usb/dwc3/Makefile | 1 + .../usb/dwc3/dwc3-octeon.c | 105 ++++++++++-------- drivers/usb/dwc3/dwc3-of-simple.c | 1 - 6 files changed, 68 insertions(+), 51 deletions(-) rename arch/mips/cavium-octeon/octeon-usb.c => drivers/usb/dwc3/dwc3-octeon.c (91%) diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 7c02e542959a..2a5926578841 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -18,4 +18,3 @@ obj-y += crypto/ obj-$(CONFIG_MTD) += flash_setup.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o -obj-$(CONFIG_USB) += octeon-usb.o diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index ce05c0dd3acd..235c77ce7b18 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -450,7 +450,6 @@ static const struct of_device_id octeon_ids[] __initconst = { { .compatible = "cavium,octeon-3860-bootbus", }, { .compatible = "cavium,mdio-mux", }, { .compatible = "gpio-leds", }, - { .compatible = "cavium,octeon-7130-usb-uctl", }, {}, }; diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index be954a9abbe0..98efcbb76c88 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -168,4 +168,14 @@ config USB_DWC3_AM62 The Designware Core USB3 IP is programmed to operate in in USB 2.0 mode only. Say 'Y' or 'M' here if you have one such device + +config USB_DWC3_OCTEON + tristate "Cavium Octeon Platforms" + depends on CAVIUM_OCTEON_SOC || COMPILE_TEST + default USB_DWC3 + help + Support Cavium Octeon platforms with DesignWare Core USB3 IP. + Only the host mode is currently supported. + Say 'Y' or 'M' here if you have one such device. + endif diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 9f66bd82b639..fe1493d4bbe5 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -54,3 +54,4 @@ obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o +obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/drivers/usb/dwc3/dwc3-octeon.c similarity index 91% rename from arch/mips/cavium-octeon/octeon-usb.c rename to drivers/usb/dwc3/dwc3-octeon.c index 2add435ad038..7134cdfc0fb6 100644 --- a/arch/mips/cavium-octeon/octeon-usb.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -187,7 +187,10 @@ #define USBDRD_UCTL_ECC 0xf0 #define USBDRD_UCTL_SPARE1 0xf8 -static DEFINE_MUTEX(dwc3_octeon_clocks_mutex); +struct dwc3_octeon { + struct device *dev; + void __iomem *base; +}; #ifdef CONFIG_CAVIUM_OCTEON_SOC #include @@ -233,6 +236,11 @@ static inline uint64_t dwc3_octeon_readq(void __iomem *addr) static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) { } static inline void dwc3_octeon_config_gpio(int index, int gpio) { } + +static uint64_t octeon_get_io_clock_rate(void) +{ + return 150000000; +} #endif static int dwc3_octeon_get_divider(void) @@ -494,58 +502,59 @@ static void __init dwc3_octeon_phy_reset(void __iomem *base) dwc3_octeon_writeq(uctl_ctl_reg, val); } -static int __init dwc3_octeon_device_init(void) +static int dwc3_octeon_probe(struct platform_device *pdev) { - const char compat_node_name[] = "cavium,octeon-7130-usb-uctl"; - struct platform_device *pdev; - struct device_node *node; - struct resource *res; - void __iomem *base; + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct dwc3_octeon *octeon; + int err; - /* - * There should only be three universal controllers, "uctl" - * in the device tree. Two USB and a SATA, which we ignore. - */ - node = NULL; - do { - node = of_find_node_by_name(node, "uctl"); - if (!node) - return -ENODEV; - - if (of_device_is_compatible(node, compat_node_name)) { - pdev = of_find_device_by_node(node); - if (!pdev) - return -ENODEV; - - /* - * The code below maps in the registers necessary for - * setting up the clocks and reseting PHYs. We must - * release the resources so the dwc3 subsystem doesn't - * know the difference. - */ - base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (IS_ERR(base)) { - put_device(&pdev->dev); - return PTR_ERR(base); - } + octeon = devm_kzalloc(dev, sizeof(*octeon), GFP_KERNEL); + if (!octeon) + return -ENOMEM; - mutex_lock(&dwc3_octeon_clocks_mutex); - if (dwc3_octeon_clocks_start(&pdev->dev, base) == 0) - dev_info(&pdev->dev, "clocks initialized.\n"); - dwc3_octeon_set_endian_mode(base); - dwc3_octeon_phy_reset(base); - mutex_unlock(&dwc3_octeon_clocks_mutex); - devm_iounmap(&pdev->dev, base); - devm_release_mem_region(&pdev->dev, res->start, - resource_size(res)); - put_device(&pdev->dev); - } - } while (node != NULL); + octeon->dev = dev; + octeon->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(octeon->base)) + return PTR_ERR(octeon->base); - return 0; + err = dwc3_octeon_clocks_start(dev, octeon->base); + if (err) + return err; + + dwc3_octeon_set_endian_mode(octeon->base); + dwc3_octeon_phy_reset(octeon->base); + + platform_set_drvdata(pdev, octeon); + + return of_platform_populate(node, NULL, NULL, dev); +} + +static void dwc3_octeon_remove(struct platform_device *pdev) +{ + struct dwc3_octeon *octeon = platform_get_drvdata(pdev); + + of_platform_depopulate(octeon->dev); + platform_set_drvdata(pdev, NULL); } -device_initcall(dwc3_octeon_device_init); +static const struct of_device_id dwc3_octeon_of_match[] = { + { .compatible = "cavium,octeon-7130-usb-uctl" }, + { }, +}; +MODULE_DEVICE_TABLE(of, dwc3_octeon_of_match); + +static struct platform_driver dwc3_octeon_driver = { + .probe = dwc3_octeon_probe, + .remove_new = dwc3_octeon_remove, + .driver = { + .name = "dwc3-octeon", + .of_match_table = dwc3_octeon_of_match, + }, +}; +module_platform_driver(dwc3_octeon_driver); + +MODULE_ALIAS("platform:dwc3-octeon"); MODULE_AUTHOR("David Daney "); MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("USB driver for OCTEON III SoC"); +MODULE_DESCRIPTION("DesignWare USB3 OCTEON III Glue Layer"); diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c index 7e6ad8fe61a5..d1539fc9eabd 100644 --- a/drivers/usb/dwc3/dwc3-of-simple.c +++ b/drivers/usb/dwc3/dwc3-of-simple.c @@ -170,7 +170,6 @@ static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = { static const struct of_device_id of_dwc3_simple_match[] = { { .compatible = "rockchip,rk3399-dwc3" }, - { .compatible = "cavium,octeon-7130-usb-uctl" }, { .compatible = "sprd,sc9860-dwc3" }, { .compatible = "allwinner,sun50i-h6-dwc3" }, { .compatible = "hisilicon,hi3670-dwc3" }, From patchwork Mon Jul 31 09:31:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13334162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1933FC04FDF for ; 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a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1690795882; bh=zyvVzoejlo3FqR7ayhT/w66XsBh9AM5Bu614Jh/8fTs=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=qVZmkMMHXEoKJKy3ZPkc9LuKKsWT2vQcXN7PVkvf5cPL/7IFACAXtLWKMxroA3aYx Isc7VLxh+bGx7ZeD9Vne3CYHZ/g5ZmTFu4rJLbnNvqwsUmAGxJFkN4yzg5uE4O+pym EZ5HoVWZCmzS/vk9C2rm/FJrLR30r/vcugJHaIrX48kxQJxc42AHvYqVyOhFtyQnMf 1pR7T4QjHBXTC3VRG894iuHNlcknmJiLkGLph9dc8fbSbwU5p7NbhjHsqfhGqBBnZv d5FirYPi3g0hUparDhaKGDu0YltFqUJmNpYLqcFI8S/tDTRuN4oyvTE7RLWsmsMY2q mw1Sif+Wj2YtA== Date: Mon, 31 Jul 2023 11:31:21 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v5 2/7] usb: dwc3: dwc3-octeon: Use _ULL bitfields defines Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfBpHXL+vnvCjyDA/B27KBP3vbHfIk8ksxxDfj8qyIGW78CAJhpndfUsAKED4wTUcdrRwiWCflb9Iuu7P3fl2wHiiAkTcFtjOb0PuKPASpCnRDpvpqxK1 s7DJqVajGM47u31jK+bkfJId0fpfI833vSeloml2PWzqHp5hQz+g6rA8YTutb50IVmce/5fCukryPji4hctByupTzDhrxnnyXf/NUpF5d4R3KEgqJG4qxGum wFDZwRQEuFXo4LFiLuApqYdhbexmLMf+mizOAsfBRqHiinxTJ/D/hicWhC08ixAuN7fTyTW1MQn3krPBvzLIEg9YrNBgEUYP2kzcXofMeSuQ86h7g+5LtgfX K+y1qwP6 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl While driver is intended to run on 64bit machines, it is compile time tested for 32bit targets as well. Here shift count overflow is reported for bits greater than 31, so use _ULL versions of BIT and GENMASK macros to silence these warnings. Signed-off-by: Ladislav Michl Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202307260537.MROrhVNM-lkp@intel.com/ Acked-by: Thinh Nguyen Reviewed-by: Philippe Mathieu-Daudé --- CHANGES: -v5: new patch drivers/usb/dwc3/dwc3-octeon.c | 78 +++++++++++++++++----------------- 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 7134cdfc0fb6..69fe50cfa719 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -24,9 +24,9 @@ /* BIST fast-clear mode select. A BIST run with this bit set * clears all entries in USBH RAMs to 0x0. */ -# define USBDRD_UCTL_CTL_CLEAR_BIST BIT(63) +# define USBDRD_UCTL_CTL_CLEAR_BIST BIT_ULL(63) /* 1 = Start BIST and cleared by hardware */ -# define USBDRD_UCTL_CTL_START_BIST BIT(62) +# define USBDRD_UCTL_CTL_START_BIST BIT_ULL(62) /* Reference clock select for SuperSpeed and HighSpeed PLLs: * 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock * 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock @@ -35,32 +35,32 @@ * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock & * HighSpeed PLL uses PLL_REF_CLK for reference clck */ -# define USBDRD_UCTL_CTL_REF_CLK_SEL GENMASK(61, 60) +# define USBDRD_UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60) /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */ -# define USBDRD_UCTL_CTL_SSC_EN BIT(59) +# define USBDRD_UCTL_CTL_SSC_EN BIT_ULL(59) /* Spread-spectrum clock modulation range: * 0x0 = -4980 ppm downspread * 0x1 = -4492 ppm downspread * 0x2 = -4003 ppm downspread * 0x3 - 0x7 = Reserved */ -# define USBDRD_UCTL_CTL_SSC_RANGE GENMASK(58, 56) +# define USBDRD_UCTL_CTL_SSC_RANGE GENMASK_ULL(58, 56) /* Enable non-standard oscillator frequencies: * [55:53] = modules -1 * [52:47] = 2's complement push amount, 0 = Feature disabled */ -# define USBDRD_UCTL_CTL_SSC_REF_CLK_SEL GENMASK(55, 47) +# define USBDRD_UCTL_CTL_SSC_REF_CLK_SEL GENMASK_ULL(55, 47) /* Reference clock multiplier for non-standard frequencies: * 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 * 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 * 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 * Other Values = Reserved */ -# define USBDRD_UCTL_CTL_MPLL_MULTIPLIER GENMASK(46, 40) +# define USBDRD_UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40) /* Enable reference clock to prescaler for SuperSpeed functionality. * Should always be set to "1" */ -# define USBDRD_UCTL_CTL_REF_SSP_EN BIT(39) +# define USBDRD_UCTL_CTL_REF_SSP_EN BIT_ULL(39) /* Divide the reference clock by 2 before entering the * REF_CLK_FSEL divider: * If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal @@ -68,21 +68,21 @@ * 0x1 = DLMC_REF_CLK* is 125MHz * 0x0 = DLMC_REF_CLK* is another supported frequency */ -# define USBDRD_UCTL_CTL_REF_CLK_DIV2 BIT(38) +# define USBDRD_UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38) /* Select reference clock freqnuency for both PLL blocks: * 0x27 = REF_CLK_SEL is 0x0 or 0x1 * 0x07 = REF_CLK_SEL is 0x2 or 0x3 */ -# define USBDRD_UCTL_CTL_REF_CLK_FSEL GENMASK(37, 32) +# define USBDRD_UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32) /* Controller clock enable. */ -# define USBDRD_UCTL_CTL_H_CLK_EN BIT(30) +# define USBDRD_UCTL_CTL_H_CLK_EN BIT_ULL(30) /* Select bypass input to controller clock divider: * 0x0 = Use divided coprocessor clock from H_CLKDIV * 0x1 = Use clock from GPIO pins */ -# define USBDRD_UCTL_CTL_H_CLK_BYP_SEL BIT(29) +# define USBDRD_UCTL_CTL_H_CLK_BYP_SEL BIT_ULL(29) /* Reset controller clock divider. */ -# define USBDRD_UCTL_CTL_H_CLKDIV_RST BIT(28) +# define USBDRD_UCTL_CTL_H_CLKDIV_RST BIT_ULL(28) /* Clock divider select: * 0x0 = divide by 1 * 0x1 = divide by 2 @@ -93,29 +93,29 @@ * 0x6 = divide by 24 * 0x7 = divide by 32 */ -# define USBDRD_UCTL_CTL_H_CLKDIV_SEL GENMASK(26, 24) +# define USBDRD_UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24) /* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */ -# define USBDRD_UCTL_CTL_USB3_PORT_PERM_ATTACH BIT(21) +# define USBDRD_UCTL_CTL_USB3_PORT_PERM_ATTACH BIT_ULL(21) /* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */ -# define USBDRD_UCTL_CTL_USB2_PORT_PERM_ATTACH BIT(20) +# define USBDRD_UCTL_CTL_USB2_PORT_PERM_ATTACH BIT_ULL(20) /* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */ -# define USBDRD_UCTL_CTL_USB3_PORT_DISABLE BIT(18) +# define USBDRD_UCTL_CTL_USB3_PORT_DISABLE BIT_ULL(18) /* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */ -# define USBDRD_UCTL_CTL_USB2_PORT_DISABLE BIT(16) +# define USBDRD_UCTL_CTL_USB2_PORT_DISABLE BIT_ULL(16) /* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */ -# define USBDRD_UCTL_CTL_SS_POWER_EN BIT(14) +# define USBDRD_UCTL_CTL_SS_POWER_EN BIT_ULL(14) /* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */ -# define USBDRD_UCTL_CTL_HS_POWER_EN BIT(12) +# define USBDRD_UCTL_CTL_HS_POWER_EN BIT_ULL(12) /* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */ -# define USBDRD_UCTL_CTL_CSCLK_EN BIT(4) +# define USBDRD_UCTL_CTL_CSCLK_EN BIT_ULL(4) /* Controller mode: 0x0 = Host, 0x1 = Device */ -# define USBDRD_UCTL_CTL_DRD_MODE BIT(3) +# define USBDRD_UCTL_CTL_DRD_MODE BIT_ULL(3) /* PHY reset */ -# define USBDRD_UCTL_CTL_UPHY_RST BIT(2) +# define USBDRD_UCTL_CTL_UPHY_RST BIT_ULL(2) /* Software reset UAHC */ -# define USBDRD_UCTL_CTL_UAHC_RST BIT(1) +# define USBDRD_UCTL_CTL_UAHC_RST BIT_ULL(1) /* Software resets UCTL */ -# define USBDRD_UCTL_CTL_UCTL_RST BIT(0) +# define USBDRD_UCTL_CTL_UCTL_RST BIT_ULL(0) #define USBDRD_UCTL_BIST_STATUS 0x08 #define USBDRD_UCTL_SPARE0 0x10 @@ -130,59 +130,59 @@ */ #define USBDRD_UCTL_HOST_CFG 0xe0 /* Indicates minimum value of all received BELT values */ -# define USBDRD_UCTL_HOST_CFG_HOST_CURRENT_BELT GENMASK(59, 48) +# define USBDRD_UCTL_HOST_CFG_HOST_CURRENT_BELT GENMASK_ULL(59, 48) /* HS jitter adjustment */ -# define USBDRD_UCTL_HOST_CFG_FLA GENMASK(37, 32) +# define USBDRD_UCTL_HOST_CFG_FLA GENMASK_ULL(37, 32) /* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */ -# define USBDRD_UCTL_HOST_CFG_BME BIT(28) +# define USBDRD_UCTL_HOST_CFG_BME BIT_ULL(28) /* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */ -# define USBDRD_UCTL_HOST_OCI_EN BIT(27) +# define USBDRD_UCTL_HOST_OCI_EN BIT_ULL(27) /* Overcurrent sene selection: * 0x0 = Overcurrent indication from off-chip is active-low * 0x1 = Overcurrent indication from off-chip is active-high */ -# define USBDRD_UCTL_HOST_OCI_ACTIVE_HIGH_EN BIT(26) +# define USBDRD_UCTL_HOST_OCI_ACTIVE_HIGH_EN BIT_ULL(26) /* Port power control enable: 0x0 = unavailable, 0x1 = available */ -# define USBDRD_UCTL_HOST_PPC_EN BIT(25) +# define USBDRD_UCTL_HOST_PPC_EN BIT_ULL(25) /* Port power control sense selection: * 0x0 = Port power to off-chip is active-low * 0x1 = Port power to off-chip is active-high */ -# define USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN BIT(24) +# define USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN BIT_ULL(24) /* * UCTL Shim Features Register */ #define USBDRD_UCTL_SHIM_CFG 0xe8 /* Out-of-bound UAHC register access: 0 = read, 1 = write */ -# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_WRN BIT(63) +# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_WRN BIT_ULL(63) /* SRCID error log for out-of-bound UAHC register access: * [59:58] = chipID * [57] = Request source: 0 = core, 1 = NCB-device * [56:51] = Core/NCB-device number, [56] always 0 for NCB devices * [50:48] = SubID */ -# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_OSRC GENMASK(59, 48) +# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_OSRC GENMASK_ULL(59, 48) /* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */ -# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_WRN BIT(47) +# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_WRN BIT_ULL(47) /* Encoded error type for bad UAHC DMA */ -# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_TYPE GENMASK(43, 40) +# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_TYPE GENMASK_ULL(43, 40) /* Select the IOI read command used by DMA accesses */ -# define USBDRD_UCTL_SHIM_CFG_DMA_READ_CMD BIT(12) +# define USBDRD_UCTL_SHIM_CFG_DMA_READ_CMD BIT_ULL(12) /* Select endian format for DMA accesses to the L2C: * 0x0 = Little endian * 0x1 = Big endian * 0x2 = Reserved * 0x3 = Reserved */ -# define USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK(9, 8) +# define USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8) /* Select endian format for IOI CSR access to UAHC: * 0x0 = Little endian * 0x1 = Big endian * 0x2 = Reserved * 0x3 = Reserved */ -# define USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK(1, 0) +# define USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0) #define USBDRD_UCTL_ECC 0xf0 #define USBDRD_UCTL_SPARE1 0xf8 From patchwork Mon Jul 31 09:31:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13334168 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36716C001E0 for ; Mon, 31 Jul 2023 09:32:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232357AbjGaJcY (ORCPT ); Mon, 31 Jul 2023 05:32:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232355AbjGaJb4 (ORCPT ); Mon, 31 Jul 2023 05:31:56 -0400 Received: from h1.cmg2.smtp.forpsi.com (h1.cmg2.smtp.forpsi.com [81.2.195.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 559FC126 for ; Mon, 31 Jul 2023 02:31:48 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id QPFiq0lZmv5uIQPFjqCu2p; Mon, 31 Jul 2023 11:31:47 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1690795907; bh=ejQNu4WaAC5/i3r4ni9jXUpPtWCphTBUKHGIV1oS+Es=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=wWNbnff0ZGavtkCVSjvEMIo3BM47uINeewbsWB8Pmt3bt9gLKooxo7gCqifQVwyPY oRdTdXxszSoaqcbLUUVmX8walu+4XvKTMXABR+L1slXEV3Kk8vLaXJrCDwst43DP8F Lb2CeE6q+f1GuZEu6iTGFwWH14gtjwG0KJBI7PQFkZ/rXeaXFWgEj8MO1qiS2h0umO q+9Gyu/T65z7W5J4kjevfzfuyjwvghRXn9EpjRzT5Tme38ntIG+QlxM15cwKaWAIgo 2HvUtLoUuvEFnXsIh8XYfv2zdCIDS5bGwkYWsp7dFpIcH2NU3rtvO0xuL2tzDYV7X2 ljx6EKytc0eJg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1690795907; bh=ejQNu4WaAC5/i3r4ni9jXUpPtWCphTBUKHGIV1oS+Es=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=wWNbnff0ZGavtkCVSjvEMIo3BM47uINeewbsWB8Pmt3bt9gLKooxo7gCqifQVwyPY oRdTdXxszSoaqcbLUUVmX8walu+4XvKTMXABR+L1slXEV3Kk8vLaXJrCDwst43DP8F Lb2CeE6q+f1GuZEu6iTGFwWH14gtjwG0KJBI7PQFkZ/rXeaXFWgEj8MO1qiS2h0umO q+9Gyu/T65z7W5J4kjevfzfuyjwvghRXn9EpjRzT5Tme38ntIG+QlxM15cwKaWAIgo 2HvUtLoUuvEFnXsIh8XYfv2zdCIDS5bGwkYWsp7dFpIcH2NU3rtvO0xuL2tzDYV7X2 ljx6EKytc0eJg== Date: Mon, 31 Jul 2023 11:31:46 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v5 3/7] usb: dwc3: dwc3-octeon: Pass dwc3_octeon to setup functions Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfKaZp2d7YTiWz14zlRtMEtkytLrK9QOyIOtBr0V4GGUwshynwMrNafveOkks+uRpldnAszgys7NkRl687c7P06JNeywwAZgJRBylFLXcwGas9lelgBO7 H+7qQc9WPTTx2PBLFYbWXi0lj4RNsG7ueNFsautf4w/L6TSQx6NJHkeU1kpmy5IADlJom3dCB+2GrDsXAh4TFRJ7HCpWnq+7pinSSilW6TzhYjAlq2gE6rQr 7z3yzizKTdqhINkLVqxPjCWgMLy+P3sazUSTPEZdYE/W0VZ5xP4kM84SGuq3TMBDeTXFJBRIBZ7sXsZcWXGC+sMACn/AXy0rVO+glsuGpGQ4/jnzWEswZf8n bW+MmpVE Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Pass dwc3_octeon instead of just the base. It fits with the function names and it requires less change in the future if access to dwc3_octeon is needed. Signed-off-by: Ladislav Michl Reviewed-by: Philippe Mathieu-Daudé Acked-by: Thinh Nguyen --- CHANGES: - v4: new patch - v5: Philippe's review tag drivers/usb/dwc3/dwc3-octeon.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 69fe50cfa719..24e75881b5cf 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -300,12 +300,13 @@ static int dwc3_octeon_config_power(struct device *dev, void __iomem *base) return 0; } -static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) +static int dwc3_octeon_clocks_start(struct dwc3_octeon *octeon) { int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; u32 clock_rate; u64 val; - void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; + struct device *dev = octeon->dev; + void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL; if (dev->of_node) { const char *ss_clock_type; @@ -452,8 +453,8 @@ static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) /* Step 8b: Wait 10 controller-clock cycles. */ udelay(10); - /* Steo 8c: Setup power-power control. */ - if (dwc3_octeon_config_power(dev, base)) + /* Step 8c: Setup power control. */ + if (dwc3_octeon_config_power(dev, octeon->base)) return -EINVAL; /* Step 8d: Deassert UAHC reset signal. */ @@ -477,10 +478,10 @@ static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) return 0; } -static void __init dwc3_octeon_set_endian_mode(void __iomem *base) +static void dwc3_octeon_set_endian_mode(struct dwc3_octeon *octeon) { u64 val; - void __iomem *uctl_shim_cfg_reg = base + USBDRD_UCTL_SHIM_CFG; + void __iomem *uctl_shim_cfg_reg = octeon->base + USBDRD_UCTL_SHIM_CFG; val = dwc3_octeon_readq(uctl_shim_cfg_reg); val &= ~USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE; @@ -492,10 +493,10 @@ static void __init dwc3_octeon_set_endian_mode(void __iomem *base) dwc3_octeon_writeq(uctl_shim_cfg_reg, val); } -static void __init dwc3_octeon_phy_reset(void __iomem *base) +static void dwc3_octeon_phy_reset(struct dwc3_octeon *octeon) { u64 val; - void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; + void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL; val = dwc3_octeon_readq(uctl_ctl_reg); val &= ~USBDRD_UCTL_CTL_UPHY_RST; @@ -518,12 +519,12 @@ static int dwc3_octeon_probe(struct platform_device *pdev) if (IS_ERR(octeon->base)) return PTR_ERR(octeon->base); - err = dwc3_octeon_clocks_start(dev, octeon->base); + err = dwc3_octeon_clocks_start(octeon); if (err) return err; - dwc3_octeon_set_endian_mode(octeon->base); - dwc3_octeon_phy_reset(octeon->base); + dwc3_octeon_set_endian_mode(octeon); + dwc3_octeon_phy_reset(octeon); platform_set_drvdata(pdev, octeon); From patchwork Mon Jul 31 09:32:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13334169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09AA4C001E0 for ; Mon, 31 Jul 2023 09:33:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230506AbjGaJdF (ORCPT ); Mon, 31 Jul 2023 05:33:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232358AbjGaJcZ (ORCPT ); Mon, 31 Jul 2023 05:32:25 -0400 Received: from h1.cmg1.smtp.forpsi.com (h1.cmg1.smtp.forpsi.com [81.2.195.162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DC6F10FA for ; Mon, 31 Jul 2023 02:32:19 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id QPGCqwV2zPm6CQPGEqqIHT; Mon, 31 Jul 2023 11:32:18 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1690795938; bh=nWemIEuN8F90ycMXo5G6slMMbUU2sM5EfPT8NBTPH+w=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=tPJrgk8lnUJXstbdwX1HVnU9HrDu83n0Wqi/T1wobk9a7u/2berlAmLDoHvs0ETbC 6n996SaL93cnvSxiCKFg12tssBD/uSXgPV1aZRV0kYm3v8IAuCyuPZP/XzczKi4Hqu o2YImRhZZHdhokB/gpFhV1mx1xrH9LQ0mv12q+wLGujSv+bcYdXvRWHSn36eSZoSfu 6aLWr5kpl1RqH1dy23MplV8JPHX/F7RSG3BupMOXW5eFzo+CGyaau+N6SAXe6SemlK uZC8Sx4oknIa0UugQBEcmMDQ2f3M/egP//axTSU6vumyTo04QBWw0dHaWnRzBYWUeK MPx8pCXB4awMA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1690795938; bh=nWemIEuN8F90ycMXo5G6slMMbUU2sM5EfPT8NBTPH+w=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=tPJrgk8lnUJXstbdwX1HVnU9HrDu83n0Wqi/T1wobk9a7u/2berlAmLDoHvs0ETbC 6n996SaL93cnvSxiCKFg12tssBD/uSXgPV1aZRV0kYm3v8IAuCyuPZP/XzczKi4Hqu o2YImRhZZHdhokB/gpFhV1mx1xrH9LQ0mv12q+wLGujSv+bcYdXvRWHSn36eSZoSfu 6aLWr5kpl1RqH1dy23MplV8JPHX/F7RSG3BupMOXW5eFzo+CGyaau+N6SAXe6SemlK uZC8Sx4oknIa0UugQBEcmMDQ2f3M/egP//axTSU6vumyTo04QBWw0dHaWnRzBYWUeK MPx8pCXB4awMA== Date: Mon, 31 Jul 2023 11:32:16 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v5 4/7] usb: dwc3: dwc3-octeon: Avoid half-initialized controller state Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfJvX+DbKj70iVO55h/ufyqck4oKCkcAtuowsxZyJcQ+RO55f2pB5igYfDhqg5RhMSr8ReDu9kD6h4C6wSQSR7b+rufVFVr7TzBPy1+I2dM3S40sS2xKY PyayaoR333GNTqDljQfUn6G7Yn5v6nv2wJdNX4Ig9/tROAfl4bQNknGEAxXzBItvh+0LQSj1csVXlxsla3J3SK0LJa1Fk9c74wmEpnQmQDvTx7SgP2H63yAg 31FQe0EB4pfAdiUGOS9NHSVBA6qCe8oFTPtqEyHhXt54rxyYXF3gjU+jfywaLPIA2zieLKxHdwFm4r0ebi8va/1e1Y1cVx7M2kNL+1PU4Gm5Z1u8hoRS8e5Y n+roVJO+ Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Power gpio configuration is done from the middle of dwc3_octeon_clocks_start leaving hardware in half-initialized state if it fails. As that indicates dwc3_octeon_clocks_start does more than just initialize the clocks rename it appropriately and verify power gpio configuration in advance at the beginning of device probe. Signed-off-by: Ladislav Michl Acked-by: Thinh Nguyen --- CHANGES: - v4: new patch - v5: use uintptr_t instead of u64 to retype base address to make 32bit compilers happy. drivers/usb/dwc3/dwc3-octeon.c | 90 ++++++++++++++++------------------ 1 file changed, 43 insertions(+), 47 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 24e75881b5cf..0dc45dda134c 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -192,6 +192,8 @@ struct dwc3_octeon { void __iomem *base; }; +#define DWC3_GPIO_POWER_NONE (-1) + #ifdef CONFIG_CAVIUM_OCTEON_SOC #include static inline uint64_t dwc3_octeon_readq(void __iomem *addr) @@ -258,55 +260,15 @@ static int dwc3_octeon_get_divider(void) return div; } -static int dwc3_octeon_config_power(struct device *dev, void __iomem *base) -{ - uint32_t gpio_pwr[3]; - int gpio, len, power_active_low; - struct device_node *node = dev->of_node; - u64 val; - void __iomem *uctl_host_cfg_reg = base + USBDRD_UCTL_HOST_CFG; - - if (of_find_property(node, "power", &len) != NULL) { - if (len == 12) { - of_property_read_u32_array(node, "power", gpio_pwr, 3); - power_active_low = gpio_pwr[2] & 0x01; - gpio = gpio_pwr[1]; - } else if (len == 8) { - of_property_read_u32_array(node, "power", gpio_pwr, 2); - power_active_low = 0; - gpio = gpio_pwr[1]; - } else { - dev_err(dev, "invalid power configuration\n"); - return -EINVAL; - } - dwc3_octeon_config_gpio(((u64)base >> 24) & 1, gpio); - - /* Enable XHCI power control and set if active high or low. */ - val = dwc3_octeon_readq(uctl_host_cfg_reg); - val |= USBDRD_UCTL_HOST_PPC_EN; - if (power_active_low) - val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; - else - val |= USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; - dwc3_octeon_writeq(uctl_host_cfg_reg, val); - } else { - /* Disable XHCI power control and set if active high. */ - val = dwc3_octeon_readq(uctl_host_cfg_reg); - val &= ~USBDRD_UCTL_HOST_PPC_EN; - val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; - dwc3_octeon_writeq(uctl_host_cfg_reg, val); - dev_info(dev, "power control disabled\n"); - } - return 0; -} - -static int dwc3_octeon_clocks_start(struct dwc3_octeon *octeon) +static int dwc3_octeon_setup(struct dwc3_octeon *octeon, + int power_gpio, int power_active_low) { int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; u32 clock_rate; u64 val; struct device *dev = octeon->dev; void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL; + void __iomem *uctl_host_cfg_reg = octeon->base + USBDRD_UCTL_HOST_CFG; if (dev->of_node) { const char *ss_clock_type; @@ -454,8 +416,21 @@ static int dwc3_octeon_clocks_start(struct dwc3_octeon *octeon) udelay(10); /* Step 8c: Setup power control. */ - if (dwc3_octeon_config_power(dev, octeon->base)) - return -EINVAL; + val = dwc3_octeon_readq(uctl_host_cfg_reg); + val |= USBDRD_UCTL_HOST_PPC_EN; + if (power_gpio == DWC3_GPIO_POWER_NONE) { + val &= ~USBDRD_UCTL_HOST_PPC_EN; + } else { + val |= USBDRD_UCTL_HOST_PPC_EN; + dwc3_octeon_config_gpio(((__force uintptr_t)octeon->base >> 24) & 1, + power_gpio); + dev_dbg(dev, "power control is using gpio%d\n", power_gpio); + } + if (power_active_low) + val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; + else + val |= USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; + dwc3_octeon_writeq(uctl_host_cfg_reg, val); /* Step 8d: Deassert UAHC reset signal. */ val = dwc3_octeon_readq(uctl_ctl_reg); @@ -508,7 +483,28 @@ static int dwc3_octeon_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *node = dev->of_node; struct dwc3_octeon *octeon; - int err; + int power_active_low, power_gpio; + int err, len; + + power_gpio = DWC3_GPIO_POWER_NONE; + power_active_low = 0; + if (of_find_property(node, "power", &len)) { + u32 gpio_pwr[3]; + + switch (len) { + case 8: + of_property_read_u32_array(node, "power", gpio_pwr, 2); + break; + case 12: + of_property_read_u32_array(node, "power", gpio_pwr, 3); + power_active_low = gpio_pwr[2] & 0x01; + break; + default: + dev_err(dev, "invalid power configuration\n"); + return -EINVAL; + } + power_gpio = gpio_pwr[1]; + } octeon = devm_kzalloc(dev, sizeof(*octeon), GFP_KERNEL); if (!octeon) @@ -519,7 +515,7 @@ static int dwc3_octeon_probe(struct platform_device *pdev) if (IS_ERR(octeon->base)) return PTR_ERR(octeon->base); - err = dwc3_octeon_clocks_start(octeon); + err = dwc3_octeon_setup(octeon, power_gpio, power_active_low); if (err) return err; From patchwork Mon Jul 31 09:32:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13334170 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A352CC001DE for ; Mon, 31 Jul 2023 09:33:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231963AbjGaJdO (ORCPT ); Mon, 31 Jul 2023 05:33:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232268AbjGaJc7 (ORCPT ); Mon, 31 Jul 2023 05:32:59 -0400 Received: from h1.cmg1.smtp.forpsi.com (h1.cmg1.smtp.forpsi.com [81.2.195.162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68DEFE43 for ; Mon, 31 Jul 2023 02:32:58 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id QPGpqwVUgPm6CQPGqqqIQx; Mon, 31 Jul 2023 11:32:56 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1690795976; bh=s9wblspwj9Vu52h88bzBEwg8cmpKO+43BMvX9zWQhHk=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=GeNgdcHmIWQahqDkkbd7jrO/82zpm+uM9fjT6YJv3ti3lMC0ZlwwlRObXpRS1y7lc LITm1eJowYZ5sMcfiR+u98s9jJeagm7fvQ3gDxtmi4UlJR/Xlvo0mMBhA3knV0iVaZ Q70UZ+vLPCi+ybHZd11wEDfCx2A1UeXv9nznR4+x+pT99uwPfxYb0XTG60p0fIW/6G UXFH/ricfBOvaCYr/lJyVXLHwaKeKT5G29/EovolBabQccfBUUK22SgJMtbayDw+l7 c14rXvxd6L7lLOXb3oJdwxJfW3MSBM1zczDM0Xl3leFOcI8JtyRt+ZMhEXqW/wkRxr FAe7WE/pliI7g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1690795976; bh=s9wblspwj9Vu52h88bzBEwg8cmpKO+43BMvX9zWQhHk=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=GeNgdcHmIWQahqDkkbd7jrO/82zpm+uM9fjT6YJv3ti3lMC0ZlwwlRObXpRS1y7lc LITm1eJowYZ5sMcfiR+u98s9jJeagm7fvQ3gDxtmi4UlJR/Xlvo0mMBhA3knV0iVaZ Q70UZ+vLPCi+ybHZd11wEDfCx2A1UeXv9nznR4+x+pT99uwPfxYb0XTG60p0fIW/6G UXFH/ricfBOvaCYr/lJyVXLHwaKeKT5G29/EovolBabQccfBUUK22SgJMtbayDw+l7 c14rXvxd6L7lLOXb3oJdwxJfW3MSBM1zczDM0Xl3leFOcI8JtyRt+ZMhEXqW/wkRxr FAe7WE/pliI7g== Date: Mon, 31 Jul 2023 11:32:55 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v5 5/7] usb: dwc3: dwc3-octeon: Move node parsing into driver probe Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfOz47zrcMbx+CLTdTNma5gF++/y9i/v5353Enp6LVelH+x8FwXbGxSqr0VbKyFX/xvLp4w3o2/Fd9u+DjJ/ELK2JmFDjSylcPPZaAJXT6C5iE5AbTwF/ v4dxMb1aCe26vuJroKkAW0ZAHvoXFeK8PGTDPTtSGimob8bQmjPLWKo29SeyuJ2plnzem9id1bfSfkYPWwbMeb6IkaxNBnXXqJzh34eEqTC/1UnyYLD1oxrb BbYos1bo3PDHapgxvuhsaD/XIIi9bMKK+uIZQrhM+zjPXvlFf8sUXlEWpsw9aqQ4DB/xi5D//+NC/Fb7iSpysZxl/v9OL6lpYawPHQ8f9h4D9vyB8XdTMSJF bhIf7Kvz Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Parse and verify device tree node first, then setup UCTL bridge using verified values. This avoids needless allocations in case DT misconfiguration was found in the middle of setup. Signed-off-by: Ladislav Michl Acked-by: Thinh Nguyen --- CHANGES: - v2: if else block bracket according CodingStyle - v3: more descriptive commit message, power gpio parsing in probe too, checkpatch --strict passed - v4: move changes unrelated to parsing move into separate patches - v5: none drivers/usb/dwc3/dwc3-octeon.c | 135 +++++++++++++++------------------ 1 file changed, 60 insertions(+), 75 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 0dc45dda134c..330bcb59cc95 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -261,69 +261,15 @@ static int dwc3_octeon_get_divider(void) } static int dwc3_octeon_setup(struct dwc3_octeon *octeon, + int ref_clk_sel, int ref_clk_fsel, int mpll_mul, int power_gpio, int power_active_low) { - int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; - u32 clock_rate; u64 val; + int div; struct device *dev = octeon->dev; void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL; void __iomem *uctl_host_cfg_reg = octeon->base + USBDRD_UCTL_HOST_CFG; - if (dev->of_node) { - const char *ss_clock_type; - const char *hs_clock_type; - - i = of_property_read_u32(dev->of_node, - "refclk-frequency", &clock_rate); - if (i) { - dev_err(dev, "No UCTL \"refclk-frequency\"\n"); - return -EINVAL; - } - i = of_property_read_string(dev->of_node, - "refclk-type-ss", &ss_clock_type); - if (i) { - dev_err(dev, "No UCTL \"refclk-type-ss\"\n"); - return -EINVAL; - } - i = of_property_read_string(dev->of_node, - "refclk-type-hs", &hs_clock_type); - if (i) { - dev_err(dev, "No UCTL \"refclk-type-hs\"\n"); - return -EINVAL; - } - if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { - if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) - ref_clk_sel = 0; - else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) - ref_clk_sel = 2; - else - dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", - hs_clock_type); - } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { - if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) - ref_clk_sel = 1; - else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) - ref_clk_sel = 3; - else { - dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", - hs_clock_type); - ref_clk_sel = 3; - } - } else - dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n", - ss_clock_type); - - if ((ref_clk_sel == 0 || ref_clk_sel == 1) && - (clock_rate != 100000000)) - dev_warn(dev, "Invalid UCTL clock rate of %u, using 100000000 instead\n", - clock_rate); - - } else { - dev_err(dev, "No USB UCTL device node\n"); - return -EINVAL; - } - /* * Step 1: Wait for all voltages to be stable...that surely * happened before starting the kernel. SKIP @@ -367,24 +313,6 @@ static int dwc3_octeon_setup(struct dwc3_octeon *octeon, val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL; val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel); - ref_clk_fsel = 0x07; - switch (clock_rate) { - default: - dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", - clock_rate); - fallthrough; - case 100000000: - mpll_mul = 0x19; - if (ref_clk_sel < 2) - ref_clk_fsel = 0x27; - break; - case 50000000: - mpll_mul = 0x32; - break; - case 125000000: - mpll_mul = 0x28; - break; - } val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL; val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel); @@ -483,8 +411,64 @@ static int dwc3_octeon_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *node = dev->of_node; struct dwc3_octeon *octeon; + const char *hs_clock_type, *ss_clock_type; + int ref_clk_sel, ref_clk_fsel, mpll_mul; int power_active_low, power_gpio; int err, len; + u32 clock_rate; + + if (of_property_read_u32(node, "refclk-frequency", &clock_rate)) { + dev_err(dev, "No UCTL \"refclk-frequency\"\n"); + return -EINVAL; + } + if (of_property_read_string(node, "refclk-type-ss", &ss_clock_type)) { + dev_err(dev, "No UCTL \"refclk-type-ss\"\n"); + return -EINVAL; + } + if (of_property_read_string(node, "refclk-type-hs", &hs_clock_type)) { + dev_err(dev, "No UCTL \"refclk-type-hs\"\n"); + return -EINVAL; + } + + ref_clk_sel = 2; + if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { + if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) + ref_clk_sel = 0; + else if (strcmp(hs_clock_type, "pll_ref_clk")) + dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", + hs_clock_type); + } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { + if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) { + ref_clk_sel = 1; + } else { + ref_clk_sel = 3; + if (strcmp(hs_clock_type, "pll_ref_clk")) + dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", + hs_clock_type); + } + } else { + dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n", + ss_clock_type); + } + + ref_clk_fsel = 0x07; + switch (clock_rate) { + default: + dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", + clock_rate); + fallthrough; + case 100000000: + mpll_mul = 0x19; + if (ref_clk_sel < 2) + ref_clk_fsel = 0x27; + break; + case 50000000: + mpll_mul = 0x32; + break; + case 125000000: + mpll_mul = 0x28; + break; + } power_gpio = DWC3_GPIO_POWER_NONE; power_active_low = 0; @@ -515,7 +499,8 @@ static int dwc3_octeon_probe(struct platform_device *pdev) if (IS_ERR(octeon->base)) return PTR_ERR(octeon->base); - err = dwc3_octeon_setup(octeon, power_gpio, power_active_low); + err = dwc3_octeon_setup(octeon, ref_clk_sel, ref_clk_fsel, mpll_mul, + power_gpio, power_active_low); if (err) return err; From patchwork Mon Jul 31 09:33:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13334171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A6DFC001E0 for ; Mon, 31 Jul 2023 09:33:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231560AbjGaJdh (ORCPT ); Mon, 31 Jul 2023 05:33:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229735AbjGaJdc (ORCPT ); Mon, 31 Jul 2023 05:33:32 -0400 Received: from h1.cmg2.smtp.forpsi.com (h1.cmg2.smtp.forpsi.com [81.2.195.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59FA312B for ; Mon, 31 Jul 2023 02:33:27 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id QPHIq0mezv5uIQPHJqCuT7; Mon, 31 Jul 2023 11:33:25 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1690796005; bh=isYG4ju5ujO2jvZKE7He4YghaXfIC1uepsHjRAJVSoU=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=nRMU0qnGfBvpeksQMwHRb9RI/gcni2T351aKK9aSZnxa89771uK1CVyDw0m3rbKzS Dvk1CbjYHG8tf7PgTgM4AANTN5AGdZd8PAOej0PGOGExm2Y1E/4FEChVoC0a7lIWid 11HqrSaPdqXfVOAEKc/bd4wB+UwWehPXBxFUhoNK+377L6Y0C+z2nD9hWCgAHpeve5 qb+l+2Gu44Jhucwt9VOjv1f4rFOtH+KxTVGctyIr2m1qmVtEPiz+1rLo41vhqEJEaI mSZDGVzuI5Ev/mOG5YXshseyY6pPey/RQT+8c3ABMxrIwsEWCH3/vwES1BTGme6IJj 51OCrMZhLmfSw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1690796005; bh=isYG4ju5ujO2jvZKE7He4YghaXfIC1uepsHjRAJVSoU=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=nRMU0qnGfBvpeksQMwHRb9RI/gcni2T351aKK9aSZnxa89771uK1CVyDw0m3rbKzS Dvk1CbjYHG8tf7PgTgM4AANTN5AGdZd8PAOej0PGOGExm2Y1E/4FEChVoC0a7lIWid 11HqrSaPdqXfVOAEKc/bd4wB+UwWehPXBxFUhoNK+377L6Y0C+z2nD9hWCgAHpeve5 qb+l+2Gu44Jhucwt9VOjv1f4rFOtH+KxTVGctyIr2m1qmVtEPiz+1rLo41vhqEJEaI mSZDGVzuI5Ev/mOG5YXshseyY6pPey/RQT+8c3ABMxrIwsEWCH3/vwES1BTGme6IJj 51OCrMZhLmfSw== Date: Mon, 31 Jul 2023 11:33:24 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v5 6/7] usb: dwc3: dwc3-octeon: Dump control register on clock init failure Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfLWc86PEY2dpI617wbrd4PmgMa6IW8wFqDldx1klsAL6WnQ2/q41tQKqaUgRM8C0Gw0M4U/ST0JywcARNpymFCyz3GBfDyBofVnGkpgMUCauN3zpwDlA iyrDDb7SK1ib8Ivwdm1SGbx/iP2yyfScN/M10tpMhPV8Dv0cil6dCS5RdsPNPCtJuD13GjnA7zsSv1FQVeXR9oEtNVjh5B/SF9M4DTow5cpMiq9vCk1n11MA lpVnG1L+U+exlorJ81mXGgqgHD1eV2nOfnvpqy/qKhKy4xBULTSdIwbz00ouTboM6w/PfPCb41V/QiAeHzb53fx+qB5fJ60Hr1zByEWA5EL4Tqg89QcLO5zS eIR29Q90 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl It might be interesting to know control register value in case clock fails to enable. Signed-off-by: Ladislav Michl Reviewed-by: Philippe Mathieu-Daudé Acked-by: Thinh Nguyen --- CHANGES: - v4: new patch - v5: Philippe's review tag drivers/usb/dwc3/dwc3-octeon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 330bcb59cc95..d578110f7afb 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -299,8 +299,8 @@ static int dwc3_octeon_setup(struct dwc3_octeon *octeon, val = dwc3_octeon_readq(uctl_ctl_reg); if ((div != FIELD_GET(USBDRD_UCTL_CTL_H_CLKDIV_SEL, val)) || (!(FIELD_GET(USBDRD_UCTL_CTL_H_CLK_EN, val)))) { - dev_err(dev, "dwc3 controller clock init failure.\n"); - return -EINVAL; + dev_err(dev, "clock init failure (UCTL_CTL=%016llx)\n", val); + return -EINVAL; } /* Step 4c: Deassert the controller clock divider reset. */ From patchwork Mon Jul 31 09:33:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 13334172 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3D67C001DE for ; Mon, 31 Jul 2023 09:33:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230137AbjGaJd5 (ORCPT ); Mon, 31 Jul 2023 05:33:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229735AbjGaJd5 (ORCPT ); Mon, 31 Jul 2023 05:33:57 -0400 Received: from h1.cmg2.smtp.forpsi.com (h1.cmg2.smtp.forpsi.com [81.2.195.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9B42F3 for ; Mon, 31 Jul 2023 02:33:55 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id QPHlq0muLv5uIQPHmqCucJ; Mon, 31 Jul 2023 11:33:54 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1690796034; bh=p8BAX+z5tyX+vrhH+vr3OPQKUiBENZsKmQLHx64s87M=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=fN2Q0CYaxde7NSd/hEnjOppkcnVAt4qRVFjyg1DVS7qIGHgp59qrsc7lwswg2wdTc pmELR/mwWpaYpqVsoCG+huvUeXl6y3teHhyCz1jnFyuX3DySOfK82LGlHQ+FbDZM/X dprtagk4hwQ6Y2epkaIAV+lonZRyZ5SAxbSEVNbFhNLTuSxIhiDqw0A1we7x+c8/OY yUQv96f114dQ5Iz/7EnrwPzZTMRm9h4E9woWvPaJEyhxlti5IK/GGrGSfR3LdUEQYO 7c2kzBdb5DSEXBzEV07UPuUGvfcJ/0AhMJlXewZxb+6p82ffFAPIspKjTVHNxCYHtt Knl5gkUOdMW3w== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1690796034; bh=p8BAX+z5tyX+vrhH+vr3OPQKUiBENZsKmQLHx64s87M=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=fN2Q0CYaxde7NSd/hEnjOppkcnVAt4qRVFjyg1DVS7qIGHgp59qrsc7lwswg2wdTc pmELR/mwWpaYpqVsoCG+huvUeXl6y3teHhyCz1jnFyuX3DySOfK82LGlHQ+FbDZM/X dprtagk4hwQ6Y2epkaIAV+lonZRyZ5SAxbSEVNbFhNLTuSxIhiDqw0A1we7x+c8/OY yUQv96f114dQ5Iz/7EnrwPzZTMRm9h4E9woWvPaJEyhxlti5IK/GGrGSfR3LdUEQYO 7c2kzBdb5DSEXBzEV07UPuUGvfcJ/0AhMJlXewZxb+6p82ffFAPIspKjTVHNxCYHtt Knl5gkUOdMW3w== Date: Mon, 31 Jul 2023 11:33:53 +0200 From: Ladislav Michl To: Thomas Bogendoerfer , Thinh Nguyen , Greg Kroah-Hartman , Liang He Cc: linux-mips@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH v5 7/7] usb: dwc3: dwc3-octeon: Add SPDX header and copyright Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfCN0FotF9j3o28CTfKr2i3BdJ+umd/S1pdcLejQsmY33tmwbYTfg1ADDfiA1w73jWZmK5ioXlT3ixhxwixfvKSl7TvarauCM5gXW/Vus86EpmfQmImtT HSBfBU/z00n8Q9A4+eKufZQSU/CrHr03tr/plnm/OX77M+qPSwSBa5NK4f58BeX1/AGyNqut29kvqRMYlTMZw2xdVrOZ7gfwY4g96m8ejK3oCXr4k/wXmIjX lY2AsJEDxykncJXtbcErAcxAE5x325r/2s1uscLz/UGIE5GUKogYJq7mIEg+WpJFDHP8XuHl9nqtYgw2Jyh7vEFpwSgaBr6N+CiFasqqiX5rDFHaOnTEw2nV aBimIDki Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Assign copyright to indicate driver rewrite is done for RACOM s.r.o. As David no longer works for Marvell (Cavium), I'm to blame for breakage. Signed-off-by: Ladislav Michl Acked-by: Thinh Nguyen Reviewed-by: Philippe Mathieu-Daudé Acked-by: David Daney Reviewed-by: Philippe Mathieu-Daudé --- CHANGES: - v2: None - v3: None - v4: Assign copyring to RACOM s.r.o., Mírová 1283, Nové Město na Moravě - v5: None drivers/usb/dwc3/dwc3-octeon.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index d578110f7afb..6f47262a117a 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -1,11 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * XHCI HCD glue for Cavium Octeon III SOCs. + * DWC3 glue for Cavium Octeon III SOCs. * * Copyright (C) 2010-2017 Cavium Networks - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * Copyright (C) 2023 RACOM s.r.o. */ #include @@ -537,6 +535,6 @@ static struct platform_driver dwc3_octeon_driver = { module_platform_driver(dwc3_octeon_driver); MODULE_ALIAS("platform:dwc3-octeon"); -MODULE_AUTHOR("David Daney "); +MODULE_AUTHOR("Ladislav Michl "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("DesignWare USB3 OCTEON III Glue Layer");