From patchwork Wed Aug 2 04:59:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13337623 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D25EAC04FDF for ; Wed, 2 Aug 2023 04:59:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232117AbjHBE7k (ORCPT ); Wed, 2 Aug 2023 00:59:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230349AbjHBE7j (ORCPT ); Wed, 2 Aug 2023 00:59:39 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22FB2210D; Tue, 1 Aug 2023 21:59:38 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3724Qpo3015901; Wed, 2 Aug 2023 04:59:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=gV1AawchQgi85X6RLjogBZvLTS9QABorkwBIs0uhlms=; b=RyvhT+L2fEYwtoNvfwG43glzX8sJmgon8S0DhJ8tAZ4IcVKQSFLXdqPJhyVjNpQ/T4OA jql91T8dBa3EXPWBcoptlWgDPOfYj7aGpi4/dz34DT7V5aGS8AJj48/VDva59knFoy3x ee3bhbONrbscoceu2lV0yjv40vJ127fPsDYARBCju/y+hUikJNnnVyiTdj1q1gfdmuf9 syzxNF6nmIUTt2HUwcqv+nvRNDw3AR6i5RhWjwqhAcNZt3HVDCZNoDtPiolS3dnpTflm 5iqUSSs8qpTex5r5PHNJU9I9ZozlQ57rlwJhBEAxwhVKsXTeo4qHQjNHTyuLSgzI0bkV ww== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s7bw9gesk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 02 Aug 2023 04:59:31 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3724xRqx022304; Wed, 2 Aug 2023 04:59:27 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3s4uukd91v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 02 Aug 2023 04:59:27 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3724xQ8d022284; Wed, 2 Aug 2023 04:59:26 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3724xQ7m022278; Wed, 02 Aug 2023 04:59:26 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 995824B5C; Wed, 2 Aug 2023 10:29:25 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, quic_parass@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Kishon Vijay Abraham I , Bjorn Helgaas , Jonathan Corbet , linux-doc@vger.kernel.org (open list:DOCUMENTATION) Subject: [PATCH v5 1/5] PCI: endpoint: Add wakeup host API to EPC core Date: Wed, 2 Aug 2023 10:29:15 +0530 Message-Id: <1690952359-8625-2-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690952359-8625-1-git-send-email-quic_krichai@quicinc.com> References: <1690952359-8625-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: -oe8HkYHvvYprXsKrtAHYdzt16vWDF_j X-Proofpoint-GUID: -oe8HkYHvvYprXsKrtAHYdzt16vWDF_j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_02,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 adultscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=795 phishscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020044 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Endpoint cannot send any data/MSI when the D-state is in D3cold or D3hot. Endpoint needs to wake up the host to bring the D-state to D0. Endpoint can toggle wake signal when the D-state is in D3cold and vaux is not supplied or can send inband PME. To support this add wakeup_host() callback to the EPC core. Signed-off-by: Krishna chaitanya chundru --- Documentation/PCI/endpoint/pci-endpoint.rst | 6 ++++++ drivers/pci/endpoint/pci-epc-core.c | 30 +++++++++++++++++++++++++++++ include/linux/pci-epc.h | 5 +++++ 3 files changed, 41 insertions(+) diff --git a/Documentation/PCI/endpoint/pci-endpoint.rst b/Documentation/PCI/endpoint/pci-endpoint.rst index 66f3191..9a96ce0 100644 --- a/Documentation/PCI/endpoint/pci-endpoint.rst +++ b/Documentation/PCI/endpoint/pci-endpoint.rst @@ -53,6 +53,7 @@ by the PCI controller driver. * raise_irq: ops to raise a legacy, MSI or MSI-X interrupt * start: ops to start the PCI link * stop: ops to stop the PCI link + * wakeup_host: ops to wakeup host The PCI controller driver can then create a new EPC device by invoking devm_pci_epc_create()/pci_epc_create(). @@ -121,6 +122,11 @@ by the PCI endpoint function driver. The PCI endpoint function driver should use pci_epc_mem_free_addr() to free the memory space allocated using pci_epc_mem_alloc_addr(). +* pci_epc_wakeup_host() + + The PCI endpoint function driver should use pci_epc_wakeup_host() to wakeup + host. + Other EPC APIs ~~~~~~~~~~~~~~ diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 4cf9c82..afd6a25 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -167,6 +167,36 @@ const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc, EXPORT_SYMBOL_GPL(pci_epc_get_features); /** + * pci_epc_wakeup_host() - Wakeup the host + * @epc: the EPC device which has to wakeup the host + * @func_no: the physical endpoint function number in the EPC device + * @vfunc_no: the virtual endpoint function number in the physical function + * @send_pme: true if wakeup is by sending PME + * + * Invoke to wakeup host + */ +bool pci_epc_wakeup_host(struct pci_epc *epc, u8 func_no, u8 vfunc_no, bool send_pme) +{ + int ret; + + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) + return false; + + if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) + return false; + + if (!epc->ops->wakeup_host) + return true; + + mutex_lock(&epc->lock); + ret = epc->ops->wakeup_host(epc, func_no, vfunc_no, send_pme); + mutex_unlock(&epc->lock); + + return ret; +} +EXPORT_SYMBOL_GPL(pci_epc_wakeup_host); + +/** * pci_epc_stop() - stop the PCI link * @epc: the link of the EPC device that has to be stopped * diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 26a1108..166a86b 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -59,6 +59,7 @@ pci_epc_interface_string(enum pci_epc_interface_type type) * @start: ops to start the PCI link * @stop: ops to stop the PCI link * @get_features: ops to get the features supported by the EPC + * @wakeup_host: ops to wakeup the host * @owner: the module owner containing the ops */ struct pci_epc_ops { @@ -88,6 +89,8 @@ struct pci_epc_ops { void (*stop)(struct pci_epc *epc); const struct pci_epc_features* (*get_features)(struct pci_epc *epc, u8 func_no, u8 vfunc_no); + bool (*wakeup_host)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + bool send_pme); struct module *owner; }; @@ -234,6 +237,8 @@ int pci_epc_start(struct pci_epc *epc); void pci_epc_stop(struct pci_epc *epc); const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no); +bool pci_epc_wakeup_host(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + bool send_pme); enum pci_barno pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features); enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features From patchwork Wed Aug 2 04:59:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13337624 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE34AC001DE for ; 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Wed, 02 Aug 2023 04:59:31 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3724xRiD022303; Wed, 2 Aug 2023 04:59:27 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3s4uukd91u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 02 Aug 2023 04:59:27 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3724xQud022283; Wed, 2 Aug 2023 04:59:26 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3724xQxt022280; Wed, 02 Aug 2023 04:59:26 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id D9C4E4B5F; Wed, 2 Aug 2023 10:29:25 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, quic_parass@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Subject: [PATCH v5 2/5] PCI: dwc: Add wakeup host op to pci_epc_ops Date: Wed, 2 Aug 2023 10:29:16 +0530 Message-Id: <1690952359-8625-3-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690952359-8625-1-git-send-email-quic_krichai@quicinc.com> References: <1690952359-8625-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: feycgqgB72pj-HQrac95SQL0Uq5jWAX1 X-Proofpoint-ORIG-GUID: feycgqgB72pj-HQrac95SQL0Uq5jWAX1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_02,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=724 adultscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 mlxscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 clxscore=1011 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020044 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add wakeup host op to wake up host from D3cold or D3hot. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-designware-ep.c | 12 ++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index f9182f8..e2733a4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -463,6 +463,17 @@ dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) return ep->ops->get_features(ep); } +static bool dw_pcie_ep_wakeup_host(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + bool send_pme) +{ + struct dw_pcie_ep *ep = epc_get_drvdata(epc); + + if (!ep->ops->wakeup_host) + return false; + + return ep->ops->wakeup_host(ep, func_no, send_pme); +} + static const struct pci_epc_ops epc_ops = { .write_header = dw_pcie_ep_write_header, .set_bar = dw_pcie_ep_set_bar, @@ -477,6 +488,7 @@ static const struct pci_epc_ops epc_ops = { .start = dw_pcie_ep_start, .stop = dw_pcie_ep_stop, .get_features = dw_pcie_ep_get_features, + .wakeup_host = dw_pcie_ep_wakeup_host, }; int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 6156606..fc47e74 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -330,6 +330,8 @@ struct dw_pcie_ep_ops { * driver. */ unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no); + + bool (*wakeup_host)(struct dw_pcie_ep *ep, u8 func_no, bool send_pme); }; struct dw_pcie_ep_func { From patchwork Wed Aug 2 04:59:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13337622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2818EC04A6A for ; Wed, 2 Aug 2023 04:59:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232084AbjHBE7k (ORCPT ); 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Wed, 02 Aug 2023 04:59:31 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3724xRPx022308; Wed, 2 Aug 2023 04:59:27 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3s4uukd91x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 02 Aug 2023 04:59:27 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3724xRoS022297; Wed, 2 Aug 2023 04:59:27 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3724xQrn022281; Wed, 02 Aug 2023 04:59:27 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 16BEA4B62; Wed, 2 Aug 2023 10:29:26 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, quic_parass@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Subject: [PATCH v5 3/5] PCI: qcom-ep: Add wake up host op to dw_pcie_ep_ops Date: Wed, 2 Aug 2023 10:29:17 +0530 Message-Id: <1690952359-8625-4-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690952359-8625-1-git-send-email-quic_krichai@quicinc.com> References: <1690952359-8625-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: PVDHyEEx2ur7t7tltrCFEB8-w0ZwfE6o X-Proofpoint-GUID: PVDHyEEx2ur7t7tltrCFEB8-w0ZwfE6o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_03,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 clxscore=1015 impostorscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020044 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add wakeup host op to dw_pcie_ep_ops to wake up host. If the wakeup type is PME, then trigger inband PME by writing to the PARF PARF_PM_CTRL register, otherwise toggle #WAKE. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 0c69a61..e78a74a1 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -89,6 +89,7 @@ /* PARF_PM_CTRL register fields */ #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1) #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2) +#define PARF_PM_CTRL_XMT_PME BIT(4) #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5) /* PARF_MHI_CLOCK_RESET_CTRL fields */ @@ -730,10 +731,35 @@ static void qcom_pcie_ep_init(struct dw_pcie_ep *ep) dw_pcie_ep_reset_bar(pci, bar); } +static bool qcom_pcie_ep_wakeup_host(struct dw_pcie_ep *ep, u8 func_no, bool send_pme) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); + struct device *dev = pci->dev; + u32 val; + + if (send_pme) { + dev_dbg(dev, "Waking up the host using PME\n"); + val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL); + writel_relaxed(val | PARF_PM_CTRL_XMT_PME, pcie_ep->parf + PARF_PM_CTRL); + writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL); + + } else { + dev_dbg(dev, "Waking up the host by toggling WAKE#\n"); + gpiod_set_value_cansleep(pcie_ep->wake, 1); + usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500); + gpiod_set_value_cansleep(pcie_ep->wake, 0); + + } + + return true; +} + static const struct dw_pcie_ep_ops pci_ep_ops = { .ep_init = qcom_pcie_ep_init, .raise_irq = qcom_pcie_ep_raise_irq, .get_features = qcom_pcie_epc_get_features, + .wakeup_host = qcom_pcie_ep_wakeup_host, }; static int qcom_pcie_ep_probe(struct platform_device *pdev) From patchwork Wed Aug 2 04:59:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13337625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44B8FC05051 for ; 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Wed, 02 Aug 2023 04:59:33 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 3724xRiF022303; Wed, 2 Aug 2023 04:59:29 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3s4uukd927-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 02 Aug 2023 04:59:29 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3724xTDs022327; Wed, 2 Aug 2023 04:59:29 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3724xST2022326; Wed, 02 Aug 2023 04:59:29 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id 192874B59; Wed, 2 Aug 2023 10:29:28 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, quic_parass@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Kishon Vijay Abraham I , Bjorn Helgaas , Jeffrey Hugo , mhi@lists.linux.dev (open list:MHI BUS) Subject: [PATCH v5 4/5] PCI: epf-mhi: Add wakeup host op Date: Wed, 2 Aug 2023 10:29:18 +0530 Message-Id: <1690952359-8625-5-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690952359-8625-1-git-send-email-quic_krichai@quicinc.com> References: <1690952359-8625-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 92-aV62lJWL5uu5wnUdl96PSRfarudDL X-Proofpoint-GUID: 92-aV62lJWL5uu5wnUdl96PSRfarudDL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_03,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 priorityscore=1501 phishscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=787 adultscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020044 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add wakeup host op for MHI EPF. If the D-state is in D3cold toggle wake signal, otherwise send PME. Signed-off-by: Krishna chaitanya chundru --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 12 ++++++++++++ include/linux/mhi_ep.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c index ee91bfc..840d5d3 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -237,6 +237,17 @@ static int pci_epf_mhi_write_to_host(struct mhi_ep_cntrl *mhi_cntrl, return 0; } +static int pci_epf_mhi_wakeup_host(struct mhi_ep_cntrl *mhi_cntrl) +{ + struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); + struct pci_epf *epf = epf_mhi->epf; + struct pci_epc *epc = epf->epc; + + return pci_epc_wakeup_host(epc, epf->func_no, epf->vfunc_no, + (mhi_cntrl->dstate == PCI_D3cold) ? false : true); + +} + static int pci_epf_mhi_core_init(struct pci_epf *epf) { struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); @@ -293,6 +304,7 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf) mhi_cntrl->unmap_free = pci_epf_mhi_unmap_free; mhi_cntrl->read_from_host = pci_epf_mhi_read_from_host; mhi_cntrl->write_to_host = pci_epf_mhi_write_to_host; + mhi_cntrl->wakeup_host = pci_epf_mhi_wakeup_host; /* Register the MHI EP controller */ ret = mhi_ep_register_controller(mhi_cntrl, info->config); diff --git a/include/linux/mhi_ep.h b/include/linux/mhi_ep.h index c3a0685..e353c429 100644 --- a/include/linux/mhi_ep.h +++ b/include/linux/mhi_ep.h @@ -137,6 +137,7 @@ struct mhi_ep_cntrl { void __iomem *virt, size_t size); int (*read_from_host)(struct mhi_ep_cntrl *mhi_cntrl, u64 from, void *to, size_t size); int (*write_to_host)(struct mhi_ep_cntrl *mhi_cntrl, void *from, u64 to, size_t size); + int (*wakeup_host)(struct mhi_ep_cntrl *mhi_cntrl); enum mhi_state mhi_state; From patchwork Wed Aug 2 04:59:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13337626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 704DCC04A6A for ; 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Wed, 02 Aug 2023 05:00:16 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 37250DJQ023276; Wed, 2 Aug 2023 05:00:13 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3s4uukd960-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 02 Aug 2023 05:00:13 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 37250Crg023266; Wed, 2 Aug 2023 05:00:12 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-krichai-hyd.qualcomm.com [10.213.110.112]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 37250CbJ023265; Wed, 02 Aug 2023 05:00:12 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 4058933) id CFA8B4B59; Wed, 2 Aug 2023 10:30:11 +0530 (+0530) From: Krishna chaitanya chundru To: manivannan.sadhasivam@linaro.org Cc: helgaas@kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_nitegupt@quicinc.com, quic_skananth@quicinc.com, quic_ramkri@quicinc.com, quic_parass@quicinc.com, krzysztof.kozlowski@linaro.org, Krishna chaitanya chundru , Manivannan Sadhasivam , Jeffrey Hugo , Dan Carpenter , Greg Kroah-Hartman , mhi@lists.linux.dev (open list:MHI BUS) Subject: [PATCH v5 5/5] bus: mhi: ep: wake up host if the MHI state is in M3 Date: Wed, 2 Aug 2023 10:29:19 +0530 Message-Id: <1690952359-8625-6-git-send-email-quic_krichai@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1690952359-8625-1-git-send-email-quic_krichai@quicinc.com> References: <1690952359-8625-1-git-send-email-quic_krichai@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: DClo9cbYKnJB2DOf7VdGkt6EuVUak_7J X-Proofpoint-ORIG-GUID: DClo9cbYKnJB2DOf7VdGkt6EuVUak_7J X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_02,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 impostorscore=0 phishscore=0 clxscore=1015 mlxlogscore=937 bulkscore=0 lowpriorityscore=0 mlxscore=0 adultscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020044 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If the MHI state is in M3 then most probably the host kept the device in D3 hot or D3 cold, due to that endpoint transactions will not be read by the host, endpoint needs to wakes up the host to bring the host to D0 which eventually bring back the MHI state to M0. Signed-off-by: Krishna chaitanya chundru --- drivers/bus/mhi/ep/main.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/bus/mhi/ep/main.c b/drivers/bus/mhi/ep/main.c index 6008818..9035e02 100644 --- a/drivers/bus/mhi/ep/main.c +++ b/drivers/bus/mhi/ep/main.c @@ -25,6 +25,26 @@ static DEFINE_IDA(mhi_ep_cntrl_ida); static int mhi_ep_create_device(struct mhi_ep_cntrl *mhi_cntrl, u32 ch_id); static int mhi_ep_destroy_device(struct device *dev, void *data); +static int mhi_ep_wake_host(struct mhi_ep_cntrl *mhi_cntrl) +{ + enum mhi_state state; + bool mhi_reset; + u32 count = 0; + + mhi_cntrl->wakeup_host(mhi_cntrl); + + /* Wait for Host to set the M0 state */ + while (count++ < M0_WAIT_COUNT) { + msleep(M0_WAIT_DELAY_MS); + + mhi_ep_mmio_get_mhi_state(mhi_cntrl, &state, &mhi_reset); + if (state == MHI_STATE_M0) + return 0; + } + + return -ENODEV; +} + static int mhi_ep_send_event(struct mhi_ep_cntrl *mhi_cntrl, u32 ring_idx, struct mhi_ring_element *el, bool bei) { @@ -466,6 +486,14 @@ int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, struct sk_buff *skb) mutex_lock(&mhi_chan->lock); + if (mhi_cntrl->mhi_state == MHI_STATE_M3) { + ret = mhi_ep_wake_host(mhi_cntrl); + if (ret) { + dev_err(dev, "Failed to wakeup host\n"); + goto err_exit; + } + } + do { /* Don't process the transfer ring if the channel is not in RUNNING state */ if (mhi_chan->state != MHI_CH_STATE_RUNNING) {