From patchwork Wed Aug 2 14:05:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13338209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E91E8C41513 for ; Wed, 2 Aug 2023 14:06:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234697AbjHBOGu (ORCPT ); Wed, 2 Aug 2023 10:06:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234719AbjHBOGt (ORCPT ); Wed, 2 Aug 2023 10:06:49 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA6E0270F; Wed, 2 Aug 2023 07:06:45 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 372Abngj006748; Wed, 2 Aug 2023 14:06:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=dXJIA5rml4HpJkJrfbgjmxkSF4l/5L9XLfKKQQJbQLg=; b=XOzyV418R4DbSVUIVPEuUZH3WVLPT6l1Pw2pZW6jONnXYbFIiC9FCAUsLpPbAbvRUBqX aZyNr1M/Ut1k62KreWZ+YnsxkoprMczElBEVX3ymR+J4V3Qh9FLjvl1zbpQ38GUlgBL9 kyfwF+aggOn85b1s+5kl/8SdOAWeXVKrlykaqVkxEgJ1TmLMPHoq5ZJtUgK/Ly5oU6A/ 32yjmFRfk5WfI96eF6AwNlVS03Au7tjuZKw4pFQyG9gF01MAUtNHhXRGOYuzrNj/mcFS tFvsBgU2mSWJ7q1vX6dUEZdB3anDVqhH64lVSaqWLJHkXr9oCfX+2Na2GfcI6Ks6w92l ew== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s75dgak4u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 02 Aug 2023 14:06:38 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 372E6b4s008713 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Aug 2023 14:06:37 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 2 Aug 2023 07:06:30 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v5 01/11] dt-bindings: remoteproc: qcom: Add support for multipd model Date: Wed, 2 Aug 2023 19:35:56 +0530 Message-ID: <20230802140606.2041889-2-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> References: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: sMfmLtqU-2zYI2ohE5earPcHf1g7T382 X-Proofpoint-ORIG-GUID: sMfmLtqU-2zYI2ohE5earPcHf1g7T382 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_09,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 clxscore=1011 malwarescore=0 suspectscore=0 bulkscore=0 adultscore=0 impostorscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020125 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Add new binding document for multipd model remoteproc. IPQ5332, IPQ9574 follows multipd model. Signed-off-by: Manikanta Mylavarapu Reviewed-by: Krzysztof Kozlowski --- Changes in v5: - No changes. Changes in v4: - No changes. Changes in v3: - Pick up R-b tag Changes in v2: - Fixed all comments and rebased on linux-next. - Changed to BSD-3-Clause - Added firmware-name. .../bindings/remoteproc/qcom,multipd-pil.yaml | 189 ++++++++++++++++++ 1 file changed, 189 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml new file mode 100644 index 000000000000..c52ac1640d7a --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,multipd-pil.yaml @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,multipd-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Multipd Secure Peripheral Image Loader + +maintainers: + - Manikanta Mylavarapu + +description: + Multipd Peripheral Image Loader loads firmware and boots Q6 protection domain, + WCSS protection domain remoteproc's on the Qualcomm IPQ9574, IPQ5332 SoC. + Protection domain is similar to process in Linux. Here QDSP6 processor runs + each wifi radio functionality on a separate process. One process can't access + other process resources, so this is termed as PD i.e protection domain. + +properties: + compatible: + enum: + - qcom,ipq5332-q6-mpd + - qcom,ipq9574-q6-mpd + + reg: + maxItems: 1 + + firmware-name: + maxItems: 2 + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the remote processor + items: + - description: Shutdown Q6 + - description: Stop Q6 + + qcom,smem-state-names: + description: + Names of the states used by the AP to signal the remote processor + items: + - const: shutdown + - const: stop + + memory-region: + items: + - description: Q6 reserved region + + glink-edge: + $ref: /schemas/remoteproc/qcom,glink-edge.yaml# + description: + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the Modem. + unevaluatedProperties: false + +patternProperties: + "^pd-1|pd-2|pd-3": + type: object + description: + WCSS means 'wireless connectivity sub system', in simple words it's a + wifi radio block. In multipd model, Q6 root protection domain will + provide services to WCSS user protection domain. In other words WCSS + protection domains depends on Q6 protection domain i.e Q6 should be up + before WCSS, similarly Q6 should shut down after all WCSS domains are + down. It can be achieved by building parent-child topology between Q6 + and WCSS domain's i.e keeping wcss node as sub node of Q6 device node. + + properties: + firmware-name: + maxItems: 1 + + interrupts: + items: + - description: Fatal interrupt + - description: Ready interrupt + - description: Spawn acknowledge interrupt + - description: Stop acknowledge interrupt + + interrupt-names: + items: + - const: fatal + - const: ready + - const: spawn-ack + - const: stop-ack + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the remote processor + items: + - description: Shutdown WCSS pd + - description: Stop WCSS pd + - description: Spawn WCSS pd + + qcom,smem-state-names: + description: + Names of the states used by the AP to signal the remote processor + items: + - const: shutdown + - const: stop + - const: spawn + + required: + - firmware-name + - interrupts + - interrupt-names + - qcom,smem-states + - qcom,smem-state-names + + additionalProperties: false + +required: + - compatible + - firmware-name + - reg + - interrupts + - interrupt-names + - qcom,smem-states + - qcom,smem-state-names + - memory-region + +additionalProperties: false + +examples: + - | + #include + q6v5_wcss: remoteproc@d100000 { + compatible = "qcom,ipq5332-q6-mpd"; + reg = <0xd100000 0x4040>; + firmware-name = "ath11k/IPQ5332/hw1.0/q6_fw0.mdt", + "ath11k/IPQ5332/hw1.0/iu_fw.mdt"; + interrupts-extended = <&intc GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 1 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 2 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 3 IRQ_TYPE_NONE>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + + memory-region = <&q6_region>; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + + pd-1 { + firmware-name = "ath11k/IPQ5332/hw1.0/q6_fw1.mdt"; + interrupts-extended = <&wcss_smp2p_in 8 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 9 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 12 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 11 IRQ_TYPE_NONE>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + qcom,smem-states = <&wcss_smp2p_out 8>, + <&wcss_smp2p_out 9>, + <&wcss_smp2p_out 10>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + }; + }; From patchwork Wed Aug 2 14:05:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13338210 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 315BBC04FE0 for ; Wed, 2 Aug 2023 14:06:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234695AbjHBOGw (ORCPT ); Wed, 2 Aug 2023 10:06:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234737AbjHBOGv (ORCPT ); Wed, 2 Aug 2023 10:06:51 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E1B926B6; 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Wed, 02 Aug 2023 14:06:45 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 372E6ich019172 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Aug 2023 14:06:44 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 2 Aug 2023 07:06:37 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v5 02/11] clk: qcom: ipq5332: remove q6 bring up clocks Date: Wed, 2 Aug 2023 19:35:57 +0530 Message-ID: <20230802140606.2041889-3-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> References: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rBOw71TcOcuIhpdae5GWNDDchWUbdMvf X-Proofpoint-ORIG-GUID: rBOw71TcOcuIhpdae5GWNDDchWUbdMvf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_09,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 bulkscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 suspectscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020125 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org In multipd model Q6 firmware takes care of bringup clocks, so remove them from gcc driver. Signed-off-by: Manikanta Mylavarapu --- Changes in v5: - Rebased on linux-next. Changes in v4: - In V3 series this patch is [05/11]. Here it's moved to [02/11] because to compile dt-bindings patches. drivers/clk/qcom/gcc-ipq5332.c | 380 --------------------------------- 1 file changed, 380 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index ce6dc6e99a29..7153c2853b74 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -2266,150 +2266,6 @@ static struct clk_branch gcc_prng_ahb_clk = { }, }; -static struct clk_branch gcc_q6_ahb_clk = { - .halt_reg = 0x25014, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x25014, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_wcss_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_ahb_s_clk = { - .halt_reg = 0x25018, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x25018, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_ahb_s_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_wcss_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_axim_clk = { - .halt_reg = 0x2500c, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x2500c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_axim_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_q6_axim_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_axis_clk = { - .halt_reg = 0x25010, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x25010, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_axis_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_system_noc_bfdcd_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_tsctr_1to2_clk = { - .halt_reg = 0x25020, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x25020, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_tsctr_1to2_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_qdss_tsctr_div2_clk_src.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6ss_atbm_clk = { - .halt_reg = 0x2501c, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x2501c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_atbm_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_qdss_at_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6ss_pclkdbg_clk = { - .halt_reg = 0x25024, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x25024, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_pclkdbg_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_qdss_dap_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6ss_trig_clk = { - .halt_reg = 0x250a0, - .halt_check = BRANCH_HALT_VOTED, - .clkr = { - .enable_reg = 0x250a0, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_trig_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_qdss_dap_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_qdss_at_clk = { .halt_reg = 0x2d038, .halt_check = BRANCH_HALT_VOTED, @@ -2837,24 +2693,6 @@ static struct clk_branch gcc_sys_noc_at_clk = { }, }; -static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { - .halt_reg = 0x2e030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2e030, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_sys_noc_wcss_ahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_wcss_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_uniphy0_ahb_clk = { .halt_reg = 0x16010, .halt_check = BRANCH_HALT, @@ -3070,204 +2908,6 @@ static struct clk_branch gcc_usb0_sleep_clk = { }, }; -static struct clk_branch gcc_wcss_axim_clk = { - .halt_reg = 0x2505c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2505c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_axim_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_system_noc_bfdcd_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_axis_clk = { - .halt_reg = 0x25060, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x25060, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_axis_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_system_noc_bfdcd_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = { - .halt_reg = 0x25048, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x25048, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_apb_bdg_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_qdss_dap_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = { - .halt_reg = 0x25038, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x25038, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_apb_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_qdss_dap_div_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = { - .halt_reg = 0x2504c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2504c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_atb_bdg_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_qdss_at_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { - .halt_reg = 0x2503c, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2503c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_atb_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_qdss_at_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = { - .halt_reg = 0x25050, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x25050, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_nts_bdg_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_qdss_tsctr_div2_clk_src.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { - .halt_reg = 0x25040, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x25040, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_nts_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_qdss_tsctr_div2_clk_src.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_ecahb_clk = { - .halt_reg = 0x25058, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x25058, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_ecahb_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_wcss_ahb_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_mst_async_bdg_clk = { - .halt_reg = 0x2e0b0, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2e0b0, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_mst_async_bdg_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_system_noc_bfdcd_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_slv_async_bdg_clk = { - .halt_reg = 0x2e0b4, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x2e0b4, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_slv_async_bdg_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_system_noc_bfdcd_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_xo_clk = { .halt_reg = 0x34018, .halt_check = BRANCH_HALT, @@ -3500,15 +3140,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr, [GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr, [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, - [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, - [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, - [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, [GCC_Q6_AXIM_CLK_SRC] = &gcc_q6_axim_clk_src.clkr, - [GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr, - [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, - [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, - [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, - [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, [GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr, [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr, @@ -3537,7 +3169,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr, [GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr, [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr, - [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr, [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr, [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr, @@ -3558,17 +3189,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr, [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, [GCC_WCSS_AHB_CLK_SRC] = &gcc_wcss_ahb_clk_src.clkr, - [GCC_WCSS_AXIM_CLK] = &gcc_wcss_axim_clk.clkr, - [GCC_WCSS_AXIS_CLK] = &gcc_wcss_axis_clk.clkr, - [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr, - [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, - [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr, - [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, - [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr, - [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, - [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, - [GCC_WCSS_MST_ASYNC_BDG_CLK] = &gcc_wcss_mst_async_bdg_clk.clkr, - [GCC_WCSS_SLV_ASYNC_BDG_CLK] = &gcc_wcss_slv_async_bdg_clk.clkr, [GCC_XO_CLK] = &gcc_xo_clk.clkr, [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr, From patchwork Wed Aug 2 14:05:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13338229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7C42C41513 for ; Wed, 2 Aug 2023 14:07:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234854AbjHBOHO (ORCPT ); Wed, 2 Aug 2023 10:07:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234756AbjHBOHK (ORCPT ); Wed, 2 Aug 2023 10:07:10 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5491426B6; Wed, 2 Aug 2023 07:06:57 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 372ATWqS009881; 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Wed, 2 Aug 2023 14:06:51 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 2 Aug 2023 07:06:44 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v5 03/11] clk: qcom: ipq9574: remove q6 bring up clocks Date: Wed, 2 Aug 2023 19:35:58 +0530 Message-ID: <20230802140606.2041889-4-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> References: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ZvAkE3XOR2W9_enuKdU0YXor8k5co25G X-Proofpoint-GUID: ZvAkE3XOR2W9_enuKdU0YXor8k5co25G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_09,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 phishscore=0 adultscore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020125 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org In multipd model Q6 firmware takes care of bringup clocks, so remove them from gcc driver. Signed-off-by: Manikanta Mylavarapu --- Changes in v5: - Rebased on linux-next. Changes in v4: - In V3 series this patch is [04/11]. Here it's moved to [03/11] because to compile dt-bindings patches. Changes in v3: - Rebased on linux-next. drivers/clk/qcom/gcc-ipq9574.c | 326 --------------------------------- 1 file changed, 326 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 8f430367299e..8142b06d019d 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -2571,24 +2571,6 @@ static struct clk_rcg2 system_noc_bfdcd_clk_src = { }, }; -static struct clk_branch gcc_q6ss_boot_clk = { - .halt_reg = 0x25080, - .halt_check = BRANCH_HALT_SKIP, - .clkr = { - .enable_reg = 0x25080, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_boot_clk", - .parent_hws = (const struct clk_hw *[]) { - &system_noc_bfdcd_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_nssnoc_snoc_clk = { .halt_reg = 0x17028, .clkr = { @@ -2659,91 +2641,6 @@ static struct clk_rcg2 wcss_ahb_clk_src = { }, }; -static struct clk_branch gcc_q6_ahb_clk = { - .halt_reg = 0x25014, - .clkr = { - .enable_reg = 0x25014, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_ahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6_ahb_s_clk = { - .halt_reg = 0x25018, - .clkr = { - .enable_reg = 0x25018, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_ahb_s_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_ecahb_clk = { - .halt_reg = 0x25058, - .clkr = { - .enable_reg = 0x25058, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_ecahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_acmt_clk = { - .halt_reg = 0x2505c, - .clkr = { - .enable_reg = 0x2505c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_acmt_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { - .halt_reg = 0x2e030, - .clkr = { - .enable_reg = 0x2e030, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_sys_noc_wcss_ahb_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_ahb_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = { F(24000000, P_XO, 1, 0, 0), F(133333333, P_GPLL0, 6, 0, 0), @@ -2764,23 +2661,6 @@ static struct clk_rcg2 wcss_axi_m_clk_src = { }, }; -static struct clk_branch gcc_anoc_wcss_axi_m_clk = { - .halt_reg = 0x2e0a8, - .clkr = { - .enable_reg = 0x2e0a8, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_anoc_wcss_axi_m_clk", - .parent_hws = (const struct clk_hw *[]) { - &wcss_axi_m_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static const struct freq_tbl ftbl_qdss_at_clk_src[] = { F(240000000, P_GPLL4, 5, 0, 0), { } @@ -2799,40 +2679,6 @@ static struct clk_rcg2 qdss_at_clk_src = { }, }; -static struct clk_branch gcc_q6ss_atbm_clk = { - .halt_reg = 0x2501c, - .clkr = { - .enable_reg = 0x2501c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_atbm_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_at_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { - .halt_reg = 0x2503c, - .clkr = { - .enable_reg = 0x2503c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_atb_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_at_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_nssnoc_atb_clk = { .halt_reg = 0x17014, .clkr = { @@ -3069,40 +2915,6 @@ static struct clk_fixed_factor qdss_tsctr_div2_clk_src = { }, }; -static struct clk_branch gcc_q6_tsctr_1to2_clk = { - .halt_reg = 0x25020, - .clkr = { - .enable_reg = 0x25020, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_tsctr_1to2_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_tsctr_div2_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { - .halt_reg = 0x25040, - .clkr = { - .enable_reg = 0x25040, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_nts_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_tsctr_div2_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_qdss_tsctr_div2_clk = { .halt_reg = 0x2d044, .clkr = { @@ -3277,74 +3089,6 @@ static struct clk_branch gcc_qdss_tsctr_div16_clk = { }, }; -static struct clk_branch gcc_q6ss_pclkdbg_clk = { - .halt_reg = 0x25024, - .clkr = { - .enable_reg = 0x25024, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_pclkdbg_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_q6ss_trig_clk = { - .halt_reg = 0x25068, - .clkr = { - .enable_reg = 0x25068, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6ss_trig_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = { - .halt_reg = 0x25038, - .clkr = { - .enable_reg = 0x25038, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_apb_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { - .halt_reg = 0x25044, - .clkr = { - .enable_reg = 0x25044, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_dbg_ifc_dapbus_clk", - .parent_hws = (const struct clk_hw *[]) { - &qdss_dap_sync_clk_src.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_qdss_dap_clk = { .halt_reg = 0x2d058, .clkr = { @@ -3466,58 +3210,6 @@ static struct clk_rcg2 q6_axi_clk_src = { }, }; -static struct clk_branch gcc_q6_axim_clk = { - .halt_reg = 0x2500c, - .clkr = { - .enable_reg = 0x2500c, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_q6_axim_clk", - .parent_hws = (const struct clk_hw *[]) { - &q6_axi_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_wcss_q6_tbu_clk = { - .halt_reg = 0x12050, - .halt_check = BRANCH_HALT_DELAY, - .clkr = { - .enable_reg = 0xb00c, - .enable_mask = BIT(6), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_wcss_q6_tbu_clk", - .parent_hws = (const struct clk_hw *[]) { - &q6_axi_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_mem_noc_q6_axi_clk = { - .halt_reg = 0x19010, - .clkr = { - .enable_reg = 0x19010, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_mem_noc_q6_axi_clk", - .parent_hws = (const struct clk_hw *[]) { - &q6_axi_clk_src.clkr.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static const struct freq_tbl ftbl_q6_axim2_clk_src[] = { F(342857143, P_GPLL4, 3.5, 0, 0), { } @@ -4067,16 +3759,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr, [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr, [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr, - [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, - [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, - [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, - [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr, - [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, [WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr, - [GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr, [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, - [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, - [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr, @@ -4089,27 +3773,18 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr, [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr, [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, - [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, - [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, [GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr, [GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr, [GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr, [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr, [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr, [GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr, - [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, - [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, - [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, - [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr, [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, [GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr, [GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr, [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr, [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr, - [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, - [GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr, - [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr, [Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr, [NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr, [GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr, @@ -4133,7 +3808,6 @@ static struct clk_regmap *gcc_ipq9574_clks[] = { [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr, [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr, [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, - [GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr, [UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr, [NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr, [GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr, From patchwork Wed Aug 2 14:05:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13338230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BCBEC001DF for ; Wed, 2 Aug 2023 14:07:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234823AbjHBOH1 (ORCPT ); Wed, 2 Aug 2023 10:07:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234818AbjHBOHO (ORCPT ); Wed, 2 Aug 2023 10:07:14 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A17D2D74; Wed, 2 Aug 2023 07:07:03 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 372AHdm1029690; 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Wed, 2 Aug 2023 14:06:59 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 2 Aug 2023 07:06:51 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v5 04/11] dt-bindings: clock: qcom: gcc-ipq5332: remove q6 bring up clock macros Date: Wed, 2 Aug 2023 19:35:59 +0530 Message-ID: <20230802140606.2041889-5-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> References: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: KgpsElx3AewPptY4Dkc_UBMQ0MJrP4RO X-Proofpoint-ORIG-GUID: KgpsElx3AewPptY4Dkc_UBMQ0MJrP4RO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_09,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020125 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org In multipd model Q6 firmware takes care of bringup clocks, so remove them. Signed-off-by: Manikanta Mylavarapu Reviewed-by: Krzysztof Kozlowski --- Changes in v5: - No changes. Changes in v4: - Pick up R-b tag Changes in v3: - Rebased on linux-next include/dt-bindings/clock/qcom,ipq5332-gcc.h | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h index 8a405a0a96d0..da9b507c30bf 100644 --- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h @@ -96,15 +96,7 @@ #define GCC_PCNOC_BFDCD_CLK_SRC 87 #define GCC_PCNOC_LPASS_CLK 88 #define GCC_PRNG_AHB_CLK 89 -#define GCC_Q6_AHB_CLK 90 -#define GCC_Q6_AHB_S_CLK 91 -#define GCC_Q6_AXIM_CLK 92 #define GCC_Q6_AXIM_CLK_SRC 93 -#define GCC_Q6_AXIS_CLK 94 -#define GCC_Q6_TSCTR_1TO2_CLK 95 -#define GCC_Q6SS_ATBM_CLK 96 -#define GCC_Q6SS_PCLKDBG_CLK 97 -#define GCC_Q6SS_TRIG_CLK 98 #define GCC_QDSS_AT_CLK 99 #define GCC_QDSS_AT_CLK_SRC 100 #define GCC_QDSS_CFG_AHB_CLK 101 @@ -134,7 +126,6 @@ #define GCC_SNOC_PCIE3_2LANE_S_CLK 125 #define GCC_SNOC_USB_CLK 126 #define GCC_SYS_NOC_AT_CLK 127 -#define GCC_SYS_NOC_WCSS_AHB_CLK 128 #define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129 #define GCC_UNIPHY0_AHB_CLK 130 #define GCC_UNIPHY0_SYS_CLK 131 @@ -155,17 +146,6 @@ #define GCC_USB0_PIPE_CLK 146 #define GCC_USB0_SLEEP_CLK 147 #define GCC_WCSS_AHB_CLK_SRC 148 -#define GCC_WCSS_AXIM_CLK 149 -#define GCC_WCSS_AXIS_CLK 150 -#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 151 -#define GCC_WCSS_DBG_IFC_APB_CLK 152 -#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 153 -#define GCC_WCSS_DBG_IFC_ATB_CLK 154 -#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 155 -#define GCC_WCSS_DBG_IFC_NTS_CLK 156 -#define GCC_WCSS_ECAHB_CLK 157 -#define GCC_WCSS_MST_ASYNC_BDG_CLK 158 -#define GCC_WCSS_SLV_ASYNC_BDG_CLK 159 #define GCC_XO_CLK 160 #define GCC_XO_CLK_SRC 161 #define GCC_XO_DIV4_CLK 162 From patchwork Wed Aug 2 14:06:00 2023 Content-Type: text/plain; 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Wed, 2 Aug 2023 14:07:06 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 2 Aug 2023 07:06:59 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v5 05/11] dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macros Date: Wed, 2 Aug 2023 19:36:00 +0530 Message-ID: <20230802140606.2041889-6-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> References: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: zVfZVp48ZgLhtpBy315S-n7o5gGXhZau X-Proofpoint-ORIG-GUID: zVfZVp48ZgLhtpBy315S-n7o5gGXhZau X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_09,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 suspectscore=0 bulkscore=0 adultscore=0 impostorscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020125 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org In multipd model Q6 firmware takes care of bringup clocks, so remove them. Signed-off-by: Manikanta Mylavarapu Reviewed-by: Krzysztof Kozlowski --- Changes in v5: - No changes Changes in v4: - Pick up R-b tag Changes in v3: - Rebased on linux-next include/dt-bindings/clock/qcom,ipq9574-gcc.h | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index 08fd3a37acaa..9217b90f6847 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -132,16 +132,8 @@ #define GCC_NSSNOC_SNOC_1_CLK 123 #define GCC_QDSS_ETR_USB_CLK 124 #define WCSS_AHB_CLK_SRC 125 -#define GCC_Q6_AHB_CLK 126 -#define GCC_Q6_AHB_S_CLK 127 -#define GCC_WCSS_ECAHB_CLK 128 -#define GCC_WCSS_ACMT_CLK 129 -#define GCC_SYS_NOC_WCSS_AHB_CLK 130 #define WCSS_AXI_M_CLK_SRC 131 -#define GCC_ANOC_WCSS_AXI_M_CLK 132 #define QDSS_AT_CLK_SRC 133 -#define GCC_Q6SS_ATBM_CLK 134 -#define GCC_WCSS_DBG_IFC_ATB_CLK 135 #define GCC_NSSNOC_ATB_CLK 136 #define GCC_QDSS_AT_CLK 137 #define GCC_SYS_NOC_AT_CLK 138 @@ -154,27 +146,18 @@ #define QDSS_TRACECLKIN_CLK_SRC 145 #define GCC_QDSS_TRACECLKIN_CLK 146 #define QDSS_TSCTR_CLK_SRC 147 -#define GCC_Q6_TSCTR_1TO2_CLK 148 -#define GCC_WCSS_DBG_IFC_NTS_CLK 149 #define GCC_QDSS_TSCTR_DIV2_CLK 150 #define GCC_QDSS_TS_CLK 151 #define GCC_QDSS_TSCTR_DIV4_CLK 152 #define GCC_NSS_TS_CLK 153 #define GCC_QDSS_TSCTR_DIV8_CLK 154 #define GCC_QDSS_TSCTR_DIV16_CLK 155 -#define GCC_Q6SS_PCLKDBG_CLK 156 -#define GCC_Q6SS_TRIG_CLK 157 -#define GCC_WCSS_DBG_IFC_APB_CLK 158 -#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 159 #define GCC_QDSS_DAP_CLK 160 #define GCC_QDSS_APB2JTAG_CLK 161 #define GCC_QDSS_TSCTR_DIV3_CLK 162 #define QPIC_IO_MACRO_CLK_SRC 163 #define GCC_QPIC_IO_MACRO_CLK 164 #define Q6_AXI_CLK_SRC 165 -#define GCC_Q6_AXIM_CLK 166 -#define GCC_WCSS_Q6_TBU_CLK 167 -#define GCC_MEM_NOC_Q6_AXI_CLK 168 #define Q6_AXIM2_CLK_SRC 169 #define NSSNOC_MEMNOC_BFDCD_CLK_SRC 170 #define GCC_NSSNOC_MEMNOC_CLK 171 @@ -199,7 +182,6 @@ #define GCC_UNIPHY2_SYS_CLK 190 #define GCC_CMN_12GPLL_SYS_CLK 191 #define GCC_NSSNOC_XO_DCD_CLK 192 -#define GCC_Q6SS_BOOT_CLK 193 #define UNIPHY_SYS_CLK_SRC 194 #define NSS_TS_CLK_SRC 195 #define GCC_ANOC_PCIE0_1LANE_M_CLK 196 From patchwork Wed Aug 2 14:06:01 2023 Content-Type: text/plain; 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Wed, 2 Aug 2023 14:07:13 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 2 Aug 2023 07:07:06 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v5 06/11] firmware: qcom_scm: ipq5332: add support to pass metadata size Date: Wed, 2 Aug 2023 19:36:01 +0530 Message-ID: <20230802140606.2041889-7-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> References: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 7Qk7Dru2vwL0rYmV7gZ0ZPoX1tfXOujZ X-Proofpoint-GUID: 7Qk7Dru2vwL0rYmV7gZ0ZPoX1tfXOujZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_09,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 clxscore=1015 mlxscore=0 suspectscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020125 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org IPQ5332 security software running under trustzone requires metadata size. With V2 cmd, pass metadata size as well. Signed-off-by: Manikanta Mylavarapu --- Changes in v5: - Rebased on linux-next Changes in v4: - Rebased on linux-next drivers/firmware/qcom_scm.c | 8 ++++++++ drivers/firmware/qcom_scm.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 06fe8aca870d..5e1ff137ab52 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -495,6 +495,14 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, desc.args[1] = mdata_phys; + if (__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, + QCOM_SCM_PAS_INIT_IMAGE_V2)) { + desc.cmd = QCOM_SCM_PAS_INIT_IMAGE_V2; + desc.arginfo = + QCOM_SCM_ARGS(3, QCOM_SCM_VAL, QCOM_SCM_RW, QCOM_SCM_VAL); + desc.args[2] = size; + } + ret = qcom_scm_call(__scm->dev, &desc, &res); qcom_scm_bw_disable(); diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index e6e512bd57d1..6ab5e7c77e8d 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -91,6 +91,7 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_SVC_PIL 0x02 #define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01 +#define QCOM_SCM_PAS_INIT_IMAGE_V2 0x1a #define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02 #define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05 #define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06 From patchwork Wed Aug 2 14:06:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13338233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC7DDC04A6A for ; Wed, 2 Aug 2023 14:08:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233493AbjHBOHy (ORCPT ); Wed, 2 Aug 2023 10:07:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233613AbjHBOHj (ORCPT ); Wed, 2 Aug 2023 10:07:39 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 930522D76; Wed, 2 Aug 2023 07:07:26 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 372Cr2N8006885; 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Wed, 2 Aug 2023 14:07:20 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 2 Aug 2023 07:07:13 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v5 07/11] firmware: qcom_scm: ipq5332: add msa lock/unlock support Date: Wed, 2 Aug 2023 19:36:02 +0530 Message-ID: <20230802140606.2041889-8-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> References: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Q03FPkwOjgvKNB4DAH79Hk6dk-scz9hj X-Proofpoint-ORIG-GUID: Q03FPkwOjgvKNB4DAH79Hk6dk-scz9hj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_09,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 adultscore=0 mlxlogscore=999 impostorscore=0 mlxscore=0 phishscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020125 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org IPQ5332 user pd remoteproc firmwares need to be locked with MSA(modem secure access) features. This patch add support to lock/unlock MSA features. Signed-off-by: Manikanta Mylavarapu --- Changes in v5: - Moved to EXPORT_SYMBOL_GPL() because scm driver moved to using EXPORT_SYMBOL_GPL() now. Changes in v4: - Rebased on linux-next drivers/firmware/qcom_scm.c | 78 ++++++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 2 + include/linux/firmware/qcom/qcom_scm.h | 2 + 3 files changed, 82 insertions(+) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 5e1ff137ab52..ae5c6e495e19 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -676,6 +676,84 @@ bool qcom_scm_pas_supported(u32 peripheral) } EXPORT_SYMBOL_GPL(qcom_scm_pas_supported); +/** + * qcom_scm_msa_lock() - Lock given peripheral firmware region as MSA + * + * @peripheral: peripheral id + * + * Return 0 on success. + */ +int qcom_scm_msa_lock(u32 peripheral) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_MSA_LOCK, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = peripheral, + .owner = ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + + if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, + QCOM_SCM_MSA_LOCK)) + return 0; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + ret = qcom_scm_bw_enable(); + if (ret) + return ret; + + ret = qcom_scm_call(__scm->dev, &desc, &res); + qcom_scm_bw_disable(); + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} +EXPORT_SYMBOL_GPL(qcom_scm_msa_lock); + +/** + * qcom_scm_msa_unlock() - Unlock given peripheral MSA firmware region + * + * @peripheral: peripheral id + * + * Return 0 on success. + */ +int qcom_scm_msa_unlock(u32 peripheral) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_PIL, + .cmd = QCOM_SCM_MSA_UNLOCK, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = peripheral, + .owner = ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + + if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, + QCOM_SCM_MSA_UNLOCK)) + return 0; + + ret = qcom_scm_clk_enable(); + if (ret) + return ret; + + ret = qcom_scm_bw_enable(); + if (ret) + return ret; + + ret = qcom_scm_call(__scm->dev, &desc, &res); + qcom_scm_bw_disable(); + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} +EXPORT_SYMBOL_GPL(qcom_scm_msa_unlock); + static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) { struct qcom_scm_desc desc = { diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 6ab5e7c77e8d..9480b0b57c3d 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -97,6 +97,8 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06 #define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07 #define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a +#define QCOM_SCM_MSA_LOCK 0x24 +#define QCOM_SCM_MSA_UNLOCK 0x25 #define QCOM_SCM_SVC_IO 0x05 #define QCOM_SCM_IO_READ 0x01 diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index 0c091a3f6d49..58c476941e71 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -81,6 +81,8 @@ extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, extern int qcom_scm_pas_auth_and_reset(u32 peripheral); extern int qcom_scm_pas_shutdown(u32 peripheral); extern bool qcom_scm_pas_supported(u32 peripheral); +extern int qcom_scm_msa_lock(u32 peripheral); +extern int qcom_scm_msa_unlock(u32 peripheral); extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); From patchwork Wed Aug 2 14:06:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13338234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD715C04E69 for ; Wed, 2 Aug 2023 14:08:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234488AbjHBOIR (ORCPT ); Wed, 2 Aug 2023 10:08:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234722AbjHBOHt (ORCPT ); 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Wed, 02 Aug 2023 14:07:29 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 372E7S2D023439 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Aug 2023 14:07:28 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 2 Aug 2023 07:07:21 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v5 08/11] remoteproc: qcom: q6v5: Add multipd interrupts support Date: Wed, 2 Aug 2023 19:36:03 +0530 Message-ID: <20230802140606.2041889-9-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> References: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: k5Q1c_cM8dvP9wD7IN9D6DtXhHJaV6Rj X-Proofpoint-ORIG-GUID: k5Q1c_cM8dvP9wD7IN9D6DtXhHJaV6Rj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_09,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 mlxlogscore=807 bulkscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020125 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org In multipd model, root & user pd remoteproc's interrupts are different. User pd needs additional interrupts like spawn. Instead of going with qcom_q6v5_init(), we defined a new function to register userpd rproc interrupts in mpd driver. Since userpd rproc uses some of common interrupts like fatal, ready, static is removed from ISR handler and used in userpd interrupt registration. Signed-off-by: Manikanta Mylavarapu --- Changes in v5: - Exported symbols to resolve errors reported here https://lore.kernel.org/oe-kbuild-all/202307301307.LGjSxmY8-lkp@intel.com/ Changes in v4: - Rebased on linux-next Changes in v3: - Rebased on linux-next drivers/remoteproc/qcom_q6v5.c | 41 +++++++++++++++++++++++++++++++--- drivers/remoteproc/qcom_q6v5.h | 11 +++++++++ 2 files changed, 49 insertions(+), 3 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c index 192c7aa0e39e..f8f05fd686e5 100644 --- a/drivers/remoteproc/qcom_q6v5.c +++ b/drivers/remoteproc/qcom_q6v5.c @@ -118,7 +118,7 @@ static irqreturn_t q6v5_wdog_interrupt(int irq, void *data) return IRQ_HANDLED; } -static irqreturn_t q6v5_fatal_interrupt(int irq, void *data) +irqreturn_t q6v5_fatal_interrupt(int irq, void *data) { struct qcom_q6v5 *q6v5 = data; size_t len; @@ -138,8 +138,9 @@ static irqreturn_t q6v5_fatal_interrupt(int irq, void *data) return IRQ_HANDLED; } +EXPORT_SYMBOL_GPL(q6v5_fatal_interrupt); -static irqreturn_t q6v5_ready_interrupt(int irq, void *data) +irqreturn_t q6v5_ready_interrupt(int irq, void *data) { struct qcom_q6v5 *q6v5 = data; @@ -147,6 +148,7 @@ static irqreturn_t q6v5_ready_interrupt(int irq, void *data) return IRQ_HANDLED; } +EXPORT_SYMBOL_GPL(q6v5_ready_interrupt); /** * qcom_q6v5_wait_for_start() - wait for remote processor start signal @@ -183,7 +185,17 @@ static irqreturn_t q6v5_handover_interrupt(int irq, void *data) return IRQ_HANDLED; } -static irqreturn_t q6v5_stop_interrupt(int irq, void *data) +irqreturn_t q6v5_spawn_interrupt(int irq, void *data) +{ + struct qcom_q6v5 *q6v5 = data; + + complete(&q6v5->spawn_done); + + return IRQ_HANDLED; +} +EXPORT_SYMBOL_GPL(q6v5_spawn_interrupt); + +irqreturn_t q6v5_stop_interrupt(int irq, void *data) { struct qcom_q6v5 *q6v5 = data; @@ -191,6 +203,7 @@ static irqreturn_t q6v5_stop_interrupt(int irq, void *data) return IRQ_HANDLED; } +EXPORT_SYMBOL_GPL(q6v5_stop_interrupt); /** * qcom_q6v5_request_stop() - request the remote processor to stop @@ -220,6 +233,28 @@ int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon) } EXPORT_SYMBOL_GPL(qcom_q6v5_request_stop); +/** + * qcom_q6v5_request_spawn() - request the remote processor to spawn + * @q6v5: reference to qcom_q6v5 context + * + * Return: 0 on success, negative errno on failure + */ +int qcom_q6v5_request_spawn(struct qcom_q6v5 *q6v5) +{ + int ret; + + ret = qcom_smem_state_update_bits(q6v5->spawn_state, + BIT(q6v5->spawn_bit), BIT(q6v5->spawn_bit)); + + ret = wait_for_completion_timeout(&q6v5->spawn_done, 5 * HZ); + + qcom_smem_state_update_bits(q6v5->spawn_state, + BIT(q6v5->spawn_bit), 0); + + return ret == 0 ? -ETIMEDOUT : 0; +} +EXPORT_SYMBOL_GPL(qcom_q6v5_request_spawn); + /** * qcom_q6v5_panic() - panic handler to invoke a stop on the remote * @q6v5: reference to qcom_q6v5 context diff --git a/drivers/remoteproc/qcom_q6v5.h b/drivers/remoteproc/qcom_q6v5.h index 5a859c41896e..4e1bb1a68284 100644 --- a/drivers/remoteproc/qcom_q6v5.h +++ b/drivers/remoteproc/qcom_q6v5.h @@ -18,21 +18,27 @@ struct qcom_q6v5 { struct qcom_smem_state *state; struct qmp *qmp; + struct qcom_smem_state *shutdown_state; + struct qcom_smem_state *spawn_state; struct icc_path *path; unsigned stop_bit; + unsigned shutdown_bit; + unsigned spawn_bit; int wdog_irq; int fatal_irq; int ready_irq; int handover_irq; int stop_irq; + int spawn_irq; bool handover_issued; struct completion start_done; struct completion stop_done; + struct completion spawn_done; int crash_reason; @@ -50,7 +56,12 @@ void qcom_q6v5_deinit(struct qcom_q6v5 *q6v5); int qcom_q6v5_prepare(struct qcom_q6v5 *q6v5); int qcom_q6v5_unprepare(struct qcom_q6v5 *q6v5); int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon); +int qcom_q6v5_request_spawn(struct qcom_q6v5 *q6v5); int qcom_q6v5_wait_for_start(struct qcom_q6v5 *q6v5, int timeout); unsigned long qcom_q6v5_panic(struct qcom_q6v5 *q6v5); +irqreturn_t q6v5_fatal_interrupt(int irq, void *data); +irqreturn_t q6v5_ready_interrupt(int irq, void *data); +irqreturn_t q6v5_spawn_interrupt(int irq, void *data); +irqreturn_t q6v5_stop_interrupt(int irq, void *data); #endif From patchwork Wed Aug 2 14:06:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13338235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EBC4C05051 for ; Wed, 2 Aug 2023 14:08:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235035AbjHBOIS (ORCPT ); Wed, 2 Aug 2023 10:08:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234969AbjHBOIH (ORCPT ); Wed, 2 Aug 2023 10:08:07 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBB342101; Wed, 2 Aug 2023 07:07:42 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 372AIRnA021219; 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Wed, 2 Aug 2023 14:07:35 GMT Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 2 Aug 2023 07:07:28 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v5 09/11] remoteproc: qcom: Add Hexagon based multipd rproc driver Date: Wed, 2 Aug 2023 19:36:04 +0530 Message-ID: <20230802140606.2041889-10-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> References: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: jZiCxt3UeXywDwTWIdYSqHNrVXnmGrFO X-Proofpoint-ORIG-GUID: jZiCxt3UeXywDwTWIdYSqHNrVXnmGrFO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_09,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 suspectscore=0 clxscore=1015 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020125 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org It adds support to bring up remoteproc's on multipd model. Pd means protection domain. It's similar to process in Linux. Here QDSP6 processor runs each wifi radio functionality on a separate process. One process can't access other process resources, so this is termed as PD i.e protection domain. Here we have two pd's called root and user pd. We can correlate Root pd as root and user pd as user in linux. Root pd has more privileges than user pd. Root will provide services to user pd. From remoteproc driver perspective, root pd corresponds to QDSP6 processor bring up and user pd corresponds to Wifi radio (WCSS) bring up. Here WCSS(user) PD is dependent on Q6(root) PD, so first q6 pd should be up before wcss pd. After wcss pd goes down, q6 pd should be turned off. APPS QDSP6 ------- ------------- | | Crash notification | | ------ | |<---------------------|----------|-------|User| | | | | |->|PD1 | | | | ------- | | ------ | | | | | | | |Root | Start/stop Q6 | | R | | | |PD |<---------------------|->| | | | |rproc| Crash notification | | O | | | | | | | | | | |User |Start/stop UserPD1 | | O | | | |PD1 |----------------------|->| |-|----| |rproc| | | T | | | | | | | | | | |User |Start/stop UserPD2 | | P | | | |PD2 |----------------------|->| |-|----| |rproc| | | D | | | | | | ------- | | ------ | | Crash notification | | |->|User| | |<---------------------|----------|-------|PD2 | ------- | | ------ ------------ IPQ5332, IPQ9574 supports multipd remoteproc driver. Signed-off-by: Manikanta Mylavarapu --- Changes in v5: - Fixed all comments and rebased on linux-next. - Removed EPROBE_DEFER dance. Changes in v4: - Fixed all comments and rebased on linux-next. - All userpd's rproc handles stored in linked list. Get userpd rproc handles whenever required from list instead of traversing with 'for_each_available_child_of_node'. - Removed data members from compatible specific data structure. Because these are required for user pd's. Since we removed user pd compatible, then no need of this data members. - In probe itself, traverse for each userpd and call 'q6_register_userpd()'. In case of failure, call 'q6_release_resources()' to clear already allocated user pd rproc's. Changes in v3: - Fixed all comments and rebased on linux-next. - Removed WCSS userpd compatibles. - Removed AHB/PCIE terms from driver. - Removed logic to get ASID from DT node, instead computed from UserPD spawn bit no. - IPQ5018 support is dropped because it's base port patches not yet merged so added IPQ5332 support. - Added msa lock, unlock scm calls for WCSS user pd up/down. - Added bootinfo support to share userpd load-address & size to QDSP6 root pd. Changes in v2: - Common functionalities moved to seperate patches - qcom_get_pd_asid() moved to mpd driver - Last DMA block alone memset to zero - Added diagram to show how userpd data is organized and sent to trustzone - Rewritten commit message since most of the content available in cover page - Removed 'remote_id' becuase it's not required for bring up. drivers/remoteproc/Kconfig | 19 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/qcom_q6v5_mpd.c | 802 +++++++++++++++++++++++++++++ 3 files changed, 822 insertions(+) create mode 100644 drivers/remoteproc/qcom_q6v5_mpd.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 48845dc8fa85..f5592e91c1a2 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -234,6 +234,25 @@ config QCOM_Q6V5_PAS CDSP (Compute DSP), MPSS (Modem Peripheral SubSystem), and SLPI (Sensor Low Power Island). +config QCOM_Q6V5_MPD + tristate "Qualcomm Hexagon based MPD model Peripheral Image Loader" + depends on OF && ARCH_QCOM + depends on QCOM_SMEM + depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n + depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n + depends on QCOM_SYSMON || QCOM_SYSMON=n + depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=n + depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=n + select QCOM_MDT_LOADER + select QCOM_PIL_INFO + select QCOM_Q6V5_COMMON + select QCOM_RPROC_COMMON + select QCOM_SCM + help + Say y here to support the Qualcomm Secure Peripheral Image Loader + for the Hexagon based MultiPD model remote processors on e.g. IPQ5018. + This is trustZone wireless subsystem. + config QCOM_Q6V5_WCSS tristate "Qualcomm Hexagon based WCSS Peripheral Image Loader" depends on OF && ARCH_QCOM diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 91314a9b43ce..b64051080ec1 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_QCOM_PIL_INFO) += qcom_pil_info.o obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o obj-$(CONFIG_QCOM_Q6V5_COMMON) += qcom_q6v5.o obj-$(CONFIG_QCOM_Q6V5_ADSP) += qcom_q6v5_adsp.o +obj-$(CONFIG_QCOM_Q6V5_MPD) += qcom_q6v5_mpd.o obj-$(CONFIG_QCOM_Q6V5_MSS) += qcom_q6v5_mss.o obj-$(CONFIG_QCOM_Q6V5_PAS) += qcom_q6v5_pas.o obj-$(CONFIG_QCOM_Q6V5_WCSS) += qcom_q6v5_wcss.o diff --git a/drivers/remoteproc/qcom_q6v5_mpd.c b/drivers/remoteproc/qcom_q6v5_mpd.c new file mode 100644 index 000000000000..b133285888c7 --- /dev/null +++ b/drivers/remoteproc/qcom_q6v5_mpd.c @@ -0,0 +1,802 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2018 Linaro Ltd. + * Copyright (C) 2014 Sony Mobile Communications AB + * Copyright (c) 2012-2018, 2021 The Linux Foundation. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "qcom_common.h" +#include "qcom_q6v5.h" + +#include "remoteproc_internal.h" + +#define WCSS_CRASH_REASON 421 +#define WCSS_SMEM_HOST 1 + +#define WCNSS_PAS_ID 6 +#define MPD_WCNSS_PAS_ID 0xD + +#define BUF_SIZE 35 + +#define MAX_FIRMWARE 3 + +#define RPD_SWID MPD_WCNSS_PAS_ID +#define UPD_SWID 0x12 +#define REMOTE_PID 1 +#define UPD_BOOT_INFO_SMEM_SIZE 4096 +#define UPD_BOOT_INFO_HEADER_TYPE 0x2 +#define UPD_BOOT_INFO_SMEM_ID 507 +#define VERSION2 2 + +static LIST_HEAD(upd_rproc_list); +enum { + Q6_IPQ, + WCSS_IPQ, +}; + +/** + * struct userpd_boot_info_header - header of user pd bootinfo + * @type: type of bootinfo passing over smem + * @length: length of header in bytes + */ +struct userpd_boot_info_header { + u8 type; + u8 length; +}; + +/** + * struct userpd_boot_info - holds info required to boot user pd + * @header: pointer to header + * @pid: unique id represents each user pd process + * @bootaddr: load address of user pd firmware + * @data_size: user pd firmware memory size + */ +struct userpd_boot_info { + struct userpd_boot_info_header header; + u8 pid; + u32 bootaddr; + u32 data_size; +} __packed; + +struct q6_wcss { + struct device *dev; + struct qcom_rproc_glink glink_subdev; + struct qcom_rproc_ssr ssr_subdev; + struct qcom_q6v5 q6; + phys_addr_t mem_phys; + phys_addr_t mem_reloc; + void *mem_region; + size_t mem_size; + u8 pd_asid; + const struct wcss_data *desc; + const char **firmware; + u32 version; +}; + +struct wcss_data { + u32 pasid; + bool share_upd_info_to_q6; +}; + +/** + * qcom_get_pd_asid() - get the pd asid number from PD spawn bit + * @rproc: rproc handle + * + * Returns asid on success + */ +static u8 qcom_get_pd_asid(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + u8 bit = wcss->q6.spawn_bit; + + return bit / 8; +} + +static int q6_wcss_start(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + int ret; + const struct wcss_data *desc = wcss->desc; + + qcom_q6v5_prepare(&wcss->q6); + + ret = qcom_scm_pas_auth_and_reset(desc->pasid); + if (ret) { + dev_err(wcss->dev, "wcss_reset failed\n"); + return ret; + } + + ret = qcom_q6v5_wait_for_start(&wcss->q6, 5 * HZ); + if (ret == -ETIMEDOUT) + dev_err(wcss->dev, "start timed out\n"); + + return ret; +} + +static int q6_wcss_spawn_pd(struct rproc *rproc) +{ + int ret; + struct q6_wcss *wcss = rproc->priv; + + ret = qcom_q6v5_request_spawn(&wcss->q6); + if (ret == -ETIMEDOUT) { + dev_err(wcss->dev, "%s spawn timedout\n", rproc->name); + return ret; + } + + ret = qcom_q6v5_wait_for_start(&wcss->q6, msecs_to_jiffies(10000)); + if (ret == -ETIMEDOUT) { + dev_err(wcss->dev, "%s start timedout\n", rproc->name); + wcss->q6.running = false; + return ret; + } + wcss->q6.running = true; + return ret; +} + +static int wcss_pd_start(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + u32 pasid = (wcss->pd_asid << 8) | UPD_SWID; + int ret; + + ret = qcom_scm_msa_lock(pasid); + if (ret) { + dev_err(wcss->dev, "failed to power up pd\n"); + return ret; + } + + if (wcss->q6.spawn_bit) { + ret = q6_wcss_spawn_pd(rproc); + if (ret) + return ret; + } + + return ret; +} + +static int q6_wcss_stop(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + const struct wcss_data *desc = wcss->desc; + int ret; + + ret = qcom_scm_pas_shutdown(desc->pasid); + if (ret) { + dev_err(wcss->dev, "not able to shutdown\n"); + return ret; + } + qcom_q6v5_unprepare(&wcss->q6); + + return 0; +} + +/** + * wcss_pd_stop() - Stop WCSS user pd + * @rproc: rproc handle + * + * Stop root pd after user pd down. Root pd + * is used to provide services to user pd, so + * keeping root pd alive when user pd is down + * is invalid. + * --------------------------------------------- + * + * ----------- + * |-------->| User PD1 | + * | ----------- + * | + * | + * ----- | ----------- + * | Q6 |---------------->| User Pd2 | + * ----- | ----------- + * | + * | + * | ----------- + * |--------->| User Pd3 | + * ----------- + * ---------------------------------------------- + */ +static int wcss_pd_stop(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + struct rproc *rpd_rproc = dev_get_drvdata(wcss->dev->parent); + u32 pasid = (wcss->pd_asid << 8) | UPD_SWID; + int ret; + + if (rproc->state != RPROC_CRASHED && wcss->q6.stop_bit) { + ret = qcom_q6v5_request_stop(&wcss->q6, NULL); + if (ret) { + dev_err(&rproc->dev, "pd not stopped\n"); + return ret; + } + } + + ret = qcom_scm_msa_unlock(pasid); + if (ret) { + dev_err(wcss->dev, "failed to power down pd\n"); + return ret; + } + + rproc_shutdown(rpd_rproc); + + return 0; +} + +static void *q6_wcss_da_to_va(struct rproc *rproc, u64 da, size_t len, + bool *is_iomem) +{ + struct q6_wcss *wcss = rproc->priv; + int offset; + + offset = da - wcss->mem_reloc; + if (offset < 0 || offset + len > wcss->mem_size) + return NULL; + + return wcss->mem_region + offset; +} + +/** + * share_upd_bootinfo_to_q6() - Share userpd boot info to Q6 root pd + * @rproc: rproc handle + * + * Q6 needs user pd parameters like loadaddress and + * PIL size to authenticate user pd with underlying + * security software. If authenticatoin success then + * only Q6 spawns user pd and sends spawn ack to rproc + * driver. This API is passing userpd boot info to Q6 + * over SMEM. + * + * User pd boot-info format mentioned below + *
+ * + * + * Returns 0 on success else negative value on failure. + */ +static int share_upd_bootinfo_to_q6(struct rproc *rproc) +{ + int ret; + size_t size; + u16 cnt = 0, version; + void *ptr; + struct q6_wcss *wcss = rproc->priv, *upd_wcss; + struct rproc *upd_rproc; + struct userpd_boot_info upd_bootinfo = {0}; + const struct firmware *fw; + + ret = qcom_smem_alloc(REMOTE_PID, UPD_BOOT_INFO_SMEM_ID, + UPD_BOOT_INFO_SMEM_SIZE); + if (ret && ret != -EEXIST) { + dev_err(wcss->dev, + "failed to allocate q6 bootinfo smem segment\n"); + return ret; + } + + ptr = qcom_smem_get(REMOTE_PID, UPD_BOOT_INFO_SMEM_ID, &size); + if (IS_ERR(ptr) || size != UPD_BOOT_INFO_SMEM_SIZE) { + dev_err(wcss->dev, + "Unable to acquire smp2p item(%d) ret:%ld\n", + UPD_BOOT_INFO_SMEM_ID, PTR_ERR(ptr)); + return PTR_ERR(ptr); + } + + /*Version*/ + version = VERSION2; + memcpy_toio(ptr, &version, sizeof(version)); + ptr += sizeof(version); + + list_for_each_entry(upd_rproc, &upd_rproc_list, node) + cnt++; + + /* No of elements */ + cnt = (sizeof(upd_bootinfo) * cnt); + memcpy_toio(ptr, &cnt, sizeof(u16)); + ptr += sizeof(u16); + + list_for_each_entry(upd_rproc, &upd_rproc_list, node) { + upd_wcss = upd_rproc->priv; + + /* TYPE */ + upd_bootinfo.header.type = UPD_BOOT_INFO_HEADER_TYPE; + + /* LENGTH */ + upd_bootinfo.header.length = + sizeof(upd_bootinfo) - sizeof(upd_bootinfo.header); + + /* Process ID */ + upd_bootinfo.pid = upd_wcss->pd_asid + 1; + + ret = request_firmware(&fw, upd_rproc->firmware, upd_wcss->dev); + if (ret < 0) { + dev_err(upd_wcss->dev, "request_firmware failed: %d\n", ret); + return ret; + } + + /* Load address */ + upd_bootinfo.bootaddr = rproc_get_boot_addr(upd_rproc, fw); + + /* Firmware mem size */ + upd_bootinfo.data_size = qcom_mdt_get_size(fw); + + release_firmware(fw); + + /* copy into smem */ + memcpy_toio(ptr, &upd_bootinfo, sizeof(upd_bootinfo)); + ptr += sizeof(upd_bootinfo); + } + return 0; +} + +static int q6_wcss_load(struct rproc *rproc, const struct firmware *fw) +{ + struct q6_wcss *wcss = rproc->priv; + const struct firmware *fw_hdl; + int ret; + const struct wcss_data *desc = wcss->desc; + int loop; + + /* Share user pd boot info to Q6 remote processor */ + if (desc->share_upd_info_to_q6) { + ret = share_upd_bootinfo_to_q6(rproc); + if (ret) { + dev_err(wcss->dev, + "user pd boot info sharing with q6 failed %d\n", + ret); + return ret; + } + } + + ret = qcom_mdt_load(wcss->dev, fw, rproc->firmware, + desc->pasid, wcss->mem_region, + wcss->mem_phys, wcss->mem_size, + &wcss->mem_reloc); + if (ret) + return ret; + + for (loop = 1; loop < MAX_FIRMWARE; loop++) { + if (!wcss->firmware[loop]) + continue; + + ret = request_firmware(&fw_hdl, wcss->firmware[loop], + wcss->dev); + if (ret) + continue; + + ret = qcom_mdt_load_no_init(wcss->dev, fw_hdl, + wcss->firmware[loop], 0, + wcss->mem_region, + wcss->mem_phys, + wcss->mem_size, + &wcss->mem_reloc); + + release_firmware(fw_hdl); + + if (ret) { + dev_err(wcss->dev, + "can't load %s ret:%d\n", wcss->firmware[loop], ret); + return ret; + } + } + return 0; +} + +/** + * wcss_pd_load() - Load WCSS user pd firmware + * @rproc: rproc handle + * @fw: firmware handle + * + * User pd get services from root pd. So first + * bring up root pd and then load userpd firmware. + * --------------------------------------------- + * + * ----------- + * |-------->| User PD1 | + * | ----------- + * | + * | + * ----- | ----------- + * | Q6 |---------------->| User Pd2 | + * ----- | ----------- + * | + * | + * | ----------- + * |--------->| User Pd3 | + * ----------- + * ---------------------------------------------- + * + */ +static int wcss_pd_load(struct rproc *rproc, const struct firmware *fw) +{ + struct q6_wcss *wcss = rproc->priv; + struct rproc *rpd_rproc = dev_get_drvdata(wcss->dev->parent); + u32 pasid = (wcss->pd_asid << 8) | UPD_SWID; + int ret; + + ret = rproc_boot(rpd_rproc); + if (ret) + return ret; + + return qcom_mdt_load(wcss->dev, fw, rproc->firmware, + pasid, wcss->mem_region, + wcss->mem_phys, wcss->mem_size, + &wcss->mem_reloc); +} + +static unsigned long q6_wcss_panic(struct rproc *rproc) +{ + struct q6_wcss *wcss = rproc->priv; + + return qcom_q6v5_panic(&wcss->q6); +} + +static const struct rproc_ops wcss_ops = { + .start = wcss_pd_start, + .stop = wcss_pd_stop, + .load = wcss_pd_load, + .get_boot_addr = rproc_elf_get_boot_addr, +}; + +static const struct rproc_ops q6_wcss_ops = { + .start = q6_wcss_start, + .stop = q6_wcss_stop, + .da_to_va = q6_wcss_da_to_va, + .load = q6_wcss_load, + .get_boot_addr = rproc_elf_get_boot_addr, + .panic = q6_wcss_panic, +}; + +static int q6_alloc_memory_region(struct q6_wcss *wcss) +{ + struct reserved_mem *rmem = NULL; + struct device_node *node; + struct device *dev = wcss->dev; + + if (wcss->version == Q6_IPQ) { + node = of_parse_phandle(dev->of_node, "memory-region", 0); + if (node) + rmem = of_reserved_mem_lookup(node); + + of_node_put(node); + + if (!rmem) { + dev_err(dev, "unable to acquire memory-region\n"); + return -EINVAL; + } + } else { + struct rproc *rpd_rproc = dev_get_drvdata(dev->parent); + struct q6_wcss *rpd_wcss = rpd_rproc->priv; + + wcss->mem_phys = rpd_wcss->mem_phys; + wcss->mem_reloc = rpd_wcss->mem_reloc; + wcss->mem_size = rpd_wcss->mem_size; + wcss->mem_region = rpd_wcss->mem_region; + return 0; + } + + wcss->mem_phys = rmem->base; + wcss->mem_reloc = rmem->base; + wcss->mem_size = rmem->size; + wcss->mem_region = devm_ioremap_wc(dev, wcss->mem_phys, wcss->mem_size); + if (!wcss->mem_region) { + dev_err(dev, "unable to map memory region: %pa+%pa\n", + &rmem->base, &rmem->size); + return -EBUSY; + } + + return 0; +} + +static int q6_get_inbound_irq(struct qcom_q6v5 *q6, + struct platform_device *pdev, + const char *int_name, + int index, int *pirq, + irqreturn_t (*handler)(int irq, void *data)) +{ + int ret, irq; + char *interrupt, *tmp = (char *)int_name; + struct q6_wcss *wcss = q6->rproc->priv; + + irq = platform_get_irq(pdev, index); + if (irq < 0) + return irq; + + *pirq = irq; + + interrupt = devm_kzalloc(&pdev->dev, BUF_SIZE, GFP_KERNEL); + if (!interrupt) + return -ENOMEM; + + snprintf(interrupt, BUF_SIZE, "q6v5_wcss_userpd%d_%s", wcss->pd_asid, tmp); + + ret = devm_request_threaded_irq(&pdev->dev, *pirq, + NULL, handler, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + interrupt, q6); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to acquire %s irq\n", interrupt); + return 0; +} + +static int q6_get_outbound_irq(struct qcom_q6v5 *q6, + struct platform_device *pdev, + const char *int_name) +{ + struct qcom_smem_state *tmp_state; + unsigned bit; + + tmp_state = qcom_smem_state_get(&pdev->dev, int_name, &bit); + if (IS_ERR(tmp_state)) + return dev_err_probe(&pdev->dev, PTR_ERR(tmp_state), + "failed to acquire %s state\n", int_name); + + if (!strcmp(int_name, "stop")) { + q6->state = tmp_state; + q6->stop_bit = bit; + } else if (!strcmp(int_name, "spawn")) { + q6->spawn_state = tmp_state; + q6->spawn_bit = bit; + } + + return 0; +} + +static int init_irq(struct qcom_q6v5 *q6, + struct platform_device *pdev, struct rproc *rproc, + int crash_reason, const char *load_state, + void (*handover)(struct qcom_q6v5 *q6)) +{ + int ret; + struct q6_wcss *wcss = rproc->priv; + + q6->rproc = rproc; + q6->dev = &pdev->dev; + q6->crash_reason = crash_reason; + q6->handover = handover; + + init_completion(&q6->start_done); + init_completion(&q6->stop_done); + init_completion(&q6->spawn_done); + + ret = q6_get_outbound_irq(q6, pdev, "stop"); + if (ret) + return ret; + + ret = q6_get_outbound_irq(q6, pdev, "spawn"); + if (ret) + return ret; + + /* Get pd_asid to prepare interrupt names */ + wcss->pd_asid = qcom_get_pd_asid(rproc); + + ret = q6_get_inbound_irq(q6, pdev, "fatal", 0, &q6->fatal_irq, + q6v5_fatal_interrupt); + if (ret) + return ret; + + ret = q6_get_inbound_irq(q6, pdev, "ready", 1, &q6->ready_irq, + q6v5_ready_interrupt); + if (ret) + return ret; + + ret = q6_get_inbound_irq(q6, pdev, "stop-ack", 3, &q6->stop_irq, + q6v5_stop_interrupt); + if (ret) + return ret; + + ret = q6_get_inbound_irq(q6, pdev, "spawn-ack", 2, &q6->spawn_irq, + q6v5_spawn_interrupt); + if (ret) + return ret; + return 0; +} + +static void q6_release_resources(void) +{ + struct rproc *upd_rproc; + + /* Release userpd resources */ + list_for_each_entry(upd_rproc, &upd_rproc_list, node) { + rproc_del(upd_rproc); + rproc_free(upd_rproc); + } +} + +static int q6_register_userpd(struct platform_device *pdev, + struct device_node *userpd_np) +{ + struct q6_wcss *wcss; + struct rproc *rproc = NULL; + int ret; + struct platform_device *userpd_pdev; + const char *firmware_name = NULL; + const char *label = NULL; + + ret = of_property_read_string(userpd_np, "firmware-name", + &firmware_name); + if (ret < 0) { + /* All userpd's who want to register as rproc must have firmware. + * Other than userpd like glink they don't need any firmware. + * So for glink child simply return success. + */ + if (ret == -EINVAL) { + /* Confirming userpd_np is glink node or not */ + if (!of_property_read_string(userpd_np, "label", &label)) + return 0; + } + return ret; + } + + dev_info(&pdev->dev, "%s node found\n", userpd_np->name); + + userpd_pdev = of_platform_device_create(userpd_np, userpd_np->name, + &pdev->dev); + if (!userpd_pdev) + return dev_err_probe(&pdev->dev, -ENODEV, + "failed to create %s platform device\n", + userpd_np->name); + + userpd_pdev->dev.driver = pdev->dev.driver; + rproc = rproc_alloc(&userpd_pdev->dev, userpd_pdev->name, &wcss_ops, + firmware_name, sizeof(*wcss)); + if (!rproc) { + ret = -ENOMEM; + goto free_rproc; + } + + wcss = rproc->priv; + wcss->dev = &userpd_pdev->dev; + wcss->version = WCSS_IPQ; + + ret = q6_alloc_memory_region(wcss); + if (ret) + goto free_rproc; + + ret = init_irq(&wcss->q6, userpd_pdev, rproc, + WCSS_CRASH_REASON, NULL, NULL); + if (ret) + goto free_rproc; + + rproc->auto_boot = false; + ret = rproc_add(rproc); + if (ret) + goto free_rproc; + + list_add(&rproc->node, &upd_rproc_list); + platform_set_drvdata(userpd_pdev, rproc); + qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, userpd_pdev->name); + return 0; + +free_rproc: + kfree(rproc); + return ret; +} + +static int q6_wcss_probe(struct platform_device *pdev) +{ + const struct wcss_data *desc; + struct q6_wcss *wcss; + struct rproc *rproc; + int ret; + const char **firmware; + struct device_node *userpd_np; + const struct rproc_ops *ops = &q6_wcss_ops; + + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + firmware = devm_kcalloc(&pdev->dev, MAX_FIRMWARE, + sizeof(*firmware), GFP_KERNEL); + if (!firmware) + return -ENOMEM; + + ret = of_property_read_string_array(pdev->dev.of_node, "firmware-name", + firmware, MAX_FIRMWARE); + if (ret < 0) + return ret; + + rproc = rproc_alloc(&pdev->dev, pdev->name, ops, + firmware[0], sizeof(*wcss)); + if (!rproc) + return -ENOMEM; + + wcss = rproc->priv; + wcss->dev = &pdev->dev; + wcss->desc = desc; + wcss->firmware = firmware; + wcss->version = Q6_IPQ; + + ret = q6_alloc_memory_region(wcss); + if (ret) + goto free_rproc; + + ret = qcom_q6v5_init(&wcss->q6, pdev, rproc, + WCSS_CRASH_REASON, NULL, NULL); + if (ret) + goto free_rproc; + + qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss"); + qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss"); + + rproc->auto_boot = false; + ret = rproc_add(rproc); + if (ret) + goto free_rproc; + + platform_set_drvdata(pdev, rproc); + + /* Iterate over userpd child's and register with rproc */ + for_each_available_child_of_node(pdev->dev.of_node, userpd_np) { + ret = q6_register_userpd(pdev, userpd_np); + if (ret) { + /* release resources of successfully allocated userpd rproc's */ + q6_release_resources(); + return dev_err_probe(&pdev->dev, ret, + "Failed to register userpd(%s)\n", + userpd_np->name); + } + } + return 0; + +free_rproc: + rproc_free(rproc); + + return ret; +} + +static int q6_wcss_remove(struct platform_device *pdev) +{ + struct rproc *rproc = platform_get_drvdata(pdev); + struct q6_wcss *wcss = rproc->priv; + + qcom_q6v5_deinit(&wcss->q6); + + rproc_del(rproc); + rproc_free(rproc); + + return 0; +} + +static const struct wcss_data q6_ipq5332_res_init = { + .pasid = MPD_WCNSS_PAS_ID, + .share_upd_info_to_q6 = true, +}; + +static const struct wcss_data q6_ipq9574_res_init = { + .pasid = WCNSS_PAS_ID, +}; + +static const struct of_device_id q6_wcss_of_match[] = { + { .compatible = "qcom,ipq5332-q6-mpd", .data = &q6_ipq5332_res_init }, + { .compatible = "qcom,ipq9574-q6-mpd", .data = &q6_ipq9574_res_init }, + { }, +}; +MODULE_DEVICE_TABLE(of, q6_wcss_of_match); + +static struct platform_driver q6_wcss_driver = { + .probe = q6_wcss_probe, + .remove = q6_wcss_remove, + .driver = { + .name = "qcom-q6-mpd", + .of_match_table = q6_wcss_of_match, + }, +}; +module_platform_driver(q6_wcss_driver); + +MODULE_DESCRIPTION("Hexagon WCSS Multipd Peripheral Image Loader"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Aug 2 14:06:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13338236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EED97C001DF for ; Wed, 2 Aug 2023 14:08:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234924AbjHBOIs (ORCPT ); Wed, 2 Aug 2023 10:08:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235018AbjHBOIO (ORCPT ); Wed, 2 Aug 2023 10:08:14 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABB472D67; 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Signed-off-by: Manikanta Mylavarapu --- Changes in v5: - Rebased on linux-next Changes in v4: - Rebased on linux-next arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 21 ++++++++ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 60 +++++++++++++++++++++ 2 files changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index e89e2e948603..e0e2f9238b47 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -21,6 +21,27 @@ &blsp1_i2c1 { status = "okay"; }; +&q6v5_wcss { + pd-1 { + firmware-name = "ath11k/IPQ5332/hw1.0/q6_fw1.mdt"; + interrupts-extended = <&wcss_smp2p_in 8 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 9 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 12 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 11 IRQ_TYPE_NONE>; + interrupt-names = "fatal", + "ready", + "spawn-ack", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 8>, + <&wcss_smp2p_out 9>, + <&wcss_smp2p_out 10>; + qcom,smem-state-names = "shutdown", + "stop", + "spawn"; + }; +}; + &sdhc { bus-width = <4>; max-frequency = <192000000>; diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 8bfc2db44624..1abc992ede31 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -137,6 +137,11 @@ smem@4a800000 { hwlocks = <&tcsr_mutex 0>; }; + + q6_region: wcnss@4a900000 { + reg = <0x0 0x4a900000 0x0 0x2b00000>; + no-map; + }; }; soc@0 { @@ -405,6 +410,37 @@ frame@b128000 { status = "disabled"; }; }; + + q6v5_wcss: remoteproc@d100000 { + compatible = "qcom,ipq5332-q6-mpd"; + reg = <0xd100000 0x4040>; + firmware-name = "ath11k/IPQ5332/hw1.0/q6_fw0.mdt", + "ath11k/IPQ5332/hw1.0/iu_fw.mdt"; + interrupts-extended = <&intc GIC_SPI 421 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 1 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 2 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 3 IRQ_TYPE_NONE>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + + memory-region = <&q6_region>; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + }; }; timer { @@ -414,4 +450,28 @@ timer { , ; }; + + wcss: wcss-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = ; + + mboxes = <&apcs_glb 9>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + wcss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wcss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; From patchwork Wed Aug 2 14:06:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Mylavarapu X-Patchwork-Id: 13338237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94AA4C04A6A for ; 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Wed, 2 Aug 2023 07:07:43 -0700 From: Manikanta Mylavarapu To: , , , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v5 11/11] arm64: dts: qcom: ipq9574: Add nodes to bring up multipd Date: Wed, 2 Aug 2023 19:36:06 +0530 Message-ID: <20230802140606.2041889-12-quic_mmanikan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> References: <20230802140606.2041889-1-quic_mmanikan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: blO-G6wQNZb6iPw7Gdtii4-6Cojkjtas X-Proofpoint-ORIG-GUID: blO-G6wQNZb6iPw7Gdtii4-6Cojkjtas X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_09,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 bulkscore=0 mlxlogscore=732 spamscore=0 malwarescore=0 suspectscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020125 Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org Enable nodes required for multipd remoteproc bring up. Signed-off-by: Manikanta Mylavarapu --- Changes in v5: - Rebased on linux-next Changes in v4: - Rebased on linux-next Changes in v3: - Fixed all comments and rebased on linux-next. - Removed WCSS userpd nodes from dtsi file, because it vary based on no of radio's connected. Changes in v2: - Corrected syntax like alignmnet and kept nodes in sorted order. - Added 'firmware-name' property. arch/arm64/boot/dts/qcom/ipq9574.dtsi | 59 +++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 51aba071c1eb..5d59ff1557b6 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -198,6 +198,11 @@ smem@4aa00000 { hwlocks = <&tcsr_mutex 0>; no-map; }; + + q6_region: wcnss@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x2b00000>; + no-map; + }; }; soc: soc@0 { @@ -722,6 +727,36 @@ frame@b128000 { status = "disabled"; }; }; + + q6v5_wcss: remoteproc@cd00000 { + compatible = "qcom,ipq9574-q6-mpd"; + reg = <0x0cd00000 0x4040>; + firmware-name = "ath11k/IPQ9574/hw1.0/q6_fw.mdt", + "ath11k/IPQ9574/hw1.0/m3_fw.mdt"; + interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, + <&wcss_smp2p_in 0 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 1 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 2 IRQ_TYPE_NONE>, + <&wcss_smp2p_in 3 IRQ_TYPE_NONE>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + qcom,smem-states = <&wcss_smp2p_out 0>, + <&wcss_smp2p_out 1>; + qcom,smem-state-names = "shutdown", + "stop"; + memory-region = <&q6_region>; + + glink-edge { + interrupts = ; + label = "rtr"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 8>; + }; + }; }; thermal-zones { @@ -979,4 +1014,28 @@ timer { , ; }; + + wcss: wcss-smp2p { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = ; + + mboxes = <&apcs_glb 9>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + wcss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wcss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; };