From patchwork Wed Aug 2 18:08:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13338720 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0CE1C04FDF for ; Wed, 2 Aug 2023 18:09:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229480AbjHBSJX (ORCPT ); Wed, 2 Aug 2023 14:09:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56336 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233350AbjHBSJW (ORCPT ); Wed, 2 Aug 2023 14:09:22 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 223F11FD6; Wed, 2 Aug 2023 11:09:16 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 372AZpbp024201; Wed, 2 Aug 2023 18:09:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=XNMYA4UbcbSXzfcqNjsG0H+M63r3pQMWY3iLGwCz6eI=; b=n3rDGpSaOIIvvOa3z0TXlHvTfGTAmiz6mVQm2mHrH3LEnTi7JsEJPYWVG9HwVxUSqEEJ KF+jmey5nf0CxS/psoBWzuxO6YIJ7o8GjGwsz0MrgcveFQ/Ia1rvRp7sERzxoZGmU5e4 KWdnG3QO0JZ/XKTtHi4nouk9/RgIVOjrzz9nAqsOg9hRSXQT7qCd9DjAoeZmNVveXnaZ R8uKWnAcco/P/1DoM+ijbwPjQuRC5cNSLYXBYJAk7sz4eC0SvLbHR2Z3EiZ+QdRRSH9b 4qDZc7KyUV2/wn1M1noPvJ13QP0JKssP44yc3SNzl4Y7l4k9t/GWSQuMdVclyjwpCwpM 2A== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s76jv30hs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 02 Aug 2023 18:09:08 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 372I97a6025295 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Aug 2023 18:09:07 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 2 Aug 2023 11:09:07 -0700 From: Jessica Zhang Date: Wed, 2 Aug 2023 11:08:48 -0700 Subject: [PATCH v3 1/4] drm/msm/dpu: Move DPU encoder wide_bus_en setting MIME-Version: 1.0 Message-ID: <20230802-add-widebus-support-v3-1-2661706be001@quicinc.com> References: <20230802-add-widebus-support-v3-0-2661706be001@quicinc.com> In-Reply-To: <20230802-add-widebus-support-v3-0-2661706be001@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" CC: , , , , , Jessica Zhang X-Mailer: b4 0.13-dev-034f2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690999747; l=1688; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=v5usOJssXFWNQ35+PYIdulVA0KY1v7/lvKo5ADvLodg=; b=QNRCYxZXwNhEQ6iJF9jR3Jp8PqyJPnq3RqLVQ90YhkPRfHX2FWZhFtVDARncvUcRSiRlVZI73 faEywMDRjXyC/gnvqDOn3yTDfJDa582MJ6CRchoPLRY1fWW1gTyFQnw X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 1r9A7K8T_vsxGidKUlm4BcrjMgT7qtXi X-Proofpoint-GUID: 1r9A7K8T_vsxGidKUlm4BcrjMgT7qtXi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_13,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 clxscore=1015 mlxscore=0 suspectscore=0 mlxlogscore=984 phishscore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020160 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move the setting of dpu_enc.wide_bus_en to dpu_encoder_virt_atomic_enable() so that it mirrors the setting of dpu_enc.dsc. Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index d34e684a4178..3dcd37c48aac 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1194,11 +1194,18 @@ static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, struct dpu_encoder_virt *dpu_enc = NULL; int ret = 0; struct drm_display_mode *cur_mode = NULL; + struct msm_drm_private *priv = drm_enc->dev->dev_private; + struct msm_display_info *disp_info; dpu_enc = to_dpu_encoder_virt(drm_enc); + disp_info = &dpu_enc->disp_info; dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc); + if (disp_info->intf_type == INTF_DP) + dpu_enc->wide_bus_en = msm_dp_wide_bus_available( + priv->dp[disp_info->h_tile_instance[0]]); + mutex_lock(&dpu_enc->enc_lock); cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; @@ -2383,10 +2390,6 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev, timer_setup(&dpu_enc->frame_done_timer, dpu_encoder_frame_done_timeout, 0); - if (disp_info->intf_type == INTF_DP) - dpu_enc->wide_bus_en = msm_dp_wide_bus_available( - priv->dp[disp_info->h_tile_instance[0]]); - INIT_DELAYED_WORK(&dpu_enc->delayed_off_work, dpu_encoder_off_work); dpu_enc->idle_timeout = IDLE_TIMEOUT; From patchwork Wed Aug 2 18:08:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13338722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BB75C001DF for ; Wed, 2 Aug 2023 18:09:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233683AbjHBSJY (ORCPT ); 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Wed, 02 Aug 2023 18:09:09 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 372I981M029019 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Aug 2023 18:09:08 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 2 Aug 2023 11:09:07 -0700 From: Jessica Zhang Date: Wed, 2 Aug 2023 11:08:49 -0700 Subject: [PATCH v3 2/4] drm/msm/dpu: Enable widebus for DSI INTF MIME-Version: 1.0 Message-ID: <20230802-add-widebus-support-v3-2-2661706be001@quicinc.com> References: <20230802-add-widebus-support-v3-0-2661706be001@quicinc.com> In-Reply-To: <20230802-add-widebus-support-v3-0-2661706be001@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" CC: , , , , , Jessica Zhang X-Mailer: b4 0.13-dev-034f2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690999747; l=4513; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=Jmb7gaPPbyxZ6eTsoppLJiXehRUCuRT+iijJYPs2+cU=; b=BwsbMWG5/It5A17xmItoeYf+DCp5Evl8WK4RefEVypYL40zziJcaue8lyiy7GP+NWvlFn/L5Q FnndFzDA6PyD7SXNe5C5lziuM8R8yzsXj72hkMB/zTB/+jMQsvDADZt X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: xnobuU4csV3yto4Les337RKSbORNq9qM X-Proofpoint-ORIG-GUID: xnobuU4csV3yto4Les337RKSbORNq9qM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_13,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 impostorscore=0 phishscore=0 clxscore=1015 mlxlogscore=912 bulkscore=0 lowpriorityscore=0 mlxscore=0 adultscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020160 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DPU supports a data-bus widen mode for DSI INTF. Enable this mode for all supported chipsets if widebus is enabled for DSI. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ++++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 3 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 1 + drivers/gpu/drm/msm/msm_drv.h | 6 +++++- 5 files changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 3dcd37c48aac..de08aad39e15 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1196,15 +1196,20 @@ static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, struct drm_display_mode *cur_mode = NULL; struct msm_drm_private *priv = drm_enc->dev->dev_private; struct msm_display_info *disp_info; + int index; dpu_enc = to_dpu_encoder_virt(drm_enc); disp_info = &dpu_enc->disp_info; + disp_info = &dpu_enc->disp_info; + index = disp_info->h_tile_instance[0]; + dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc); - if (disp_info->intf_type == INTF_DP) - dpu_enc->wide_bus_en = msm_dp_wide_bus_available( - priv->dp[disp_info->h_tile_instance[0]]); + if (disp_info->intf_type == INTF_DSI) + dpu_enc->wide_bus_en = msm_dsi_is_widebus_enabled(priv->dsi[index]); + else if (disp_info->intf_type == INTF_DP) + dpu_enc->wide_bus_en = msm_dp_wide_bus_available(priv->dp[index]); mutex_lock(&dpu_enc->enc_lock); cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index df88358e7037..dace6168be2d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -69,8 +69,10 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( phys_enc->hw_intf, phys_enc->hw_pp->idx); - if (intf_cfg.dsc != 0) + if (intf_cfg.dsc != 0) { cmd_mode_cfg.data_compress = true; + cmd_mode_cfg.wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent); + } if (phys_enc->hw_intf->ops.program_intf_cmd_cfg) phys_enc->hw_intf->ops.program_intf_cmd_cfg(phys_enc->hw_intf, &cmd_mode_cfg); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 8ec6505d9e78..dc6f3febb574 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -521,6 +521,9 @@ static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx, if (cmd_mode_cfg->data_compress) intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; + if (cmd_mode_cfg->wide_bus_en) + intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN; + DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 77f80531782b..c539025c418b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -50,6 +50,7 @@ struct dpu_hw_intf_status { struct dpu_hw_intf_cmd_mode_cfg { u8 data_compress; /* enable data compress between dpu and dsi */ + u8 wide_bus_en; /* enable databus widen mode */ }; /** diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 9d9d5e009163..e4f706b16aad 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -344,6 +344,7 @@ void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); +bool msm_dsi_is_widebus_enabled(struct msm_dsi *msm_dsi); struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); #else static inline void __init msm_dsi_register(void) @@ -373,7 +374,10 @@ static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) { return false; } - +static inline bool msm_dsi_is_widebus_enabled(struct msm_dsi *msm_dsi) +{ + return false; +} static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) { return NULL; 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Wed, 2 Aug 2023 18:09:08 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Wed, 2 Aug 2023 11:09:08 -0700 From: Jessica Zhang Date: Wed, 2 Aug 2023 11:08:50 -0700 Subject: [PATCH v3 3/4] drm/msm/dsi: Add DATABUS_WIDEN MDP_CTRL2 bit MIME-Version: 1.0 Message-ID: <20230802-add-widebus-support-v3-3-2661706be001@quicinc.com> References: <20230802-add-widebus-support-v3-0-2661706be001@quicinc.com> In-Reply-To: <20230802-add-widebus-support-v3-0-2661706be001@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" CC: , , , , , Jessica Zhang X-Mailer: b4 0.13-dev-034f2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690999747; l=923; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=aRMmQo7E922CFIY2TnXZRiHKSErVfoF/5a7XDvCAP28=; b=pmWB7DhlFwG9lrPGKwBaC/b8mGuaIzUSL0rIGF9c9T0LUnCb2KOZ767diCxtiyB3BSti+EZKJ QxjkwUWgzhQCA5bvhh5z96QPSWpnZs0eu268PaUrbepfqRSk/6/MMQS X-Developer-Key: i=quic_jesszhan@quicinc.com; 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Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index a4a154601114..2a7d980e12c3 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -664,6 +664,7 @@ static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap v return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK; } #define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000 +#define DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN 0x00100000 #define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f From patchwork Wed Aug 2 18:08:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13338721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21FC3C001DF for ; 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Wed, 2 Aug 2023 11:09:08 -0700 From: Jessica Zhang Date: Wed, 2 Aug 2023 11:08:51 -0700 Subject: [PATCH v3 4/4] drm/msm/dsi: Enable widebus for DSI MIME-Version: 1.0 Message-ID: <20230802-add-widebus-support-v3-4-2661706be001@quicinc.com> References: <20230802-add-widebus-support-v3-0-2661706be001@quicinc.com> In-Reply-To: <20230802-add-widebus-support-v3-0-2661706be001@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" CC: , , , , , Jessica Zhang X-Mailer: b4 0.13-dev-034f2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1690999747; l=4367; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=DXCvyanWZlBEzFDdQcRaAJkq+qVMaJpptR/l3i1PuUI=; b=8dRGerBAGh8W1OK/vYWsmvtS5zNTidozakMWR2l7sXgxAgSOgu82Pth/SbMq5d8XVVXBXdePz okcVJesK4B6BIQVoTs1SbhaQqOJeWojKYJCTO8QOJOp6OwJroNpJW06 X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Ri23xspvVR3ZG2haC3tze4TQKb5ZVQ4F X-Proofpoint-ORIG-GUID: Ri23xspvVR3ZG2haC3tze4TQKb5ZVQ4F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-02_13,2023-08-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 spamscore=0 mlxlogscore=826 bulkscore=0 suspectscore=0 clxscore=1015 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308020160 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send 48 bits of compressed data instead of 24. Enable this mode whenever DSC is enabled for supported chipsets. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/dsi/dsi.c | 5 +++++ drivers/gpu/drm/msm/dsi/dsi.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 30 ++++++++++++++++++++++++++---- 3 files changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index baab79ab6e74..4fa738dea680 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -17,6 +17,11 @@ struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) return msm_dsi_host_get_dsc_config(msm_dsi->host); } +bool msm_dsi_is_widebus_enabled(struct msm_dsi *msm_dsi) +{ + return msm_dsi_host_is_widebus_enabled(msm_dsi->host); +} + static int dsi_get_phy(struct msm_dsi *msm_dsi) { struct platform_device *pdev = msm_dsi->pdev; diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index bd3763a5d723..a557d2c1aaff 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -134,6 +134,7 @@ int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi); void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host); void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host); struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host); +bool msm_dsi_host_is_widebus_enabled(struct mipi_dsi_host *host); /* dsi phy */ struct msm_dsi_phy; diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 645927214871..231b02e5ab6e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -710,6 +710,14 @@ static void dsi_ctrl_disable(struct msm_dsi_host *msm_host) dsi_write(msm_host, REG_DSI_CTRL, 0); } +bool msm_dsi_host_is_widebus_enabled(struct mipi_dsi_host *host) +{ + struct msm_dsi_host *msm_host = to_msm_dsi_host(host); + + return msm_host->dsc && (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G && + msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0); +} + static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) { @@ -753,10 +761,16 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; dsi_write(msm_host, REG_DSI_CMD_CFG1, data); - if (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G && - msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) { + if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2); - data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE; + + if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) + data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE; + + /* TODO: Allow for video-mode support once tested/fixed */ + if (msm_dsi_host_is_widebus_enabled(&msm_host->base)) + data |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN; + dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data); } } @@ -894,6 +908,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) u32 hdisplay = mode->hdisplay; u32 wc; int ret; + bool widebus_enabled = msm_dsi_host_is_widebus_enabled(&msm_host->base); DBG(""); @@ -914,6 +929,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) if (msm_host->dsc) { struct drm_dsc_config *dsc = msm_host->dsc; + u32 bytes_per_pclk; /* update dsc params with timing params */ if (!dsc || !mode->hdisplay || !mode->vdisplay) { @@ -937,7 +953,13 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) * pulse width same */ h_total -= hdisplay; - hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3); + if (widebus_enabled && !(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) + bytes_per_pclk = 6; + else + bytes_per_pclk = 3; + + hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), bytes_per_pclk); + h_total += hdisplay; ha_end = ha_start + hdisplay; }