From patchwork Wed Aug 2 18:36:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13338736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C323C04E69 for ; Wed, 2 Aug 2023 18:37:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230146AbjHBShA (ORCPT ); Wed, 2 Aug 2023 14:37:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229632AbjHBShA (ORCPT ); Wed, 2 Aug 2023 14:37:00 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89DD61BD5 for ; Wed, 2 Aug 2023 11:36:58 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2b9f48b6796so1305841fa.3 for ; Wed, 02 Aug 2023 11:36:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691001417; x=1691606217; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=ggtFCyTuEyyo2aD8lzzIhWGX6dKxbHOb8aCo9hV6An8=; b=QLbLEl/uQmxlHR8iVmV6INvv4beTNgF4a7Q4OPRlxfF5U7uhwj1PT+iqvVimR4o44H Ns/gmcd5wo3/G3ElVpDG8PEJqLKqWmtuXwha8NQdxEISeN6cLYLTtP5HsR9uo5tOncID aNrhkhPsfsEHcqB6k0LZ20Fs7kFW2qycblOdkPxEZ7zRW4JIUBK6KpaV9ps/pR+o+lVX S4cmlgHV0885see7Vaxxwb10PacpgSHz77SKVSfEMkNzT6hhYh/rf9Ak6uNd2EQbU5ya tUPl7ghaeHvUTr9JOQiQeKWyp1kaNyX/cnJyPPEvl+RxY7AiW5HtaeXs7Wkw49jSelki +C0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691001417; x=1691606217; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ggtFCyTuEyyo2aD8lzzIhWGX6dKxbHOb8aCo9hV6An8=; b=SeXL9h6lBI23duBywHbkmTa8g6SlG3L2tm2umHv+MpipdQPc8MEjqRssc+YGIprhSw sIwQaPbo2rjDwB8PT1nUDE6uaYTHgOzC3KwfKyqqeUXU81pMCKn+pfsdvJYhZ42mTNp3 R4ClTRLw1h/Im0lbVe6RePmEfhiZYrSqDufXxzyByyQ/CxobSKz8qVL3P/ICWjvCET5y u+7CFBJkKW4OfZcvit6G/wowSutBgSZy4tpaN4eYmA4TUYTNZdcsGvIFlhLVx5fw2sRh KF/cfVzKz3YBH4lRDjUIl/cMQvRnuxRlPuAWx04PzPEwGjq5aypeFOt7XteDucU8PMl3 Lkbg== X-Gm-Message-State: ABy/qLaGzpJcHYy4ier0VwDhDiXnQdbS0P24slWnr5ZZ6DiaFlOpt82C woPwFWnrqt8jmmt4xBZRzv0o7g== X-Google-Smtp-Source: APBJJlGHXsO9Auj7Pm2/sSXEJZtKvS+/HI/5k/EH2ksctqq7fJ1e5OYMMFyIZLfmOoWUjvAVzbV3RA== X-Received: by 2002:a2e:8812:0:b0:2b8:3a1e:eec9 with SMTP id x18-20020a2e8812000000b002b83a1eeec9mr5699192ljh.36.1691001416795; Wed, 02 Aug 2023 11:36:56 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id h5-20020a2e3a05000000b002b94b355527sm3682821lja.32.2023.08.02.11.36.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 11:36:56 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Ryan McCann Subject: [PATCH v2 1/2] drm/msm/dpu: fix DSC 1.2 block lengths Date: Wed, 2 Aug 2023 21:36:54 +0300 Message-Id: <20230802183655.4188640-1-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length. This includes the common block itself, enc subblocks and some empty space around. Change that to pass 0x4 instead, the length of common register block itself. Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets") Reported-by: Ryan McCann Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten --- Changes since v1: - Rebased on top of the catalog changes --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 8 ++++---- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 12 ++++++------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8 ++++---- .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 8 ++++---- 5 files changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index c906b6864b5e..f8d16f9bf528 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -283,22 +283,22 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = { static const struct dpu_dsc_cfg sm8350_dsc[] = { { .name = "dce_0_0", .id = DSC_0, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_0, }, { .name = "dce_0_1", .id = DSC_1, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_1, }, { .name = "dce_1_0", .id = DSC_2, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_0, }, { .name = "dce_1_1", .id = DSC_3, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_1, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 2bf9f34e54c6..3b5061c4402a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -163,7 +163,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { static const struct dpu_dsc_cfg sc7280_dsc[] = { { .name = "dce_0_0", .id = DSC_0, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_0, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index ccd0477f4877..58f5e25679b1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -286,32 +286,32 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = { static const struct dpu_dsc_cfg sc8280xp_dsc[] = { { .name = "dce_0_0", .id = DSC_0, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_0, }, { .name = "dce_0_1", .id = DSC_1, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_1, }, { .name = "dce_1_0", .id = DSC_2, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_0, }, { .name = "dce_1_1", .id = DSC_3, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_1, }, { .name = "dce_2_0", .id = DSC_4, - .base = 0x82000, .len = 0x29c, + .base = 0x82000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_0, }, { .name = "dce_2_1", .id = DSC_5, - .base = 0x82000, .len = 0x29c, + .base = 0x82000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_1, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 2b2e9d4800f8..1b12178dfbca 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -305,22 +305,22 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { static const struct dpu_dsc_cfg sm8450_dsc[] = { { .name = "dce_0_0", .id = DSC_0, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_0, }, { .name = "dce_0_1", .id = DSC_1, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_1, }, { .name = "dce_1_0", .id = DSC_2, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_0, }, { .name = "dce_1_1", .id = DSC_3, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_1, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 833be1167499..f2ab02d04440 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -320,22 +320,22 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { static const struct dpu_dsc_cfg sm8550_dsc[] = { { .name = "dce_0_0", .id = DSC_0, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_0, }, { .name = "dce_0_1", .id = DSC_1, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_1, }, { .name = "dce_1_0", .id = DSC_2, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_0, }, { .name = "dce_1_1", .id = DSC_3, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_1, }, From patchwork Wed Aug 2 18:36:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13338737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E6E8C04A94 for ; Wed, 2 Aug 2023 18:37:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230220AbjHBShC (ORCPT ); Wed, 2 Aug 2023 14:37:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229632AbjHBShB (ORCPT ); Wed, 2 Aug 2023 14:37:01 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21BEE1BD9 for ; Wed, 2 Aug 2023 11:37:00 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2b9b904bb04so1627091fa.1 for ; Wed, 02 Aug 2023 11:37:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691001418; x=1691606218; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WtnOSZ3n2/CymjBqeJkQ4cRZMCsGC/V1KtdFyH5+HU4=; b=HTHt+GQw19CduXQ997U6O6LHXJ0/5ydlTWhAhTfMCTlYn8UnXqmkuvVbBECJ9Laqsi hoX3S9N6rAfx3YvsKvSbt/CrJBJSIJBGE9BkH1lJHPT4l23P3A2TfiNTvE8Y13FFbDjJ r1uIjVZFEHPvpdRBDDXtp63vsW41AclSz0sLyG0u1jpcHvnqzz9Q9wSKAnKu8HMbxlQt NZdjAD2cI/EPL1tBylho/14ohGt+bTfzbKfqoNUZ9cTVk9N1MmCIMy1R/B4ug0+p++b7 H+D3dXei+diDwKjhL0DjID4dlqxbFSSlmeM78ZLPUajz/odI5xz1JIW7oRWq4OuPHLDw 8v0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691001418; x=1691606218; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WtnOSZ3n2/CymjBqeJkQ4cRZMCsGC/V1KtdFyH5+HU4=; b=IYeKoVCtLD3f0sVdIdpdwguHyuT+82aa4BScTPOLRhmD5ZJdRubUOuvRQP7QYSrHCg IJ7AVxqtt/88arEG8XZW3WsPbRUUcGNVIMnf//BaMHw1AVFqtsviV1ZaPH80i5vS2GYH bHMuzOQsEJjVIwD5yIBgR0JQR7sBM18ngq8cNa6lVe/Bxxf5ek+5od1CxsN3QhvY5pOU dlK8+SAsOjNW3W38qOpNM0ipjUbIyxmu0DkwkSo9Mf/uVuRgHiZht96uD6i4lyyvaj5p aagsI7IVPvhzkk8XeGOpf5/L0HK9QKzahUITe1xbSUrzR8YbgxQfXGr4+5WfCwcpSFU2 JjZw== X-Gm-Message-State: ABy/qLYmEBEP1IGCRX04t0lO+RE5RXyITBxlPfjw6jQ2xEulhUTjl90Z gj6TxExN0po7RZNKEhJzXZRebQ== X-Google-Smtp-Source: APBJJlEO9/nyUU2Mk3sSMr7Vvaf2bfj3p1EarkZ97421u+6v1iwV9IAMGoD65g4ZUgZFVJmxj6miyA== X-Received: by 2002:a2e:9bc3:0:b0:2b6:fa60:85a1 with SMTP id w3-20020a2e9bc3000000b002b6fa6085a1mr5960940ljj.21.1691001417728; Wed, 02 Aug 2023 11:36:57 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id h5-20020a2e3a05000000b002b94b355527sm3682821lja.32.2023.08.02.11.36.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 11:36:57 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 2/2] drm/msm/dpu: fix DSC 1.2 enc subblock length Date: Wed, 2 Aug 2023 21:36:55 +0300 Message-Id: <20230802183655.4188640-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802183655.4188640-1-dmitry.baryshkov@linaro.org> References: <20230802183655.4188640-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Both struct dpu_dsc_sub_blks instances declare enc subblock length to be 0x100, while the actual length is 0x9c (last register having offset 0x98). Reduce subblock length to remove the empty register space from being dumped. Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets") Reviewed-by: Abhinav Kumar Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- Changes since v1: - Rebased on top of the catalog changes --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 3ff07d7cbf4b..f1bac5e88249 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -456,12 +456,12 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { * DSC sub blocks config *************************************************************/ static const struct dpu_dsc_sub_blks dsc_sblk_0 = { - .enc = {.name = "enc", .base = 0x100, .len = 0x100}, + .enc = {.name = "enc", .base = 0x100, .len = 0x9c}, .ctl = {.name = "ctl", .base = 0xF00, .len = 0x10}, }; static const struct dpu_dsc_sub_blks dsc_sblk_1 = { - .enc = {.name = "enc", .base = 0x200, .len = 0x100}, + .enc = {.name = "enc", .base = 0x200, .len = 0x9c}, .ctl = {.name = "ctl", .base = 0xF80, .len = 0x10}, };