From patchwork Wed Aug 2 19:31:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naresh Solanki X-Patchwork-Id: 13338771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F51AC04A94 for ; Wed, 2 Aug 2023 19:32:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232452AbjHBTcM (ORCPT ); Wed, 2 Aug 2023 15:32:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229520AbjHBTcM (ORCPT ); Wed, 2 Aug 2023 15:32:12 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83CA41990 for ; Wed, 2 Aug 2023 12:32:09 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-31427ddd3fbso174386f8f.0 for ; Wed, 02 Aug 2023 12:32:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=9elements.com; s=google; t=1691004728; x=1691609528; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=FG/HvA/ZhPB46DVPJ1FluHZ8X/9xTIstvJa8fWyAL7s=; b=aTsL5G7mheOUz7tnXWywhC8ziDCKBSxTb575FaYpQBIM/DZkYwPjCr3TUqQo/D7KjM 681xxo/H2QmzJKKL2zBfZCINoUgHqhhTCuRi/Zn4T2JRCMWoLAJnSSvdCo7qZByXp9S9 ImGdJOfmB2l0dDlVv3aXGZI1ZROQ9TmrkRo/ioe1zJOBuRqKl8cqpwvNQ/ENKNEEptWz X54bIgMBjzQrAdCgDO3MSdlefWZFAzTPfrpqopcUk/fEiQ+AYQ9ka2t+G7h3P+XFqLZT kHE/yTqcMa4lIR1zDqn7JGJc9+G7+ReIXoyDBXgAW9tmPt4ybhXsCOyFsHO/FqOjW65u FWzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691004728; x=1691609528; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=FG/HvA/ZhPB46DVPJ1FluHZ8X/9xTIstvJa8fWyAL7s=; b=eRok2nw3E4vc8Zw7d7mDZ/mXCJDb2CG55qtYwM/bpXJ4qRoVB6MGzzMi+OM6LblkWd 8napGoYDVGx8QHb3fXFHqActJDj+rTlWHFKcIH3vjUuwBIaTv6h0wk1DpN8KiaRm5XCI n8Dn400GzcIGkZ8VcIwHEPRYKRnF4rlgTG2UU2ZRAm6Z2AIN+/QXcGdO/m3/4hiRa+iT zxOq3nrCbR0j0zJP4Zk97fLjMG0ndtU+ze521PTxxW4czZCghrqxcR8bEzKgPkhTXTwN dPBjIl9eTQSI28BWDcAdUNrFbQ+HYoCwMg2Ecr3oGslbQf5YyPhnuqKuUcjPk6fctEq8 Icew== X-Gm-Message-State: ABy/qLbe8P3U1fs3BjhnauR/KDG/SfJ8qCehHnCdsX5qPsfnO3GjoAP3 rwkT6J3I4Ib9yo5ZR6D1JZUdcA== X-Google-Smtp-Source: APBJJlGN4ok5HUHFSRnW8eQTuxLuRrNGvonXPO4jn/9w1U4oLoHipaE8+IUxSA3dfFg2caRnAVArBQ== X-Received: by 2002:a05:6000:152:b0:314:5376:f0d6 with SMTP id r18-20020a056000015200b003145376f0d6mr5372863wrx.52.1691004727865; Wed, 02 Aug 2023 12:32:07 -0700 (PDT) Received: from stroh80.sec.9e.network (ip-078-094-000-051.um19.pools.vodafone-ip.de. [78.94.0.51]) by smtp.gmail.com with ESMTPSA id v18-20020a5d43d2000000b003177074f830sm19666773wrr.59.2023.08.02.12.32.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 12:32:07 -0700 (PDT) From: Naresh Solanki X-Google-Original-From: Naresh Solanki To: Guenter Roeck , Jean Delvare , krzysztof.kozlowski+dt@linaro.org, Rob Herring , Conor Dooley , Naresh Solanki Cc: linux-hwmon@vger.kernel.org, Patrick Rudolph , Naresh Solanki , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/3] dt-bindings: hwmon: Add Infineon TDA38640 Date: Wed, 2 Aug 2023 21:31:51 +0200 Message-ID: <20230802193155.2170935-1-Naresh.Solanki@9elements.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org From: Patrick Rudolph The TDA38640 chip has different output control mechanisms depending on its mode of operation. When the chip is in SVID mode, only hardware-based output control is supported via ENABLE pin. However, when it operates in PMBus mode, software control works perfectly. To enable software control as a workaround in SVID mode, add the DT property 'infineon,en-svid-control'. This property will enable the workaround, which utilizes ENABLE pin polarity flipping for output when the chip is in SVID mode. Signed-off-by: Patrick Rudolph Signed-off-by: Naresh Solanki --- .../hwmon/pmbus/infineon,tda38640.yaml | 51 +++++++++++++++++++ .../devicetree/bindings/trivial-devices.yaml | 2 - 2 files changed, 51 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/hwmon/pmbus/infineon,tda38640.yaml base-commit: cb7022b8976e3c4d12cea2e7bb820a2944e2fd7b diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/infineon,tda38640.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/infineon,tda38640.yaml new file mode 100644 index 000000000000..c5924ddf1b47 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/pmbus/infineon,tda38640.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/hwmon/pmbus/infineon,tda38640.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Infineon TDA38640 Synchronous Buck Regulator with SVID and I2C + +maintainers: + - Naresh Solanki + +description: | + The Infineon TDA38640 is a 40A Single-voltage Synchronous Buck + Regulator with SVID and I2C designed for Industrial use. + + Datasheet: https://www.infineon.com/dgdl/Infineon-TDA38640-0000-DataSheet-v02_04-EN.pdf?fileId=8ac78c8c80027ecd018042f2337f00c9 + +properties: + compatible: + enum: + - infineon,tda38640 + + reg: + maxItems: 1 + + infineon,en-svid-control: + description: | + When enabled, it allows the chip to utilize workaround for + software control of output when operating in SVID mode where + hardware-based output control is the default behavior. + type: boolean + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + tda38640@40 { + compatible = "infineon,tda38640"; + reg = <0x40>; + }; + }; + diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 40bc475ee7e1..86c7d34f63bf 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -151,8 +151,6 @@ properties: - infineon,slb9645tt # Infineon SLB9673 I2C TPM 2.0 - infineon,slb9673 - # Infineon TDA38640 Voltage Regulator - - infineon,tda38640 # Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor - infineon,tlv493d-a1b6 # Infineon Multi-phase Digital VR Controller xdpe11280 From patchwork Wed Aug 2 19:31:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naresh Solanki X-Patchwork-Id: 13338772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBBAAC04E69 for ; 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[78.94.0.51]) by smtp.gmail.com with ESMTPSA id v18-20020a5d43d2000000b003177074f830sm19666773wrr.59.2023.08.02.12.32.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 12:32:08 -0700 (PDT) From: Naresh Solanki X-Google-Original-From: Naresh Solanki To: Guenter Roeck , Jean Delvare , krzysztof.kozlowski+dt@linaro.org Cc: linux-hwmon@vger.kernel.org, Patrick Rudolph , Naresh Solanki , linux-kernel@vger.kernel.org Subject: [PATCH v3 2/3] hwmon: (pmbus) Add ON_OFF_CONFIG register bits Date: Wed, 2 Aug 2023 21:31:52 +0200 Message-ID: <20230802193155.2170935-2-Naresh.Solanki@9elements.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230802193155.2170935-1-Naresh.Solanki@9elements.com> References: <20230802193155.2170935-1-Naresh.Solanki@9elements.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org From: Patrick Rudolph Add bits found in the ON_OFF_CONFIG register. Signed-off-by: Patrick Rudolph Signed-off-by: Naresh Solanki Reviewed-by: Guenter Roeck --- drivers/hwmon/pmbus/pmbus.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/hwmon/pmbus/pmbus.h b/drivers/hwmon/pmbus/pmbus.h index b0832a4c690d..7a28bac7f171 100644 --- a/drivers/hwmon/pmbus/pmbus.h +++ b/drivers/hwmon/pmbus/pmbus.h @@ -243,6 +243,15 @@ enum pmbus_regs { */ #define PB_OPERATION_CONTROL_ON BIT(7) +/* + * ON_OFF_CONFIG + */ +#define PB_ON_OFF_CONFIG_POWERUP_CONTROL BIT(4) +#define PB_ON_OFF_CONFIG_OPERATION_REQ BIT(3) +#define PB_ON_OFF_CONFIG_EN_PIN_REQ BIT(2) +#define PB_ON_OFF_CONFIG_POLARITY_HIGH BIT(1) +#define PB_ON_OFF_CONFIG_TURN_OFF_FAST BIT(0) + /* * WRITE_PROTECT */ From patchwork Wed Aug 2 19:31:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naresh Solanki X-Patchwork-Id: 13338773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7367BC41513 for ; Wed, 2 Aug 2023 19:32:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232396AbjHBTcP (ORCPT ); Wed, 2 Aug 2023 15:32:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229578AbjHBTcN (ORCPT ); Wed, 2 Aug 2023 15:32:13 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8E3926BC for ; Wed, 2 Aug 2023 12:32:11 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3fbc5d5742eso2080965e9.3 for ; Wed, 02 Aug 2023 12:32:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=9elements.com; s=google; t=1691004730; x=1691609530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MYt9Jjxnfumr5xXWagiHEc6kz+KL1UN3g0bRxIEi7bI=; b=BGGslXHtIQBHWYdVYrx5YGuUAjIzVNlro61Kvk419BDSKHCb/aats6mo74h6P/a85f 3SZoZQTqPPTUs4bmq0Sn1hR7U0IVPJwVW9aRGX4hpGbGTTuynmECf06hUGjW1xyGP9Tt sYgT3Re/5bXqVTfTXv/jNwNaPmzsCLVRmI1Dc5p3qOuiAUzq3OxnXKpK9J/N9SxHQJ5E LK6+3RdwGoqa6+nHHEVHVJMmMBR1tkruhIe6vee2Wi668T1S/G4xHrdaDQ1RMjwrUVqR 7PG1bEOjH6IUVDWakcoUMZ25p56W03pwW0adYRzVSLroTyWLpu3UPigHu6DOk5pdy6Rp BWMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691004730; x=1691609530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MYt9Jjxnfumr5xXWagiHEc6kz+KL1UN3g0bRxIEi7bI=; b=MeeHX1RUsZEi6wMJmn1ib3eyG7wCQzTJ5nKVzEy2RIW8TxOQWds2cvZRRJdzY0DRba J9hGulSe3vtSa2ibmSBWJ3x2vCVFtSG4wPtsbwp92/+0Z9FaDmtaP0lQg/CoItuNzffK STlJuHhgwhG63zvGK1H+2R3cer7X8P3SA8kUM7BOXPLF6f2mqyl7cQfV1Nzqb4Iwz8Sc +7GmFdA3ybjebjixGqrikZ7UhAGPYZls6yvPscpBEGjpLmaqx8X+glXGrJqNfXzg84LN J2FupAfXpKd2T/3bodB0MYrBR8VBL2ZCSPsngHvxl/c+Q+WKSTgtrni6kM02Jfms24G4 7kfg== X-Gm-Message-State: ABy/qLaRDb2LtJBfHV+1XMJOLOmkYnsn/mCfjTJmwamiMTL8CjbldygS 97Ku2yd6c+9UNzrVQkfxLw9iFA== X-Google-Smtp-Source: APBJJlEvvBLgMV6oJ6BCOVfbLLmUZBXR9uqzdDEOFn/AV7mIi7vS8jJEIEFjX+kTsYrmGKS16dtpuw== X-Received: by 2002:a7b:c3d2:0:b0:3fb:e054:903f with SMTP id t18-20020a7bc3d2000000b003fbe054903fmr6024825wmj.36.1691004730239; Wed, 02 Aug 2023 12:32:10 -0700 (PDT) Received: from stroh80.sec.9e.network (ip-078-094-000-051.um19.pools.vodafone-ip.de. [78.94.0.51]) by smtp.gmail.com with ESMTPSA id v18-20020a5d43d2000000b003177074f830sm19666773wrr.59.2023.08.02.12.32.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 12:32:09 -0700 (PDT) From: Naresh Solanki X-Google-Original-From: Naresh Solanki To: Guenter Roeck , Jean Delvare , krzysztof.kozlowski+dt@linaro.org Cc: linux-hwmon@vger.kernel.org, Patrick Rudolph , Naresh Solanki , linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] hwmon: (pmbus/tda38640) Add workaround for bug in SVID mode Date: Wed, 2 Aug 2023 21:31:53 +0200 Message-ID: <20230802193155.2170935-3-Naresh.Solanki@9elements.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230802193155.2170935-1-Naresh.Solanki@9elements.com> References: <20230802193155.2170935-1-Naresh.Solanki@9elements.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org From: Patrick Rudolph TDA38640 can operate in either PMBus mode or SVID mode. In SVID mode, by design ENABLE pin is the only option for controlling the output rail. In scenarios that utilizes the chip in SVID mode with ENABLE pin either grounded or tied to logic high & software control is desired then use dt property 'infineon,en-svid-control' to enable the below workaround. The workaround utilizes ENABLE pin polarity flipping to control output rail. If property 'infineon,en-svid-control' is specified then determine if chip is in SVID mode by checking BIT15 of MTP memory offset 0x44 as described in the datasheet. If chip is in SVID mode then apply the workaround by 1. Determine EN pin level 2. Maps BIT7 of OPERATION(01h) to EN_PIN_POLARITY(BIT1) of PB_ON_OFF_CONFIG. Signed-off-by: Patrick Rudolph Signed-off-by: Naresh Solanki ---- Changes in V3: - Use dt property to determine if workaround is needed. Changes in V2: - Remove dependency on DT propery, - Runtime determine SVID mode & ENABLE pin level, - Update commit message. Reviewed-by: Guenter Roeck --- drivers/hwmon/pmbus/tda38640.c | 154 ++++++++++++++++++++++++++++++++- 1 file changed, 152 insertions(+), 2 deletions(-) diff --git a/drivers/hwmon/pmbus/tda38640.c b/drivers/hwmon/pmbus/tda38640.c index 450b0273fb59..d3d987d0d7b6 100644 --- a/drivers/hwmon/pmbus/tda38640.c +++ b/drivers/hwmon/pmbus/tda38640.c @@ -18,6 +18,127 @@ static const struct regulator_desc __maybe_unused tda38640_reg_desc[] = { PMBUS_REGULATOR("vout", 0), }; +struct tda38640_data { + struct pmbus_driver_info info; + u32 en_pin_lvl; +}; + +#define to_tda38640_data(x) container_of(x, struct tda38640_data, info) + +/* + * Map PB_ON_OFF_CONFIG_POLARITY_HIGH to PB_OPERATION_CONTROL_ON. + */ +static int tda38640_read_byte_data(struct i2c_client *client, int page, int reg) +{ + const struct pmbus_driver_info *info = pmbus_get_driver_info(client); + struct tda38640_data *data = to_tda38640_data(info); + int ret, on_off_config, enabled; + + if (reg != PMBUS_OPERATION) + return -ENODATA; + + ret = pmbus_read_byte_data(client, page, reg); + if (ret < 0) + return ret; + + on_off_config = pmbus_read_byte_data(client, page, + PMBUS_ON_OFF_CONFIG); + if (on_off_config < 0) + return on_off_config; + + enabled = !!(on_off_config & PB_ON_OFF_CONFIG_POLARITY_HIGH); + + enabled ^= data->en_pin_lvl; + if (enabled) + ret &= ~PB_OPERATION_CONTROL_ON; + else + ret |= PB_OPERATION_CONTROL_ON; + + return ret; +} + +/* + * Map PB_OPERATION_CONTROL_ON to PB_ON_OFF_CONFIG_POLARITY_HIGH. + */ +static int tda38640_write_byte_data(struct i2c_client *client, int page, + int reg, u8 byte) +{ + const struct pmbus_driver_info *info = pmbus_get_driver_info(client); + struct tda38640_data *data = to_tda38640_data(info); + int enable, ret; + + if (reg != PMBUS_OPERATION) + return -ENODATA; + + enable = !!(byte & PB_OPERATION_CONTROL_ON); + + byte &= ~PB_OPERATION_CONTROL_ON; + ret = pmbus_write_byte_data(client, page, reg, byte); + if (ret < 0) + return ret; + + enable ^= data->en_pin_lvl; + + return pmbus_update_byte_data(client, page, PMBUS_ON_OFF_CONFIG, + PB_ON_OFF_CONFIG_POLARITY_HIGH, + enable ? 0 : PB_ON_OFF_CONFIG_POLARITY_HIGH); +} + +static int svid_mode(struct i2c_client *client, struct tda38640_data *data) +{ + /* PMBUS_MFR_READ(0xD0) + MTP Address offset */ + u8 write_buf[] = {0xd0, 0x44, 0x00}; + u8 read_buf[2]; + int ret, svid; + bool off, reg_en_pin_pol; + + struct i2c_msg msgs[2] = { + { + .addr = client->addr, + .flags = 0, + .buf = write_buf, + .len = sizeof(write_buf), + }, + { + .addr = client->addr, + .flags = I2C_M_RD, + .buf = read_buf, + .len = sizeof(read_buf), + } + }; + + ret = i2c_transfer(client->adapter, msgs, 2); + if (ret < 0) { + dev_err(&client->dev, "i2c_transfer failed. %d", ret); + return ret; + } + + /* + * 0x44[15] determines PMBus Operating Mode + * If bit is set then it is SVID mode. + */ + svid = !!(read_buf[1] & BIT(7)); + + /* + * Determine EN pin level for use in SVID mode. + * This is done with help of STATUS_BYTE bit 6(OFF) & ON_OFF_CONFIG bit 2(EN pin polarity). + */ + if (svid) { + ret = i2c_smbus_read_byte_data(client, PMBUS_STATUS_BYTE); + if (ret < 0) + return ret; + off = !!(ret & PB_STATUS_OFF); + + ret = i2c_smbus_read_byte_data(client, PMBUS_ON_OFF_CONFIG); + if (ret < 0) + return ret; + reg_en_pin_pol = !!(ret & PB_ON_OFF_CONFIG_POLARITY_HIGH); + data->en_pin_lvl = off ^ reg_en_pin_pol; + } + + return svid; +} + static struct pmbus_driver_info tda38640_info = { .pages = 1, .format[PSC_VOLTAGE_IN] = linear, @@ -26,7 +147,6 @@ static struct pmbus_driver_info tda38640_info = { .format[PSC_CURRENT_IN] = linear, .format[PSC_POWER] = linear, .format[PSC_TEMPERATURE] = linear, - .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_STATUS_INPUT | PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP | PMBUS_HAVE_IIN @@ -41,7 +161,37 @@ static struct pmbus_driver_info tda38640_info = { static int tda38640_probe(struct i2c_client *client) { - return pmbus_do_probe(client, &tda38640_info); + struct tda38640_data *data; + int svid; + + data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + memcpy(&data->info, &tda38640_info, sizeof(tda38640_info)); + + if (IS_ENABLED(CONFIG_SENSORS_TDA38640_REGULATOR) && \ + of_property_read_bool(client->dev.of_node, "infineon,en-svid-control")) { + svid = svid_mode(client, data); + if (svid < 0) { + dev_err_probe(&client->dev, svid, "Could not determine operating mode."); + return svid; + } + + /* + * Apply ON_OFF_CONFIG workaround as enabling the regulator using the + * OPERATION register doesn't work in SVID mode. + * + * One should configure PMBUS_ON_OFF_CONFIG here, but + * PB_ON_OFF_CONFIG_POWERUP_CONTROL and PB_ON_OFF_CONFIG_EN_PIN_REQ + * are ignored by the device. + * Only PB_ON_OFF_CONFIG_POLARITY_HIGH has an effect. + */ + if (svid) { + data->info.read_byte_data = tda38640_read_byte_data; + data->info.write_byte_data = tda38640_write_byte_data; + } + } + return pmbus_do_probe(client, &data->info); } static const struct i2c_device_id tda38640_id[] = {