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([187.11.154.63]) by smtp.gmail.com with ESMTPSA id e14-20020a0568301e4e00b006b29a73efb5sm11628otj.7.2023.08.03.07.00.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 07:00:31 -0700 (PDT) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 01/10] RISC-V: KVM: return ENOENT in *_one_reg() when reg is unknown Date: Thu, 3 Aug 2023 11:00:13 -0300 Message-ID: <20230803140022.399333-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803140022.399333-1-dbarboza@ventanamicro.com> References: <20230803140022.399333-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org get_one_reg() and set_one_reg() are returning EINVAL errors for almost everything: if a reg doesn't exist, if a reg ID is malformatted, if the associated CPU extension that implements the reg isn't present in the host, and for set_one_reg() if the value being written is invalid. This isn't wrong according to the existing KVM API docs (EINVAL can be used when there's no such register) but adding more ENOENT instances will make easier for userspace to understand what went wrong. Existing userspaces can be affected by this error code change. We checked a few. As of current upstream code, crosvm doesn't check for any particular errno code when using kvm_(get|set)_one_reg(). Neither does QEMU. rust-vmm doesn't have kvm-riscv support yet. Thus we have a good chance of changing these error codes now while the KVM RISC-V ecosystem is still new, minimizing user impact. Change all get_one_reg() and set_one_reg() implementations to return -ENOENT at all "no such register" cases. Signed-off-by: Daniel Henrique Barboza --- arch/riscv/kvm/aia.c | 4 ++-- arch/riscv/kvm/vcpu_fp.c | 12 ++++++------ arch/riscv/kvm/vcpu_onereg.c | 30 +++++++++++++++--------------- arch/riscv/kvm/vcpu_sbi.c | 16 +++++++++------- arch/riscv/kvm/vcpu_timer.c | 8 ++++---- 5 files changed, 36 insertions(+), 34 deletions(-) diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c index 585a3b42c52c..74bb27440527 100644 --- a/arch/riscv/kvm/aia.c +++ b/arch/riscv/kvm/aia.c @@ -176,7 +176,7 @@ int kvm_riscv_vcpu_aia_get_csr(struct kvm_vcpu *vcpu, struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; if (reg_num >= sizeof(struct kvm_riscv_aia_csr) / sizeof(unsigned long)) - return -EINVAL; + return -ENOENT; *out_val = 0; if (kvm_riscv_aia_available()) @@ -192,7 +192,7 @@ int kvm_riscv_vcpu_aia_set_csr(struct kvm_vcpu *vcpu, struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; if (reg_num >= sizeof(struct kvm_riscv_aia_csr) / sizeof(unsigned long)) - return -EINVAL; + return -ENOENT; if (kvm_riscv_aia_available()) { ((unsigned long *)csr)[reg_num] = val; diff --git a/arch/riscv/kvm/vcpu_fp.c b/arch/riscv/kvm/vcpu_fp.c index 9d8cbc42057a..08ba48a395aa 100644 --- a/arch/riscv/kvm/vcpu_fp.c +++ b/arch/riscv/kvm/vcpu_fp.c @@ -96,7 +96,7 @@ int kvm_riscv_vcpu_get_reg_fp(struct kvm_vcpu *vcpu, reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) reg_val = &cntx->fp.f.f[reg_num]; else - return -EINVAL; + return -ENOENT; } else if ((rtype == KVM_REG_RISCV_FP_D) && riscv_isa_extension_available(vcpu->arch.isa, d)) { if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { @@ -109,9 +109,9 @@ int kvm_riscv_vcpu_get_reg_fp(struct kvm_vcpu *vcpu, return -EINVAL; reg_val = &cntx->fp.d.f[reg_num]; } else - return -EINVAL; + return -ENOENT; } else - return -EINVAL; + return -ENOENT; if (copy_to_user(uaddr, reg_val, KVM_REG_SIZE(reg->id))) return -EFAULT; @@ -141,7 +141,7 @@ int kvm_riscv_vcpu_set_reg_fp(struct kvm_vcpu *vcpu, reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) reg_val = &cntx->fp.f.f[reg_num]; else - return -EINVAL; + return -ENOENT; } else if ((rtype == KVM_REG_RISCV_FP_D) && riscv_isa_extension_available(vcpu->arch.isa, d)) { if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { @@ -154,9 +154,9 @@ int kvm_riscv_vcpu_set_reg_fp(struct kvm_vcpu *vcpu, return -EINVAL; reg_val = &cntx->fp.d.f[reg_num]; } else - return -EINVAL; + return -ENOENT; } else - return -EINVAL; + return -ENOENT; if (copy_from_user(reg_val, uaddr, KVM_REG_SIZE(reg->id))) return -EFAULT; diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 85773e858120..65607f80f8db 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -156,7 +156,7 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu, reg_val = satp_mode >> SATP_MODE_SHIFT; break; default: - return -EINVAL; + return -ENOENT; } if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) @@ -242,7 +242,7 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, return -EINVAL; break; default: - return -EINVAL; + return -ENOENT; } return 0; @@ -262,7 +262,7 @@ static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcpu *vcpu, if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) return -EINVAL; if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long)) - return -EINVAL; + return -ENOENT; if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc)) reg_val = cntx->sepc; @@ -273,7 +273,7 @@ static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcpu *vcpu, reg_val = (cntx->sstatus & SR_SPP) ? KVM_RISCV_MODE_S : KVM_RISCV_MODE_U; else - return -EINVAL; + return -ENOENT; if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) return -EFAULT; @@ -295,7 +295,7 @@ static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcpu *vcpu, if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) return -EINVAL; if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long)) - return -EINVAL; + return -ENOENT; if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) return -EFAULT; @@ -311,7 +311,7 @@ static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcpu *vcpu, else cntx->sstatus &= ~SR_SPP; } else - return -EINVAL; + return -ENOENT; return 0; } @@ -323,7 +323,7 @@ static int kvm_riscv_vcpu_general_get_csr(struct kvm_vcpu *vcpu, struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long)) - return -EINVAL; + return -ENOENT; if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) { kvm_riscv_vcpu_flush_interrupts(vcpu); @@ -342,7 +342,7 @@ static int kvm_riscv_vcpu_general_set_csr(struct kvm_vcpu *vcpu, struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long)) - return -EINVAL; + return -ENOENT; if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) { reg_val &= VSIP_VALID_MASK; @@ -381,7 +381,7 @@ static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu, rc = kvm_riscv_vcpu_aia_get_csr(vcpu, reg_num, ®_val); break; default: - rc = -EINVAL; + rc = -ENOENT; break; } if (rc) @@ -420,7 +420,7 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu, rc = kvm_riscv_vcpu_aia_set_csr(vcpu, reg_num, reg_val); break; default: - rc = -EINVAL; + rc = -ENOENT; break; } if (rc) @@ -437,7 +437,7 @@ static int riscv_vcpu_get_isa_ext_single(struct kvm_vcpu *vcpu, if (reg_num >= KVM_RISCV_ISA_EXT_MAX || reg_num >= ARRAY_SIZE(kvm_isa_ext_arr)) - return -EINVAL; + return -ENOENT; *reg_val = 0; host_isa_ext = kvm_isa_ext_arr[reg_num]; @@ -455,7 +455,7 @@ static int riscv_vcpu_set_isa_ext_single(struct kvm_vcpu *vcpu, if (reg_num >= KVM_RISCV_ISA_EXT_MAX || reg_num >= ARRAY_SIZE(kvm_isa_ext_arr)) - return -EINVAL; + return -ENOENT; host_isa_ext = kvm_isa_ext_arr[reg_num]; if (!__riscv_isa_extension_available(NULL, host_isa_ext)) @@ -554,7 +554,7 @@ static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu, reg_val = ~reg_val; break; default: - rc = -EINVAL; + rc = -ENOENT; } if (rc) return rc; @@ -592,7 +592,7 @@ static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu, case KVM_REG_RISCV_SBI_MULTI_DIS: return riscv_vcpu_set_isa_ext_multi(vcpu, reg_num, reg_val, false); default: - return -EINVAL; + return -ENOENT; } return 0; @@ -659,5 +659,5 @@ int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, break; } - return -EINVAL; + return -ENOENT; } diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 7b46e04fb667..9cd97091c723 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -140,8 +140,10 @@ static int riscv_vcpu_set_sbi_ext_single(struct kvm_vcpu *vcpu, const struct kvm_riscv_sbi_extension_entry *sext = NULL; struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; - if (reg_num >= KVM_RISCV_SBI_EXT_MAX || - (reg_val != 1 && reg_val != 0)) + if (reg_num >= KVM_RISCV_SBI_EXT_MAX) + return -ENOENT; + + if (reg_val != 1 && reg_val != 0) return -EINVAL; for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) { @@ -175,7 +177,7 @@ static int riscv_vcpu_get_sbi_ext_single(struct kvm_vcpu *vcpu, struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; if (reg_num >= KVM_RISCV_SBI_EXT_MAX) - return -EINVAL; + return -ENOENT; for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) { if (sbi_ext[i].ext_idx == reg_num) { @@ -206,7 +208,7 @@ static int riscv_vcpu_set_sbi_ext_multi(struct kvm_vcpu *vcpu, unsigned long i, ext_id; if (reg_num > KVM_REG_RISCV_SBI_MULTI_REG_LAST) - return -EINVAL; + return -ENOENT; for_each_set_bit(i, ®_val, BITS_PER_LONG) { ext_id = i + reg_num * BITS_PER_LONG; @@ -226,7 +228,7 @@ static int riscv_vcpu_get_sbi_ext_multi(struct kvm_vcpu *vcpu, unsigned long i, ext_id, ext_val; if (reg_num > KVM_REG_RISCV_SBI_MULTI_REG_LAST) - return -EINVAL; + return -ENOENT; for (i = 0; i < BITS_PER_LONG; i++) { ext_id = i + reg_num * BITS_PER_LONG; @@ -272,7 +274,7 @@ int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu, case KVM_REG_RISCV_SBI_MULTI_DIS: return riscv_vcpu_set_sbi_ext_multi(vcpu, reg_num, reg_val, false); default: - return -EINVAL; + return -ENOENT; } return 0; @@ -307,7 +309,7 @@ int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu, reg_val = ~reg_val; break; default: - rc = -EINVAL; + rc = -ENOENT; } if (rc) return rc; diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c index 3ac2ff6a65da..527d269cafff 100644 --- a/arch/riscv/kvm/vcpu_timer.c +++ b/arch/riscv/kvm/vcpu_timer.c @@ -170,7 +170,7 @@ int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu, if (KVM_REG_SIZE(reg->id) != sizeof(u64)) return -EINVAL; if (reg_num >= sizeof(struct kvm_riscv_timer) / sizeof(u64)) - return -EINVAL; + return -ENOENT; switch (reg_num) { case KVM_REG_RISCV_TIMER_REG(frequency): @@ -187,7 +187,7 @@ int kvm_riscv_vcpu_get_reg_timer(struct kvm_vcpu *vcpu, KVM_RISCV_TIMER_STATE_OFF; break; default: - return -EINVAL; + return -ENOENT; } if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) @@ -211,7 +211,7 @@ int kvm_riscv_vcpu_set_reg_timer(struct kvm_vcpu *vcpu, if (KVM_REG_SIZE(reg->id) != sizeof(u64)) return -EINVAL; if (reg_num >= sizeof(struct kvm_riscv_timer) / sizeof(u64)) - return -EINVAL; + return -ENOENT; if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) return -EFAULT; @@ -233,7 +233,7 @@ int kvm_riscv_vcpu_set_reg_timer(struct kvm_vcpu *vcpu, ret = kvm_riscv_vcpu_timer_cancel(t); break; default: - ret = -EINVAL; + ret = -ENOENT; break; } From patchwork Thu Aug 3 14:00:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13340100 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1A57EB64DD for ; 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([187.11.154.63]) by smtp.gmail.com with ESMTPSA id e14-20020a0568301e4e00b006b29a73efb5sm11628otj.7.2023.08.03.07.00.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 07:00:34 -0700 (PDT) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 02/10] RISC-V: KVM: use ENOENT in *_one_reg() when extension is unavailable Date: Thu, 3 Aug 2023 11:00:14 -0300 Message-ID: <20230803140022.399333-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803140022.399333-1-dbarboza@ventanamicro.com> References: <20230803140022.399333-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Following a similar logic as the previous patch let's minimize the EINVAL usage in *_one_reg() APIs by using ENOENT when an extension that implements the reg is not available. For consistency we're also replacing an EOPNOTSUPP instance that should be an ENOENT since it's an "extension is not available" error. Signed-off-by: Daniel Henrique Barboza --- arch/riscv/kvm/vcpu_onereg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 65607f80f8db..546f75930d63 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -135,12 +135,12 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu, break; case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) - return -EINVAL; + return -ENOENT; reg_val = riscv_cbom_block_size; break; case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size): if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ)) - return -EINVAL; + return -ENOENT; reg_val = riscv_cboz_block_size; break; case KVM_REG_RISCV_CONFIG_REG(mvendorid): @@ -459,7 +459,7 @@ static int riscv_vcpu_set_isa_ext_single(struct kvm_vcpu *vcpu, host_isa_ext = kvm_isa_ext_arr[reg_num]; if (!__riscv_isa_extension_available(NULL, host_isa_ext)) - return -EOPNOTSUPP; + return -ENOENT; if (!vcpu->arch.ran_atleast_once) { /* From patchwork Thu Aug 3 14:00:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13340102 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28C99C04E69 for ; Thu, 3 Aug 2023 14:01:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236620AbjHCOB2 (ORCPT ); Thu, 3 Aug 2023 10:01:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236542AbjHCOBG (ORCPT ); Thu, 3 Aug 2023 10:01:06 -0400 Received: from mail-ot1-x335.google.com (mail-ot1-x335.google.com [IPv6:2607:f8b0:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7AF9C1981 for ; Thu, 3 Aug 2023 07:00:38 -0700 (PDT) Received: by mail-ot1-x335.google.com with SMTP id 46e09a7af769-6bcc5c86b20so927416a34.3 for ; Thu, 03 Aug 2023 07:00:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691071238; x=1691676038; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FfxDwps7lgF17ypk0wnS9BfXgR1hQYuTelZWUrO/6tw=; b=CMqqPGLsMMuaZEUTphocqW4yFgSoZOpFqaDfOJpm5Rug/qGE9nn49ubd9rzwGFSkYy gQUOqVylXWKM/wTTBU8nWcEHm3tuePXEChxVDioVSXD6CJ2rw3z0aEehDSfzXZ+gBX34 yrO8a/MPZztz43ooGbfxP15GnXMDOCZKYKm6mCz55w1JGXGI9fAY/GO4ynGqjvHLC7vg VW/5fP/O+PQuhuSGS42oR/3+eXmK+PtqPtt2VySOYmoEjtW5KTuwpdJPTWr6/AwvmnBU MgZ7I0ojWWcuyr4IJ/AJdYFvTeo3cwAlmSsCB5iumEtSoFaYOYFmEPyaAV6/O35EVbNH kw9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691071238; x=1691676038; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FfxDwps7lgF17ypk0wnS9BfXgR1hQYuTelZWUrO/6tw=; b=i+ycoUf0elrDwpaaWkfCZG+cbydgzgmMHEapimCOteqcJtv97pwsPktOxiK/QaCKeb mVeHNiTlCxFpZJJQFXKpz2f4osIYo5EIrcDDX3vPRilGFZJISX8eP/eXhmmYDNOFp5Xy R3Jlv9nkPXe5i78mvXpfGsChjDrvSV636usfqmhZMFckO8BTYMsib1fB7zrVcl7r5kwo rI99BlBtPt+WRQ5nRcxtzNF6I2OGBvU5C4o226/O+GSu5mz2ZdFxZ68zbkXVfY03KXx2 73yyx3l63HM5C4anr6uA4g6DMVFb/HMpVLhn6tcABqjpTNSLsmGnHVztO9kpNKhHv24d Rfgw== X-Gm-Message-State: ABy/qLZuD0obRmOleND6uYGIALbeR9fcHeY5w8WQdZ5BUDkGKEPqAbkT IDvoCelB2amUgIVeHSYpXZs4JrNRV74VdQqg7ZKPsw== X-Google-Smtp-Source: APBJJlH4xxE7xbhXT7gfioaufiAVlVy9fF4cSW5XrzYXhlLE8iZBPjWLQ97nKoSQ2HQL6LkEmEzfrw== X-Received: by 2002:a05:6870:ac0d:b0:1b3:eec8:fa90 with SMTP id kw13-20020a056870ac0d00b001b3eec8fa90mr25825081oab.6.1691071237839; Thu, 03 Aug 2023 07:00:37 -0700 (PDT) Received: from grind.. ([187.11.154.63]) by smtp.gmail.com with ESMTPSA id e14-20020a0568301e4e00b006b29a73efb5sm11628otj.7.2023.08.03.07.00.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 07:00:37 -0700 (PDT) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 03/10] RISC-V: KVM: do not EOPNOTSUPP in set_one_reg() zicbo(m|z) Date: Thu, 3 Aug 2023 11:00:15 -0300 Message-ID: <20230803140022.399333-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803140022.399333-1-dbarboza@ventanamicro.com> References: <20230803140022.399333-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org zicbom_block_size and zicboz_block_size have a peculiar API: they can be read via get_one_reg() but any write will return a EOPNOTSUPP. It makes sense to return a 'not supported' error since both values can't be changed, but as far as userspace goes they're regs that are throwing the same EOPNOTSUPP error even if they were read beforehand via get_one_reg(), even if the same read value is being written back. EOPNOTSUPP is also returned even if ZICBOM/ZICBOZ aren't enabled in the host. Change both to work more like their counterparts in get_one_reg() and return -ENOENT if their respective extensions aren't available. After that, check if the userspace is written a valid value (i.e. the host value). Throw an -EINVAL if that's not case, let it slide otherwise. This allows both regs to be read/written by userspace in a 'lazy' manner, as long as the userspace doesn't change the reg vals. Suggested-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza --- arch/riscv/kvm/vcpu_onereg.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 546f75930d63..49d5676928e4 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -216,9 +216,17 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, } break; case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): - return -EOPNOTSUPP; + if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) + return -ENOENT; + if (reg_val != riscv_cbom_block_size) + return -EINVAL; + break; case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size): - return -EOPNOTSUPP; + if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ)) + return -ENOENT; + if (reg_val != riscv_cboz_block_size) + return -EINVAL; + break; case KVM_REG_RISCV_CONFIG_REG(mvendorid): if (!vcpu->arch.ran_atleast_once) vcpu->arch.mvendorid = reg_val; From patchwork Thu Aug 3 14:00:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13340104 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F44BEB64DD for ; Thu, 3 Aug 2023 14:01:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236556AbjHCOBk (ORCPT ); Thu, 3 Aug 2023 10:01:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236495AbjHCOBV (ORCPT ); Thu, 3 Aug 2023 10:01:21 -0400 Received: from mail-oi1-x234.google.com (mail-oi1-x234.google.com [IPv6:2607:f8b0:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A569A1FED for ; Thu, 3 Aug 2023 07:00:42 -0700 (PDT) Received: by mail-oi1-x234.google.com with SMTP id 5614622812f47-3a74d759bfcso754823b6e.1 for ; Thu, 03 Aug 2023 07:00:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691071241; x=1691676041; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fgDQfKgZT9Ai5Y6MxDXe+dFoAViK+yC0G5UtB2DQuPI=; b=VkKL4SWpN8H1S05U44mEkQoz7D8we329L1z3V6OpzGmXL1JOMTWJV7E6MIvheGbmbu O3TT6cc8d89JSEl8/0y+hznZ2P6tP+P1yWupO4nBDfe3Q+FWN3uj7OwowwOiClEj7ZuA kFbJ5TEcNngQKU+P1pRhEyv3kE8YYUaPYYmVOSySImOEXEx9lNpTLYGZX8sGMs9LCsv1 b/LjWUsKKqdGBdWFeSJncHoi/JqicC0TBqqO765/0PYMyCDUhND/b9Wxm36UtNh1Yonr 2Zu24pcCNb9kmPJY7xGNO6KB+977IRc6w+6KnpsMHJXUL45sL1Ju6s8Pkk0XVczXIbmf 5Blg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691071241; x=1691676041; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fgDQfKgZT9Ai5Y6MxDXe+dFoAViK+yC0G5UtB2DQuPI=; b=k51R42FuJPD2OFlhza1KLdqYiT+MnlM6/8FgzXwGujvA/yfCjBfzRYxh+DGDvOYPCR YKA5ol1hWJdmiR3Ou/+QG4G+n6MXsT4YAyI+HermDYhvCfaKy0qyHd6tYWNC73iSgkbP KYqUpK8yP37Lp+2XJERHeo5AegQIHpFaua9CQGH8CxP6/1YQ278923p/HtmcuWXgQOhN oKs8HpLn2fLyP11rfnqo7IlErGUQPz5b7sgc0bPdF/cxwLCZ7LKrD+CYy5r0whyZQIOP iroqgapm4XwWrTbDF2zKWq2uaT96wQDsEd/AEdZglYhNHDVtUgcKnctI9UDuKh6VSxIx 6Iog== X-Gm-Message-State: ABy/qLbtPdDTp0hK3vaU8i/TtyvEyF+wwnPXLrP6gqbycWOYVZsflF2t 458OMGWWbyt+lE1uMt7T/VFLaQ== X-Google-Smtp-Source: APBJJlFd2x74atNXWpMe8rkpTEAS1KERwXNHpEJ0ZOg6dDJ2zjyuV432rhbjey0HbZ+Rghnf3NT3UA== X-Received: by 2002:a05:6870:d251:b0:1ba:66c1:da53 with SMTP id h17-20020a056870d25100b001ba66c1da53mr20590605oac.22.1691071240842; Thu, 03 Aug 2023 07:00:40 -0700 (PDT) Received: from grind.. ([187.11.154.63]) by smtp.gmail.com with ESMTPSA id e14-20020a0568301e4e00b006b29a73efb5sm11628otj.7.2023.08.03.07.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 07:00:40 -0700 (PDT) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 04/10] RISC-V: KVM: do not EOPNOTSUPP in set KVM_REG_RISCV_TIMER_REG Date: Thu, 3 Aug 2023 11:00:16 -0300 Message-ID: <20230803140022.399333-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803140022.399333-1-dbarboza@ventanamicro.com> References: <20230803140022.399333-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The KVM_REG_RISCV_TIMER_REG can be read via get_one_reg(). But trying to write anything in this reg via set_one_reg() results in an EOPNOTSUPP. Change the API to behave like cbom_block_size: instead of always erroring out with EOPNOTSUPP, allow userspace to write the same value (riscv_timebase) back, throwing an EINVAL if a different value is attempted. Signed-off-by: Daniel Henrique Barboza --- arch/riscv/kvm/vcpu_timer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c index 527d269cafff..75486b25ac45 100644 --- a/arch/riscv/kvm/vcpu_timer.c +++ b/arch/riscv/kvm/vcpu_timer.c @@ -218,7 +218,8 @@ int kvm_riscv_vcpu_set_reg_timer(struct kvm_vcpu *vcpu, switch (reg_num) { case KVM_REG_RISCV_TIMER_REG(frequency): - ret = -EOPNOTSUPP; + if (reg_val != riscv_timebase) + return -EINVAL; break; case KVM_REG_RISCV_TIMER_REG(time): gt->time_delta = reg_val - get_cycles64(); From patchwork Thu Aug 3 14:00:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13340103 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38378EB64DD for ; Thu, 3 Aug 2023 14:01:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236640AbjHCOBe (ORCPT ); Thu, 3 Aug 2023 10:01:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236461AbjHCOBW (ORCPT ); Thu, 3 Aug 2023 10:01:22 -0400 Received: from mail-ot1-x32a.google.com (mail-ot1-x32a.google.com [IPv6:2607:f8b0:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D561730F4 for ; Thu, 3 Aug 2023 07:00:44 -0700 (PDT) Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6bca7d82d54so897109a34.3 for ; Thu, 03 Aug 2023 07:00:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691071244; x=1691676044; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2tfXSWeWMPnAaIHY4KST0Dq87HeMn2MCQyiwOTRx9l0=; b=WP69lFjTPQZBrSl5wkrXyzdHsTpyXA2gQa0IRM5fKF/BiJJslBNKpmj/AOs0VzIEi1 230pC7w5MsZjzMNcQDLIxq8zqZjOWkA9IEz3/H0hwfTng5PnlMtVA9PGgn6q5AcL8Zmr 8hfkfw+x1vAS4NMP9lydmjgAewKG1iEXAiqWEf5AgOX9bdfy7KwBL+69QaZx11BOJqma yK6zfiBC4u0RvubTUeaNRhRXRujYEkUPQgKplcaur9kFc6JnKukD75uePnfQWwa+Uxiz WRJWWUXaqG8pv2b7Kit6dPWbwG+UbC6UlEYD3cgz1VR8q4S/7D4IN0T+eu/hu6exODeS MM0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691071244; x=1691676044; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2tfXSWeWMPnAaIHY4KST0Dq87HeMn2MCQyiwOTRx9l0=; b=li33JqxsNssxC9EPFygFwQfEf06Yh8XS9S/vqmRz+YWhFVKb5i4yg853uh/4vtnv4R MsWELPfOqhxYsOi+mgtw7S5gtjKSOH+nLfl8FjTCeYaIyz6Ualx8BdLku1EVKuKFdLPo A0DpsA0eK0TOiG/+XstP6i1YAaAW9lO3+8+oQcFsCWKWbxowisV6PwXeZix0YtsKS9p4 NbHvmu2YhiuntYoHFpDoEtmtT8O35Y96CiDhFkl0CrlcD+vMvzSOEReIic5LVS2UQMc8 5meoeJl30fphFFJSU+UZMhP36XaOfL+WhmhIAJe/Uirnh8wrmVWY1hjmjRvni3NMRfgC Gs+g== X-Gm-Message-State: ABy/qLYTLkRgaN9Xux/2ot3Y7g2cdPw18i7Rh1cNo0WkA+qcSvO3dlKR e4oLqVLk3TK9NLik2dcUmts1f10QyMdCe8w4gr6row== X-Google-Smtp-Source: APBJJlG7X8lZjATw94mHRd/2WLRlARX3gMV99Gf7BdNQxmyPF9slcJQDy0JY5lo4gAQ1GC8RuAzNfw== X-Received: by 2002:a05:6870:2198:b0:1b7:3432:9ec4 with SMTP id l24-20020a056870219800b001b734329ec4mr23759556oae.10.1691071243905; Thu, 03 Aug 2023 07:00:43 -0700 (PDT) Received: from grind.. ([187.11.154.63]) by smtp.gmail.com with ESMTPSA id e14-20020a0568301e4e00b006b29a73efb5sm11628otj.7.2023.08.03.07.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 07:00:43 -0700 (PDT) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 05/10] RISC-V: KVM: use EBUSY when !vcpu->arch.ran_atleast_once Date: Thu, 3 Aug 2023 11:00:17 -0300 Message-ID: <20230803140022.399333-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803140022.399333-1-dbarboza@ventanamicro.com> References: <20230803140022.399333-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org vcpu_set_reg_config() and vcpu_set_reg_isa_ext() is throwing an EOPNOTSUPP error when !vcpu->arch.ran_atleast_once. In similar cases we're throwing an EBUSY error, like in mvendorid/marchid/mimpid set_reg(). EOPNOTSUPP has a conotation of finality. EBUSY is more adequate in this case since its a condition/error related to the vcpu lifecycle. Change these EOPNOTSUPP instances to EBUSY. Suggested-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza --- arch/riscv/kvm/vcpu_onereg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 49d5676928e4..0cf25c18b582 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -212,7 +212,7 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, vcpu->arch.isa[0] = reg_val; kvm_riscv_vcpu_fp_reset(vcpu); } else { - return -EOPNOTSUPP; + return -EBUSY; } break; case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): @@ -484,7 +484,7 @@ static int riscv_vcpu_set_isa_ext_single(struct kvm_vcpu *vcpu, return -EINVAL; kvm_riscv_vcpu_fp_reset(vcpu); } else { - return -EOPNOTSUPP; + return -EBUSY; } return 0; From patchwork Thu Aug 3 14:00:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13340105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A993EEB64DD for ; Thu, 3 Aug 2023 14:02:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236654AbjHCOCR (ORCPT ); Thu, 3 Aug 2023 10:02:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236533AbjHCOBY (ORCPT ); Thu, 3 Aug 2023 10:01:24 -0400 Received: from mail-ot1-x32f.google.com (mail-ot1-x32f.google.com [IPv6:2607:f8b0:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 760913ABC for ; Thu, 3 Aug 2023 07:00:48 -0700 (PDT) Received: by mail-ot1-x32f.google.com with SMTP id 46e09a7af769-6bcb15aa074so710134a34.0 for ; Thu, 03 Aug 2023 07:00:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691071247; x=1691676047; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yMgdqxcdnDQl98YLRV0LQz8Q38GTfP1yqCfHWC0ZO9E=; b=OCubc2jtAM5saxSdv7vwSmoa0U1OQXP79Jz28sjbUAmAnzUFCYIwjnly6PT+H9qfel ds3DMFmheazZErFepvPTe3pKElknJ08jUJruuQrxei/F9g7B2xjN4SCVaXUBVy3Qipup lHO167bvB/GQJUgwCb8SY1P4IdoSNPsrMR6oyQpHIaW0IrpbNfe8XACcOIFszH07GDPW TfHUGOAZtE4N9hSF5q0qNHZBpKct3f7cBxaZ/H/rGGD1oIyFnPSIfeMv75OeNO1JFyMw IRVZZhYrrWJK15ZfFLGCjdmj0HdA1qPHcwzYBw5I+p5HuKmN7ZQ2k7qdC7O8Wm1N5cfw Rz1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691071247; x=1691676047; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yMgdqxcdnDQl98YLRV0LQz8Q38GTfP1yqCfHWC0ZO9E=; b=KqbBjIq3MzdRCwOLY2Tyu/0OC7lkD8oBCgDNBwiChFxcdH0dIIXw8qcptkNDPfymLr sdcPaVfQQw0FgS5n/SIX45l9vRisbiq+GligVpF471hFq98hH9mdR5qxYeaDvc90tI3K UOMHS0yiIPvLg/ktbTbvXSe98SgAxJnQxXEnoQi+H7Rh7ATjZVl2zmj4cp4WhoWeh7oX eP2mHzEoHm5EIGFfIBeZLtYSeRCf+xSr7xCGTmweUO+DwGvz3eXPpondLeSou9+PJtsZ OIldVAx5NZoyog1RdtglcFyFUpR3SLibKLRDMIMNiG8MCz2Ifu4NzAzURUSOjNVfzU+Y uMvg== X-Gm-Message-State: ABy/qLbHzbcDjsMZpWHgXc5RUTk8uQkKLRJO/UYeADCAwVcCqv2vKT9S dwIcPoDbLynw6Hux75Fv5wJn/HfTXzcwefIPSsX/Eg== X-Google-Smtp-Source: APBJJlEcDRgMfvC3IQOWIDRGvND2vw9Hl/YKtkj7BedFr1ziA1rcBuyU5M2yaJHjMLmruPyJIQMDLQ== X-Received: by 2002:a05:6830:831:b0:6b8:6bd1:d0d3 with SMTP id t17-20020a056830083100b006b86bd1d0d3mr18175614ots.5.1691071246747; Thu, 03 Aug 2023 07:00:46 -0700 (PDT) Received: from grind.. ([187.11.154.63]) by smtp.gmail.com with ESMTPSA id e14-20020a0568301e4e00b006b29a73efb5sm11628otj.7.2023.08.03.07.00.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 07:00:46 -0700 (PDT) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 06/10] RISC-V: KVM: avoid EBUSY when writing same ISA val Date: Thu, 3 Aug 2023 11:00:18 -0300 Message-ID: <20230803140022.399333-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803140022.399333-1-dbarboza@ventanamicro.com> References: <20230803140022.399333-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org kvm_riscv_vcpu_set_reg_config() will return -EBUSY if the ISA config reg is being written after the VCPU ran at least once. The same restriction isn't placed in kvm_riscv_vcpu_get_reg_config(), so there's a chance that we'll -EBUSY out on an ISA config reg write even if the userspace intended no changes to it. We'll allow the same form of 'lazy writing' that registers such as zicbom/zicboz_block_size supports: avoid erroring out if userspace made no changes to the ISA config reg. Signed-off-by: Daniel Henrique Barboza --- arch/riscv/kvm/vcpu_onereg.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 0cf25c18b582..e752e2dca8ed 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -190,6 +190,13 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, if (fls(reg_val) >= RISCV_ISA_EXT_BASE) return -EINVAL; + /* + * Return early (i.e. do nothing) if reg_val is the same + * value retrievable via kvm_riscv_vcpu_get_reg_config(). + */ + if (reg_val == (vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK)) + break; + if (!vcpu->arch.ran_atleast_once) { /* Ignore the enable/disable request for certain extensions */ for (i = 0; i < RISCV_ISA_EXT_BASE; i++) { From patchwork Thu Aug 3 14:00:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13340140 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18C45EB64DD for ; Thu, 3 Aug 2023 14:02:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236610AbjHCOCX (ORCPT ); Thu, 3 Aug 2023 10:02:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236424AbjHCOB0 (ORCPT ); Thu, 3 Aug 2023 10:01:26 -0400 Received: from mail-ot1-x332.google.com (mail-ot1-x332.google.com [IPv6:2607:f8b0:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D60AE4224 for ; Thu, 3 Aug 2023 07:00:53 -0700 (PDT) Received: by mail-ot1-x332.google.com with SMTP id 46e09a7af769-6bcb15aa074so710181a34.0 for ; Thu, 03 Aug 2023 07:00:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691071250; x=1691676050; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e0/jj8XZe2G0/16QSZpeAFh+25Re5O97IU/+Y05CM7U=; b=TMj2mDCqaHn1I7iRa95PfoZqVLDu/uigTDCqaamPwaAEITunT4atuoTgcUVlgBPnRw r9t77Nd1b81S5uWJ2kTsuaAKAZzGaDh3aQhlysDm3e0smm74UJk7QqrGyKlHgolWQ1oV BYTvJZWl3coXumhKXwtQCBRKooFyE83LZLiX//OaK/MO+9qMKtAitngfpAKeg8sHCatd FnzumKuNswefhxaXUjYJdke2RFBYXqpDcyicniWDFkFcx8vsBTuROU4lZYSlvhS9QyWf +rknPZGQ23JeiHt4vjxadRmvReQ8JARfNQ/8FKj3cy5Z1CFzxuegd967m0jIQ8Eia0qn cHCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691071250; x=1691676050; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e0/jj8XZe2G0/16QSZpeAFh+25Re5O97IU/+Y05CM7U=; b=Q5UVK8dgqGxNWrk0LT/BrDCUybIYpoYz9mNZmp5iXaxUbBGkA1fKIUm1RgH29KXYg/ W8TOlBbM8fWprSdcH8ddjbQZGYcwdnFUu+3R9ADaMDPoVnln/2B2by101dZb0bFdkZmt 3/7dURPuGu8OjKSce62FIYXUEwRDF014UYAZPdZzbbg2Sz/IA3mJ4t3tq6dlMF1q3JKX Id9CuBrz9SbLDJeptWQ4TRLul5NDTilLaj7UOlu7dKL2Hwl2W5w6dDbunA9iGTO3ZZch lpaKr5ep8iByJo8h5cNBmcWtZEcSxB7WZphvv2QluL1NaMyBCHmSHGVQwtxoPMuD5eDD kxow== X-Gm-Message-State: ABy/qLbBPeV8nFf2YqiJWbOQwB0BtkhQC+vr+XfR+UzaWhuax8o+hx+C dSiDT0zt7QIg7UVzRxMFmhxDVA== X-Google-Smtp-Source: APBJJlFN0Rk5STEm5jArdHCeyZjSMbEocsbopm5itxXndoi1sdc8VNe6PTE/U5cndrjgITYvO07ytA== X-Received: by 2002:a9d:4f1a:0:b0:6bc:b06c:9277 with SMTP id d26-20020a9d4f1a000000b006bcb06c9277mr6918980otl.7.1691071250017; Thu, 03 Aug 2023 07:00:50 -0700 (PDT) Received: from grind.. ([187.11.154.63]) by smtp.gmail.com with ESMTPSA id e14-20020a0568301e4e00b006b29a73efb5sm11628otj.7.2023.08.03.07.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 07:00:49 -0700 (PDT) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 07/10] RISC-V: KVM: avoid EBUSY when writing the same machine ID val Date: Thu, 3 Aug 2023 11:00:19 -0300 Message-ID: <20230803140022.399333-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803140022.399333-1-dbarboza@ventanamicro.com> References: <20230803140022.399333-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Right now we do not allow any write in mvendorid/marchid/mimpid if the vcpu already started, preventing these regs to be changed. However, if userspace doesn't change them, an alternative is to consider the reg write a no-op and avoid erroring out altogether. Userpace can then be oblivious about KVM internals if no changes were intended in the first place. Allow the same form of 'lazy writing' that registers such as zicbom/zicboz_block_size supports: avoid erroring out if userspace makes no changes in mvendorid/marchid/mimpid during reg write. Signed-off-by: Daniel Henrique Barboza --- arch/riscv/kvm/vcpu_onereg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index e752e2dca8ed..818900f30859 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -235,18 +235,24 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, return -EINVAL; break; case KVM_REG_RISCV_CONFIG_REG(mvendorid): + if (reg_val == vcpu->arch.mvendorid) + break; if (!vcpu->arch.ran_atleast_once) vcpu->arch.mvendorid = reg_val; else return -EBUSY; break; case KVM_REG_RISCV_CONFIG_REG(marchid): + if (reg_val == vcpu->arch.marchid) + break; if (!vcpu->arch.ran_atleast_once) vcpu->arch.marchid = reg_val; else return -EBUSY; break; case KVM_REG_RISCV_CONFIG_REG(mimpid): + if (reg_val == vcpu->arch.mimpid) + break; if (!vcpu->arch.ran_atleast_once) vcpu->arch.mimpid = reg_val; else From patchwork Thu Aug 3 14:00:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13340141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9CFEC04A94 for ; Thu, 3 Aug 2023 14:02:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236672AbjHCOCe (ORCPT ); Thu, 3 Aug 2023 10:02:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236559AbjHCOB3 (ORCPT ); Thu, 3 Aug 2023 10:01:29 -0400 Received: from mail-ot1-x333.google.com (mail-ot1-x333.google.com [IPv6:2607:f8b0:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3B15211F for ; Thu, 3 Aug 2023 07:00:57 -0700 (PDT) Received: by mail-ot1-x333.google.com with SMTP id 46e09a7af769-6b9e478e122so871590a34.1 for ; Thu, 03 Aug 2023 07:00:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691071253; x=1691676053; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4UgQi9LDUX4k3lR2Q2FdA6BSSL1gShj19us97XhXguU=; b=ICE7tPcGWwrSBFFCkEwRFCKGrJiitZ33RQSEP5SXsq0rz8HNeps+M1nXALn5mGkx3l /UY9H1rMQnfL7Oc5HKzi3UzSHuecUctTdD/ZSj+yVL5Kk/zozy8v7AXHFDe788wB2tUz py0+oElvUGjWFK3eTk35tQ/Vb2cyINuCsbUhFPEzNNKZ8QQXuSnljxngNwzPqc3rNBy/ udiBb7jEkf3cFj8/N7LPZ1G0huwxtfAazsq2f/PbTJmRNbtPhK61Z/iygXBpthX7idAu aHj2l//XFR59okmzmOZDQxvhJZK6aa4HjH/kS5AYfOfT+SSoMJi+9Hs9vUynsJ8dXjuf JGzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691071253; x=1691676053; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4UgQi9LDUX4k3lR2Q2FdA6BSSL1gShj19us97XhXguU=; b=AlsT0vFW91GmR1RqBy9zLDwfZ8sH8xSc8JA83kKoZP0WDgbZuazFwICvTLMr/CJlSL P4YA+2BNstX7tltfn5vQscSOvXkHOXGSaAuii1dJfBzXHgGq2NnGcMcPvHaZ0jfccjfI 90Y/HGjBvg+M+miJEzU8njIgO/a1nehvzdVX5+6t/zkNrKq9Qxvolr8538hToAR4xErN C9Ev5VjVVib56SWT0+b5egjJiap15FcRopGSojztw6KVoBYIGALDdaiMwKRen/8s6obU F/mX/eRyH7Rpklj3DXd68ztHdINw4QXXF/ZEZA1WN4KOb1rR3TS3PnLIdavFKgCUdJmj Viug== X-Gm-Message-State: ABy/qLay8Wj6k8Ldm+gVXS6FqWiwk3iOZqxOXpmx0b/H0c3XALm0noVJ 7RwqboW0BbKKDxnPZNzwf7W5rQ== X-Google-Smtp-Source: APBJJlEJ7XVge9+sqybuLluuJAUuShjWkmg3bWllK2pZ8dTvF2tT43lRWqnDUx8VRtN4MazF30GSvA== X-Received: by 2002:a05:6830:12c1:b0:6b8:6a83:2b17 with SMTP id a1-20020a05683012c100b006b86a832b17mr18904714otq.33.1691071253133; Thu, 03 Aug 2023 07:00:53 -0700 (PDT) Received: from grind.. ([187.11.154.63]) by smtp.gmail.com with ESMTPSA id e14-20020a0568301e4e00b006b29a73efb5sm11628otj.7.2023.08.03.07.00.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 07:00:52 -0700 (PDT) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 08/10] RISC-V: KVM: avoid EBUSY when writing the same isa_ext val Date: Thu, 3 Aug 2023 11:00:20 -0300 Message-ID: <20230803140022.399333-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803140022.399333-1-dbarboza@ventanamicro.com> References: <20230803140022.399333-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org riscv_vcpu_set_isa_ext_single() will prevent any write of isa_ext regs if the vcpu already started spinning. But if there's no extension state (enabled/disabled) made by the userspace, there's no need to -EBUSY out - we can treat the operation as a no-op. zicbom/zicboz_block_size, ISA config reg and mvendorid/march/mimpid already works in a more permissive manner w.r.t userspace writes being a no-op, so let's do the same with isa_ext writes. Signed-off-by: Daniel Henrique Barboza --- arch/riscv/kvm/vcpu_onereg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 818900f30859..fcfe2049effd 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -482,6 +482,9 @@ static int riscv_vcpu_set_isa_ext_single(struct kvm_vcpu *vcpu, if (!__riscv_isa_extension_available(NULL, host_isa_ext)) return -ENOENT; + if (reg_val == test_bit(host_isa_ext, vcpu->arch.isa)) + return 0; + if (!vcpu->arch.ran_atleast_once) { /* * All multi-letter extension and a few single letter From patchwork Thu Aug 3 14:00:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13340142 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCE80C04FE0 for ; Thu, 3 Aug 2023 14:02:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236531AbjHCOCj (ORCPT ); Thu, 3 Aug 2023 10:02:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235222AbjHCOCD (ORCPT ); Thu, 3 Aug 2023 10:02:03 -0400 Received: from mail-ot1-x32a.google.com (mail-ot1-x32a.google.com [IPv6:2607:f8b0:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F70944BD for ; Thu, 3 Aug 2023 07:01:01 -0700 (PDT) Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6bc9254a1baso901301a34.2 for ; Thu, 03 Aug 2023 07:01:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691071256; x=1691676056; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EkwDk8dXju8I9w7KpYFAws21Qd1+OBzn/0afxgdVQLI=; b=XW9PuJZm7znGzIG6HfPZZ/EGSS3Y+yBOiKzv2jqmphbRIf/VN2MPDFnaWNAm+VOGQP 34QUrUiKUm4OkSD1al24yYdOf6sjR3/rCgLKIETf0kA2njYbv/lZDER/JT8cSlv6+na2 aeTQfyDIjwwuX6RVsOiwhNVWY/uXkOLSHKP/UcIpeGGm5fohk16zPrWhL9FJiF16gKdc arFNZ5mDy52or5a3sBPZk8uMlAONYl/76yjBviZeEeRH8NVWytAEia2yJkI7REmXODFv QoUR1W9PhYUPdMM0u6yp3qAgn7LIAZuHkPSdefAC+ihmm+tyt2eb34SnZEUSmwgl60eT gvfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691071256; x=1691676056; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EkwDk8dXju8I9w7KpYFAws21Qd1+OBzn/0afxgdVQLI=; b=JfiKWpDmoW6OsPgM1sWoFRoW5j2KuseFL+bJbXuX2hM2bo70Nuc7t4PB0C9e4Gq+98 XDgPpvwUv9VvJvQMQ9R02nBPtFXFKvUy2jObR8rDzMmcvIZyQaMv5e+ibjhZm5A00YUf 8AkA98N0PBBD+OvtXU0buP+dA6agEdJl+N0FVInuGMWFczsVTwEpdWcfZg4irbljAI/j uKPJaGRcZMhAowF1f5JYofaO6KWuChOSKM7jamI0p/vuKVnOJ8nAvVoAWhqC3nif9fBt 2YH245Y3cWwo81UxCu9QMBQ+tkhoEPGgC5P3HF8aTbp2QV887YyI+WGDHS5w8dVdn1m1 1cJw== X-Gm-Message-State: ABy/qLZcG8WJbZFpKhTC19qiSeU6pirJlVBqzT5f6THMqdU/nMAOvBr4 htAXRSZq5BibWSyIHIrG13EgCA== X-Google-Smtp-Source: APBJJlGZdJ8RVR9JidGuJDXr3yfjorlKS5cjnZTx47GbtEuo0utyyEwhjsgOyM7aj9j2Hz8lFiOMMA== X-Received: by 2002:a9d:4e89:0:b0:6bc:8cd2:dd9c with SMTP id v9-20020a9d4e89000000b006bc8cd2dd9cmr17883841otk.36.1691071256311; Thu, 03 Aug 2023 07:00:56 -0700 (PDT) Received: from grind.. ([187.11.154.63]) by smtp.gmail.com with ESMTPSA id e14-20020a0568301e4e00b006b29a73efb5sm11628otj.7.2023.08.03.07.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 07:00:55 -0700 (PDT) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, ajones@ventanamicro.com Subject: [PATCH v3 09/10] RISC-V: KVM: Improve vector save/restore errors Date: Thu, 3 Aug 2023 11:00:21 -0300 Message-ID: <20230803140022.399333-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803140022.399333-1-dbarboza@ventanamicro.com> References: <20230803140022.399333-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Andrew Jones kvm_riscv_vcpu_(get/set)_reg_vector() now returns ENOENT if V is not available, EINVAL if reg type is not of VECTOR type, and any error that might be thrown by kvm_riscv_vcpu_vreg_addr(). Signed-off-by: Andrew Jones --- arch/riscv/kvm/vcpu_vector.c | 60 ++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 27 deletions(-) diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c index edd2eecbddc2..39c5bceb4d1b 100644 --- a/arch/riscv/kvm/vcpu_vector.c +++ b/arch/riscv/kvm/vcpu_vector.c @@ -91,44 +91,44 @@ void kvm_riscv_vcpu_free_vector_context(struct kvm_vcpu *vcpu) } #endif -static void *kvm_riscv_vcpu_vreg_addr(struct kvm_vcpu *vcpu, +static int kvm_riscv_vcpu_vreg_addr(struct kvm_vcpu *vcpu, unsigned long reg_num, - size_t reg_size) + size_t reg_size, + void **reg_val) { struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; - void *reg_val; size_t vlenb = riscv_v_vsize / 32; if (reg_num < KVM_REG_RISCV_VECTOR_REG(0)) { if (reg_size != sizeof(unsigned long)) - return NULL; + return -EINVAL; switch (reg_num) { case KVM_REG_RISCV_VECTOR_CSR_REG(vstart): - reg_val = &cntx->vector.vstart; + *reg_val = &cntx->vector.vstart; break; case KVM_REG_RISCV_VECTOR_CSR_REG(vl): - reg_val = &cntx->vector.vl; + *reg_val = &cntx->vector.vl; break; case KVM_REG_RISCV_VECTOR_CSR_REG(vtype): - reg_val = &cntx->vector.vtype; + *reg_val = &cntx->vector.vtype; break; case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr): - reg_val = &cntx->vector.vcsr; + *reg_val = &cntx->vector.vcsr; break; case KVM_REG_RISCV_VECTOR_CSR_REG(datap): default: - return NULL; + return -ENOENT; } } else if (reg_num <= KVM_REG_RISCV_VECTOR_REG(31)) { if (reg_size != vlenb) - return NULL; - reg_val = cntx->vector.datap + return -EINVAL; + *reg_val = cntx->vector.datap + (reg_num - KVM_REG_RISCV_VECTOR_REG(0)) * vlenb; } else { - return NULL; + return -ENOENT; } - return reg_val; + return 0; } int kvm_riscv_vcpu_get_reg_vector(struct kvm_vcpu *vcpu, @@ -141,17 +141,20 @@ int kvm_riscv_vcpu_get_reg_vector(struct kvm_vcpu *vcpu, unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | rtype); - void *reg_val = NULL; size_t reg_size = KVM_REG_SIZE(reg->id); + void *reg_val; + int rc; - if (rtype == KVM_REG_RISCV_VECTOR && - riscv_isa_extension_available(isa, v)) { - reg_val = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size); - } - - if (!reg_val) + if (rtype != KVM_REG_RISCV_VECTOR) return -EINVAL; + if (!riscv_isa_extension_available(isa, v)) + return -ENOENT; + + rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, ®_val); + if (rc) + return rc; + if (copy_to_user(uaddr, reg_val, reg_size)) return -EFAULT; @@ -168,17 +171,20 @@ int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu, unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | rtype); - void *reg_val = NULL; size_t reg_size = KVM_REG_SIZE(reg->id); + void *reg_val; + int rc; - if (rtype == KVM_REG_RISCV_VECTOR && - riscv_isa_extension_available(isa, v)) { - reg_val = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size); - } - - if (!reg_val) + if (rtype != KVM_REG_RISCV_VECTOR) return -EINVAL; + if (!riscv_isa_extension_available(isa, v)) + return -ENOENT; + + rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, ®_val); + if (rc) + return rc; + if (copy_from_user(reg_val, uaddr, reg_size)) return -EFAULT; From patchwork Thu Aug 3 14:00:22 2023 Content-Type: text/plain; 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([187.11.154.63]) by smtp.gmail.com with ESMTPSA id e14-20020a0568301e4e00b006b29a73efb5sm11628otj.7.2023.08.03.07.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 07:00:58 -0700 (PDT) From: Daniel Henrique Barboza To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: anup@brainfault.org, atishp@atishpatra.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 10/10] docs: kvm: riscv: document EBUSY in KVM_SET_ONE_REG Date: Thu, 3 Aug 2023 11:00:22 -0300 Message-ID: <20230803140022.399333-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803140022.399333-1-dbarboza@ventanamicro.com> References: <20230803140022.399333-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The EBUSY errno is being used for KVM_SET_ONE_REG as a way to tell userspace that a given reg can't be changed after the vcpu started. Signed-off-by: Daniel Henrique Barboza --- Documentation/virt/kvm/api.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index c0ddd3035462..3249fb56cc69 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -2259,6 +2259,8 @@ Errors: EINVAL invalid register ID, or no such register or used with VMs in protected virtualization mode on s390 EPERM (arm64) register access not allowed before vcpu finalization + EBUSY (riscv) changing register value not allowed after the vcpu + has run at least once ====== ============================================================ (These error codes are indicative only: do not rely on a specific error