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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L , "Rafael J . Wysocki" Subject: [RFC PATCH v1 01/21] ACPICA: MADT: Add RISC-V external interrupt controllers Date: Thu, 3 Aug 2023 23:28:56 +0530 Message-Id: <20230803175916.3174453-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org ACPICA commit 8c048cee4ea7b9ded8db3e1b3b9c14e21e084a2c This adds 3 different external interrupt controller definitions in MADT for RISC-V. 1) RISC-V PLIC is a platform interrupt controller for handling wired interrupt in a RISC-V systems. 2) RISC-V IMSIC is MSI interrupt controller to support MSI interrupts. 3) RISC-V APLIC has dual functionality. First it can act like PLIC and direct all wired interrupts to the CPU which doesn't have MSI controller. Second, when the CPU has MSI controller (IMSIC), it will act as a converter from wired interrupts to MSI. Update the existing RINTC structure also to support these external interrupt controllers. This codefirst ECR is approved by UEFI forum and will be part of next ACPI spec version. Link: https://github.com/acpica/acpica/commit/8c048cee Co-developed-by: Haibo Xu Signed-off-by: Haibo Xu Signed-off-by: Sunil V L Signed-off-by: Bob Moore Signed-off-by: Rafael J. Wysocki --- include/acpi/actbl2.h | 50 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index 0029336775a9..280ab4c7f77a 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -893,7 +893,10 @@ enum acpi_madt_type { ACPI_MADT_TYPE_BIO_PIC = 22, ACPI_MADT_TYPE_LPC_PIC = 23, ACPI_MADT_TYPE_RINTC = 24, - ACPI_MADT_TYPE_RESERVED = 25, /* 25 to 0x7F are reserved */ + ACPI_MADT_TYPE_IMSIC = 25, + ACPI_MADT_TYPE_APLIC = 26, + ACPI_MADT_TYPE_PLIC = 27, + ACPI_MADT_TYPE_RESERVED = 28, /* 28 to 0x7F are reserved */ ACPI_MADT_TYPE_OEM_RESERVED = 0x80 /* 0x80 to 0xFF are reserved for OEM use */ }; @@ -1261,6 +1264,9 @@ struct acpi_madt_rintc { u32 flags; u64 hart_id; u32 uid; /* ACPI processor UID */ + u32 ext_intc_id; /* External INTC Id */ + u64 imsic_addr; /* IMSIC base address */ + u32 imsic_size; /* IMSIC size */ }; /* Values for RISC-V INTC Version field above */ @@ -1271,6 +1277,48 @@ enum acpi_madt_rintc_version { ACPI_MADT_RINTC_VERSION_RESERVED = 2 /* 2 and greater are reserved */ }; +/* 25: RISC-V IMSIC */ +struct acpi_madt_imsic { + struct acpi_subtable_header header; + u8 version; + u8 reserved; + u32 flags; + u16 num_ids; + u16 num_guest_ids; + u8 guest_index_bits; + u8 hart_index_bits; + u8 group_index_bits; + u8 group_index_shift; +}; + +/* 26: RISC-V APLIC */ +struct acpi_madt_aplic { + struct acpi_subtable_header header; + u8 version; + u8 id; + u32 flags; + u8 hw_id[8]; + u16 num_idcs; + u16 num_sources; + u32 gsi_base; + u64 base_addr; + u32 size; +}; + +/* 27: RISC-V PLIC */ +struct acpi_madt_plic { + struct acpi_subtable_header header; + u8 version; + u8 id; + u8 hw_id[8]; + u16 num_irqs; + u16 max_prio; + u32 flags; + u32 size; + u64 base_addr; + u32 gsi_base; +}; + /* 80: OEM data */ struct acpi_madt_oem_data { From patchwork Thu Aug 3 17:58:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7E3EEB64DD for ; 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Thu, 03 Aug 2023 10:59:49 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.10.59.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 10:59:49 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L , "Rafael J . Wysocki" Subject: [RFC PATCH v1 02/21] ACPICA: RHCT: Add flags, CMO and MMU nodes Date: Thu, 3 Aug 2023 23:28:57 +0530 Message-Id: <20230803175916.3174453-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org ACPICA commit 2eded5a6a13d892b7dc3be6096e7b1e8d4407600 Update RHCT table with below details. 1) Add additional structure to describe the Cache Management Operation (CMO) related information. 2) Add structure to describe MMU type. 3) Convert the current reserved field to flags and define a flag to indicate timer capability. This codefirst ECR is approved by UEFI forum and will be part of next ACPI spec version. Link: https://github.com/acpica/acpica/commit/2eded5a6 Signed-off-by: Sunil V L Signed-off-by: Bob Moore Signed-off-by: Rafael J. Wysocki --- include/acpi/actbl2.h | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index 280ab4c7f77a..3751ae69432f 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -2778,12 +2778,15 @@ enum acpi_rgrt_image_type { struct acpi_table_rhct { struct acpi_table_header header; /* Common ACPI table header */ - u32 reserved; + u32 flags; /* RHCT flags */ u64 time_base_freq; u32 node_count; u32 node_offset; }; +/* RHCT Flags */ + +#define ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU (1) /* * RHCT subtables */ @@ -2797,6 +2800,9 @@ struct acpi_rhct_node_header { enum acpi_rhct_node_type { ACPI_RHCT_NODE_TYPE_ISA_STRING = 0x0000, + ACPI_RHCT_NODE_TYPE_CMO = 0x0001, + ACPI_RHCT_NODE_TYPE_MMU = 0x0002, + ACPI_RHCT_NODE_TYPE_RESERVED = 0x0003, ACPI_RHCT_NODE_TYPE_HART_INFO = 0xFFFF, }; @@ -2810,6 +2816,24 @@ struct acpi_rhct_isa_string { char isa[]; }; +struct acpi_rhct_cmo_node { + u8 reserved; /* Must be zero */ + u8 cbom_size; /* CBOM size in powerof 2 */ + u8 cbop_size; /* CBOP size in powerof 2 */ + u8 cboz_size; /* CBOZ size in powerof 2 */ +}; + +struct acpi_rhct_mmu_node { + u8 reserved; /* Must be zero */ + u8 mmu_type; /* Virtual Address Scheme */ +}; + +enum acpi_rhct_mmu_type { + ACPI_RHCT_MMU_TYPE_SV39 = 0, + ACPI_RHCT_MMU_TYPE_SV48 = 1, + ACPI_RHCT_MMU_TYPE_SV57 = 2 +}; + /* Hart Info node structure */ struct acpi_rhct_hart_info { u16 num_offsets; From patchwork Thu Aug 3 17:58:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F04DBEB64DD for ; Thu, 3 Aug 2023 18:00:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233822AbjHCSAY (ORCPT ); Thu, 3 Aug 2023 14:00:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235202AbjHCSAH (ORCPT ); Thu, 3 Aug 2023 14:00:07 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D37444B0 for ; Thu, 3 Aug 2023 10:59:57 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-686ed1d2594so1081546b3a.2 for ; Thu, 03 Aug 2023 10:59:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691085597; x=1691690397; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dlgMxBU+gnbxavLK2CnXHLqjxrOHpsQhLJivrmp7gq8=; b=Mn/vo0MoTkPiEepTolmO07DSHUYqv7rFmArT6LTUsVmzAqnBvKBjkRZBvhSJTyiZAM 1h1+n6DkofxPjLLD7asRa2i/oE66f7GWtWQqA9+nDJYue6PrwjDM067chowzEAr4ODxH vSRhcalLZi64uzfoqGFqhxbjGjGGDhdaLNb94wU3+LcfSd6SGzYCkrAI2qx43QP8mXm+ DJ0Il1lN5U+uqlCxzJ+JnPkr+AJ87TQm7Mbi6Aqs2pV30Apw6vIAlJMrvnORHqksud91 revKW71DM8rTMoqvZp3Ftaus2TBe8ju/o/MzItnmUE5tDKZn5+PQ0RhtNd0uQFIakZk6 1UZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691085597; x=1691690397; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dlgMxBU+gnbxavLK2CnXHLqjxrOHpsQhLJivrmp7gq8=; b=XMyPsDleoTefcd5+XfalaoT4chNyXXyFW1UQBJnVzRnD6d5EkpjMUUmqf5Si8IJBWC yQKsJ7rKU8AX0mjizHe2rWGNORpeuSmz+dWRMePXVZr9gLEjHnKnqj7LQVTqia6yWPFr bZcJ2T3Cd1wrGRbSioX8927cmp3aOn3VaxwWu3UkVNKuisEOjQA+XGg0baqmaOVcE624 EN4f94UTDS3krahQtF8OlF7vh8gAggKBOkAiqkzyMCYKVqYKP9K/SYPDbiMoOhLLUb98 26+VUSnnT+rZ6bI89KFPNvVbJmyXwDk7mumVwbtdYC+KkF9UbglfO5V9KbW45Iq6jVEe hW/Q== X-Gm-Message-State: ABy/qLa0LerFZXy5QrYTYjuYUG4VC3X+fObQ1y59fsaQ0cmC50AaCt4A xBY2a7FabHS860yB0gC04j4UnQ== X-Google-Smtp-Source: APBJJlHeLQhx5wJXxieN87kQ/FrrGdUXv58YAFTjJ6UeQQPmtQGf8bvG5vbiImqAXiXcjHGvc1bNlw== X-Received: by 2002:a05:6a00:c86:b0:682:4c9f:aa0 with SMTP id a6-20020a056a000c8600b006824c9f0aa0mr23559310pfv.29.1691085596954; Thu, 03 Aug 2023 10:59:56 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.10.59.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 10:59:56 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L , kernel test robot Subject: [RFC PATCH v1 03/21] RISC-V: ACPI: Fix acpi_os_ioremap to return iomem address Date: Thu, 3 Aug 2023 23:28:58 +0530 Message-Id: <20230803175916.3174453-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org acpi_os_ioremap() currently is a wrapper to memremap() on RISC-V. But the callers of acpi_os_ioremap() expect it to return __iomem address and hence sparse tool reports a new warning. Fix this issue by type casting to __iomem type. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202307230357.egcTAefj-lkp@intel.com/ Fixes: a91a9ffbd3a5 ("RISC-V: Add support to build the ACPI core") Signed-off-by: Sunil V L Reviewed-by: Andrew Jones --- arch/riscv/include/asm/acpi.h | 2 +- arch/riscv/kernel/acpi.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index f71ce21ff684..d5604d2073bc 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -19,7 +19,7 @@ typedef u64 phys_cpuid_t; #define PHYS_CPUID_INVALID INVALID_HARTID /* ACPI table mapping after acpi_permanent_mmap is set */ -void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size); +void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size); #define acpi_os_ioremap acpi_os_ioremap #define acpi_strict 1 /* No out-of-spec workarounds on RISC-V */ diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 5ee03ebab80e..56cb2c986c48 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -215,9 +215,9 @@ void __init __acpi_unmap_table(void __iomem *map, unsigned long size) early_iounmap(map, size); } -void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) +void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) { - return memremap(phys, size, MEMREMAP_WB); + return (void __iomem *)memremap(phys, size, MEMREMAP_WB); } #ifdef CONFIG_PCI From patchwork Thu Aug 3 17:58:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFC28EB64DD for ; Thu, 3 Aug 2023 18:00:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235295AbjHCSAf (ORCPT ); Thu, 3 Aug 2023 14:00:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235386AbjHCSAT (ORCPT ); Thu, 3 Aug 2023 14:00:19 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5429B420C for ; Thu, 3 Aug 2023 11:00:05 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-68706d67ed9so908795b3a.2 for ; Thu, 03 Aug 2023 11:00:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691085605; x=1691690405; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zrij3XCVzAcOqQorsC5sehKTr0CEJKtsrFsGaW9zZqM=; b=g6+YMcM4UaL1m62Ntt4qPvlZaEv/BYe4UX4PetuB3JttzYhNsA1GY4WTrRaVsePaTR atxJKkHV0OHfvFZ2y8Ln/HQAgi5oGOO9gAsr0K+aIIaY7ouzgXaONyhs/oUd71rdBMNZ LTqtCTDaFhTgMbf7aC8o2trc7JnD/nv6tEP80GHX3A+sLyfMvPmLcM1jG9CgM37CUAlF HA8ellFJwKVcSDXCbvFRMKk1KlpyWU7+fF8Ue932AzN1tptU0DxnNrPXXKi8jfk7+sRR EjceIniHqsZY3gcJMhRO2hVSYyvOldIln61vUNwnPp8vNEzk5ArDaGdXypxKcq0OKj54 7How== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691085605; x=1691690405; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zrij3XCVzAcOqQorsC5sehKTr0CEJKtsrFsGaW9zZqM=; b=QwyU4FjUJfDkKr8FO5zioc2C22k4ojbiDa7uW7LZmdGJJ4aA6veEoesFt50xILnTct IL7pqaROHL/7+uBsHGa7oL1VT+NN81KuuYfqs6HQXD2P7/OcrmHFyEIbXGv18fNKfM4u OYCmY8NjziVfMFopOSzzUEdwIK8owtftkRd0LolrpEHgFoqdSVB2Ecf1S+G7dh30+MrY OIrgpLZiF3dThbgYbr6OXv1J6uPIiU3DlAfEPuv9Jbdfqqzut/Z53i9yxzGSj6UCPYoK QgN9NkIwmzfWceClH3ayfKM90k3CLHd/RdxAeuqFjfwMzpkxuCbDi8ytkfpMsbUOECBN U1Mw== X-Gm-Message-State: ABy/qLYdglGxFKBpidoTNaA71Br/tp98vHpSAsONLPgazyYOibGK33Ak CGV8v4s3gLDtzxX/fG1vGx9pKA== X-Google-Smtp-Source: APBJJlGfqnPnWK07EeosxE/Z01LsrLZM2OzMNSmgb3YDtRcKmZUzwJl9E9d4B2w1+YCc7DEVzsQZpA== X-Received: by 2002:aa7:8896:0:b0:687:4369:4ad2 with SMTP id z22-20020aa78896000000b0068743694ad2mr12618344pfe.33.1691085604789; Thu, 03 Aug 2023 11:00:04 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.10.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 11:00:04 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L , Ard Biesheuvel , Alexandre Ghiti Subject: [RFC PATCH v1 04/21] RISC-V: ACPI: Enhance acpi_os_ioremap with MMIO remapping Date: Thu, 3 Aug 2023 23:28:59 +0530 Message-Id: <20230803175916.3174453-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enhance the acpi_os_ioremap() to support opregions in MMIO space. Also, have strict checks using EFI memory map to allow remapping the RAM similar to arm64. Cc: Ard Biesheuvel Cc: Alexandre Ghiti Signed-off-by: Sunil V L Reviewed-by: Andrew Jones --- arch/riscv/Kconfig | 1 + arch/riscv/kernel/acpi.c | 86 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 86 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 318f62a0a187..e19f32c12a68 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -38,6 +38,7 @@ config RISCV select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAS_UBSAN_SANITIZE_ALL select ARCH_HAS_VDSO_DATA + select ARCH_KEEP_MEMBLOCK select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT select ARCH_STACKWALK diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 56cb2c986c48..aa4433bca6d9 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -17,6 +17,7 @@ #include #include #include +#include int acpi_noirq = 1; /* skip ACPI IRQ initialization */ int acpi_disabled = 1; @@ -217,7 +218,90 @@ void __init __acpi_unmap_table(void __iomem *map, unsigned long size) void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) { - return (void __iomem *)memremap(phys, size, MEMREMAP_WB); + efi_memory_desc_t *md, *region = NULL; + pgprot_t prot; + + if (WARN_ON_ONCE(!efi_enabled(EFI_MEMMAP))) + return NULL; + + for_each_efi_memory_desc(md) { + u64 end = md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT); + + if (phys < md->phys_addr || phys >= end) + continue; + + if (phys + size > end) { + pr_warn(FW_BUG "requested region covers multiple EFI memory regions\n"); + return NULL; + } + region = md; + break; + } + + /* + * It is fine for AML to remap regions that are not represented in the + * EFI memory map at all, as it only describes normal memory, and MMIO + * regions that require a virtual mapping to make them accessible to + * the EFI runtime services. + */ + prot = PAGE_KERNEL_IO; + if (region) { + switch (region->type) { + case EFI_LOADER_CODE: + case EFI_LOADER_DATA: + case EFI_BOOT_SERVICES_CODE: + case EFI_BOOT_SERVICES_DATA: + case EFI_CONVENTIONAL_MEMORY: + case EFI_PERSISTENT_MEMORY: + if (memblock_is_map_memory(phys) || + !memblock_is_region_memory(phys, size)) { + pr_warn(FW_BUG "requested region covers kernel memory @ %p\n", + &phys); + return NULL; + } + + /* + * Mapping kernel memory is permitted if the region in + * question is covered by a single memblock with the + * NOMAP attribute set: this enables the use of ACPI + * table overrides passed via initramfs. + * This particular use case only requires read access. + */ + fallthrough; + + case EFI_RUNTIME_SERVICES_CODE: + /* + * This would be unusual, but not problematic per se, + * as long as we take care not to create a writable + * mapping for executable code. + */ + prot = PAGE_KERNEL_RO; + break; + + case EFI_ACPI_RECLAIM_MEMORY: + /* + * ACPI reclaim memory is used to pass firmware tables + * and other data that is intended for consumption by + * the OS only, which may decide it wants to reclaim + * that memory and use it for something else. We never + * do that, but we usually add it to the linear map + * anyway, in which case we should use the existing + * mapping. + */ + if (memblock_is_map_memory(phys)) + return (void __iomem *)__va(phys); + fallthrough; + + default: + if (region->attribute & EFI_MEMORY_WB) + prot = PAGE_KERNEL; + else if ((region->attribute & EFI_MEMORY_WC) || + (region->attribute & EFI_MEMORY_WT)) + prot = pgprot_writecombine(PAGE_KERNEL); + } + } + + return ioremap_prot(phys, size, pgprot_val(prot)); } #ifdef CONFIG_PCI From patchwork Thu Aug 3 17:59:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A56A4C001DF for ; Thu, 3 Aug 2023 18:00:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235486AbjHCSAr (ORCPT ); Thu, 3 Aug 2023 14:00:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235365AbjHCSAa (ORCPT ); Thu, 3 Aug 2023 14:00:30 -0400 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9614422C for ; Thu, 3 Aug 2023 11:00:12 -0700 (PDT) Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-68706b39c4cso872906b3a.2 for ; Thu, 03 Aug 2023 11:00:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691085612; x=1691690412; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HZyznREMZ8qiEWo3qjSd8Z0EQsRbIhIXLSiUggIdL7w=; b=bhy59+dhquk68hVW4TYBfVmR4DtOFAh+z/J4S7eciFPke/xmbBwjsryJ7msuofRPuG vVdDuXH9t3SSriCDYwOVZM8q3FxGRY2RH90vlHkQIwhjf78qVjpWQhSw7wl0yRgRn9hv dZigT3MWX8H0sp5XlUOaNyc6ioh8fogPRZ5Dvjw8IWbukbzFacsVQ+t0hWC7RzB0vx7C 5ndErCCZFOKEP/ZPBnFnejvCxYDQh4yLDtIM5EBYU6GuVRO25EflgU7kXoXggtmfGuAf 5P+0nyfgM6je2/UtheiqMF3FrQn+O6GpRiGxExAmqg0NZ67AfymAIl91V/mq1CdFspIn IQWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691085612; x=1691690412; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HZyznREMZ8qiEWo3qjSd8Z0EQsRbIhIXLSiUggIdL7w=; b=gIT70NO5a8xfXQTmPilRa25bnncLIrD7bBdRjgIMybthg6qLOzeKTYKqRyh8f1uMgU mz50RrfTAlVxEOWuSkzo3WoWOaUHpapLuvJAHGAiTGiqVzcxObdXoFsIlGy+CBfZC1sU nwkvHuPLl9AxnvZK3OR06kibHXVvhm2Bl3gD+SfcVcPzPo85571A3tYjeLVt4brM092G MkNMt9+1f1khs4h3siEwgwbJDiLm+qqKNf95w2e/dHdG5Y/SZB9/WN/eMOG73lMUBdU0 s7HB+aSoAUZZPg95T7RRc1ZaJufJ+JB8PbsxOEjY77mQQMJjEESdfO0XjlNVWOa+Vbv1 oA/w== X-Gm-Message-State: ABy/qLaO2JFvfxw1SXmieWusSIG6D23G9F2PSWqqPHy3QzchwQAZKMI+ fCeNUzqkd9C7BfqMaiBm6JUZiQ== X-Google-Smtp-Source: APBJJlHWtEMJq7mXKgUBGIx9XN43JG5wb/bpmSTxX17st1RfcU7TluTI0q6kTlK66lbr30/sl+mHtg== X-Received: by 2002:a05:6a00:a0f:b0:686:2ad5:d11c with SMTP id p15-20020a056a000a0f00b006862ad5d11cmr22201623pfh.33.1691085612223; Thu, 03 Aug 2023 11:00:12 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.11.00.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 11:00:11 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 05/21] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Date: Thu, 3 Aug 2023 23:29:00 +0530 Message-Id: <20230803175916.3174453-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The functions defined in arm64 for ACPI support are required for RISC-V also. To avoid duplication, copy these functions to common location. Signed-off-by: Sunil V L --- arch/arm64/kernel/pci.c | 193 ---------------------------------------- drivers/pci/pci-acpi.c | 182 +++++++++++++++++++++++++++++++++++++ 2 files changed, 182 insertions(+), 193 deletions(-) diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index 2276689b5411..fd9a7bed83ce 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -6,30 +6,7 @@ * Copyright (C) 2014 ARM Ltd. */ -#include -#include -#include -#include -#include -#include -#include #include -#include -#include -#include - -#ifdef CONFIG_ACPI -/* - * Try to assign the IRQ number when probing a new device - */ -int pcibios_alloc_irq(struct pci_dev *dev) -{ - if (!acpi_disabled) - acpi_pci_irq_enable(dev); - - return 0; -} -#endif /* * raw_pci_read/write - Platform-specific PCI config space access. @@ -63,173 +40,3 @@ int pcibus_to_node(struct pci_bus *bus) EXPORT_SYMBOL(pcibus_to_node); #endif - -#ifdef CONFIG_ACPI - -struct acpi_pci_generic_root_info { - struct acpi_pci_root_info common; - struct pci_config_window *cfg; /* config space mapping */ -}; - -int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) -{ - struct pci_config_window *cfg = bus->sysdata; - struct acpi_device *adev = to_acpi_device(cfg->parent); - struct acpi_pci_root *root = acpi_driver_data(adev); - - return root->segment; -} - -int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) -{ - struct pci_config_window *cfg; - struct acpi_device *adev; - struct device *bus_dev; - - if (acpi_disabled) - return 0; - - cfg = bridge->bus->sysdata; - - /* - * On Hyper-V there is no corresponding ACPI device for a root bridge, - * therefore ->parent is set as NULL by the driver. And set 'adev' as - * NULL in this case because there is no proper ACPI device. - */ - if (!cfg->parent) - adev = NULL; - else - adev = to_acpi_device(cfg->parent); - - bus_dev = &bridge->bus->dev; - - ACPI_COMPANION_SET(&bridge->dev, adev); - set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev))); - - return 0; -} - -static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) -{ - struct resource_entry *entry, *tmp; - int status; - - status = acpi_pci_probe_root_resources(ci); - resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { - if (!(entry->res->flags & IORESOURCE_WINDOW)) - resource_list_destroy_entry(entry); - } - return status; -} - -/* - * Lookup the bus range for the domain in MCFG, and set up config space - * mapping. - */ -static struct pci_config_window * -pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) -{ - struct device *dev = &root->device->dev; - struct resource *bus_res = &root->secondary; - u16 seg = root->segment; - const struct pci_ecam_ops *ecam_ops; - struct resource cfgres; - struct acpi_device *adev; - struct pci_config_window *cfg; - int ret; - - ret = pci_mcfg_lookup(root, &cfgres, &ecam_ops); - if (ret) { - dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); - return NULL; - } - - adev = acpi_resource_consumer(&cfgres); - if (adev) - dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres, - dev_name(&adev->dev)); - else - dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n", - &cfgres); - - cfg = pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); - if (IS_ERR(cfg)) { - dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, - PTR_ERR(cfg)); - return NULL; - } - - return cfg; -} - -/* release_info: free resources allocated by init_info */ -static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) -{ - struct acpi_pci_generic_root_info *ri; - - ri = container_of(ci, struct acpi_pci_generic_root_info, common); - pci_ecam_free(ri->cfg); - kfree(ci->ops); - kfree(ri); -} - -/* Interface called from ACPI code to setup PCI host controller */ -struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) -{ - struct acpi_pci_generic_root_info *ri; - struct pci_bus *bus, *child; - struct acpi_pci_root_ops *root_ops; - struct pci_host_bridge *host; - - ri = kzalloc(sizeof(*ri), GFP_KERNEL); - if (!ri) - return NULL; - - root_ops = kzalloc(sizeof(*root_ops), GFP_KERNEL); - if (!root_ops) { - kfree(ri); - return NULL; - } - - ri->cfg = pci_acpi_setup_ecam_mapping(root); - if (!ri->cfg) { - kfree(ri); - kfree(root_ops); - return NULL; - } - - root_ops->release_info = pci_acpi_generic_release_info; - root_ops->prepare_resources = pci_acpi_root_prepare_resources; - root_ops->pci_ops = (struct pci_ops *)&ri->cfg->ops->pci_ops; - bus = acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg); - if (!bus) - return NULL; - - /* If we must preserve the resource configuration, claim now */ - host = pci_find_host_bridge(bus); - if (host->preserve_config) - pci_bus_claim_resources(bus); - - /* - * Assign whatever was left unassigned. If we didn't claim above, - * this will reassign everything. - */ - pci_assign_unassigned_root_bus_resources(bus); - - list_for_each_entry(child, &bus->children, node) - pcie_bus_configure_settings(child); - - return bus; -} - -void pcibios_add_bus(struct pci_bus *bus) -{ - acpi_pci_add_bus(bus); -} - -void pcibios_remove_bus(struct pci_bus *bus) -{ - acpi_pci_remove_bus(bus); -} - -#endif diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index a05350a4e49c..d6b2d64b8237 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1517,4 +1518,185 @@ static int __init acpi_pci_init(void) return 0; } + arch_initcall(acpi_pci_init); + +#if defined(CONFIG_ARM64) +/* + * Try to assign the IRQ number when probing a new device + */ +int pcibios_alloc_irq(struct pci_dev *dev) +{ + if (!acpi_disabled) + acpi_pci_irq_enable(dev); + + return 0; +} + +struct acpi_pci_generic_root_info { + struct acpi_pci_root_info common; + struct pci_config_window *cfg; /* config space mapping */ +}; + +int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) +{ + struct pci_config_window *cfg = bus->sysdata; + struct acpi_device *adev = to_acpi_device(cfg->parent); + struct acpi_pci_root *root = acpi_driver_data(adev); + + return root->segment; +} + +int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) +{ + struct pci_config_window *cfg; + struct acpi_device *adev; + struct device *bus_dev; + + if (acpi_disabled) + return 0; + + cfg = bridge->bus->sysdata; + + /* + * On Hyper-V there is no corresponding ACPI device for a root bridge, + * therefore ->parent is set as NULL by the driver. And set 'adev' as + * NULL in this case because there is no proper ACPI device. + */ + if (!cfg->parent) + adev = NULL; + else + adev = to_acpi_device(cfg->parent); + + bus_dev = &bridge->bus->dev; + + ACPI_COMPANION_SET(&bridge->dev, adev); + set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev))); + + return 0; +} + +static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) +{ + struct resource_entry *entry, *tmp; + int status; + + status = acpi_pci_probe_root_resources(ci); + resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { + if (!(entry->res->flags & IORESOURCE_WINDOW)) + resource_list_destroy_entry(entry); + } + return status; +} + +/* + * Lookup the bus range for the domain in MCFG, and set up config space + * mapping. + */ +static struct pci_config_window * +pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) +{ + struct device *dev = &root->device->dev; + struct resource *bus_res = &root->secondary; + u16 seg = root->segment; + const struct pci_ecam_ops *ecam_ops; + struct resource cfgres; + struct acpi_device *adev; + struct pci_config_window *cfg; + int ret; + + ret = pci_mcfg_lookup(root, &cfgres, &ecam_ops); + if (ret) { + dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); + return NULL; + } + + adev = acpi_resource_consumer(&cfgres); + if (adev) + dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres, + dev_name(&adev->dev)); + else + dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n", + &cfgres); + + cfg = pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); + if (IS_ERR(cfg)) { + dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, + PTR_ERR(cfg)); + return NULL; + } + + return cfg; +} + +/* release_info: free resources allocated by init_info */ +static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) +{ + struct acpi_pci_generic_root_info *ri; + + ri = container_of(ci, struct acpi_pci_generic_root_info, common); + pci_ecam_free(ri->cfg); + kfree(ci->ops); + kfree(ri); +} + +/* Interface called from ACPI code to setup PCI host controller */ +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ + struct acpi_pci_generic_root_info *ri; + struct pci_bus *bus, *child; + struct acpi_pci_root_ops *root_ops; + struct pci_host_bridge *host; + + ri = kzalloc(sizeof(*ri), GFP_KERNEL); + if (!ri) + return NULL; + + root_ops = kzalloc(sizeof(*root_ops), GFP_KERNEL); + if (!root_ops) { + kfree(ri); + return NULL; + } + + ri->cfg = pci_acpi_setup_ecam_mapping(root); + if (!ri->cfg) { + kfree(ri); + kfree(root_ops); + return NULL; + } + + root_ops->release_info = pci_acpi_generic_release_info; + root_ops->prepare_resources = pci_acpi_root_prepare_resources; + root_ops->pci_ops = (struct pci_ops *)&ri->cfg->ops->pci_ops; + bus = acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg); + if (!bus) + return NULL; + + /* If we must preserve the resource configuration, claim now */ + host = pci_find_host_bridge(bus); + if (host->preserve_config) + pci_bus_claim_resources(bus); + + /* + * Assign whatever was left unassigned. If we didn't claim above, + * this will reassign everything. + */ + pci_assign_unassigned_root_bus_resources(bus); + + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + + return bus; +} + +void pcibios_add_bus(struct pci_bus *bus) +{ + acpi_pci_add_bus(bus); +} + +void pcibios_remove_bus(struct pci_bus *bus) +{ + acpi_pci_remove_bus(bus); +} + +#endif From patchwork Thu Aug 3 17:59:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340390 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D82BBEB64DD for ; Thu, 3 Aug 2023 18:01:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235384AbjHCSA7 (ORCPT ); Thu, 3 Aug 2023 14:00:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235328AbjHCSAg (ORCPT ); Thu, 3 Aug 2023 14:00:36 -0400 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 264AC4482 for ; Thu, 3 Aug 2023 11:00:20 -0700 (PDT) Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-686f0d66652so1090418b3a.2 for ; Thu, 03 Aug 2023 11:00:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691085619; x=1691690419; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7mbYpJBEy7QtZn0rLm+Z46rszMOgig5KvbO250k7OII=; b=YfGQrWrqKxoHHrzv18a348oKjGYv1gGQ4cGmgyQBPY/sWq0LFcGm3LxWdqhhJX9N9s kBW3WG3VU+N9md0iX82nHkzuBp2q4t7soDxrCACNYYUFhcdhqpGhV2tZlHEQyVp7yC3I x3MZPiXRWfo/DCgcuqSvtbtyM5q1vXWl9zSat0C7GiPgfaHAdZmmf9DiiUkALXzC3yVv lSUTih5Yk/drJWTl6Lrv8KwxCFUZRYPN1Z/RXZ1bregl5jLq9/rXwM4R/ZO28pBL35/9 Tkint7JkljbwD6bJlr3TRUg/dGfiJuJLTrbOaZxni/zO2Vd+5zxHdGnGLPVhestQq1s9 FtbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691085619; x=1691690419; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7mbYpJBEy7QtZn0rLm+Z46rszMOgig5KvbO250k7OII=; b=Fv4d0d8YPozkRW72rG6EjIav8f7jsA4CelcgfZ0G/zBomDC9qvfVerOPRdMaNUdgll FobPxT55GupDABsW1Yye3j0R1azlNleSC05T9r+gZ2BwULSkqwmWc5yyhK6qKQRE6FPY jWWGDkBKZSnJHzbpNLw/+J6NsEewykxHyOW5vfMrS8oaoqvlUwB/f7r3Jg50RRVJS9nZ 2Cf2ocjUcJc6KMn86hjSrs9qjDiCovqa+4+GYn3Zz97mE6Moy1kYBSoaoKF63cPT6uQD cC9+JMxK3ghyyUoi1nmby2Uh3oReKB+1xLcZTZb2jWaQQOotn6ueyVfC0fKt/qw0gs/v ANdQ== X-Gm-Message-State: ABy/qLa3WebLiw/OGMmpvlC1LXNDouspL6HyW1la4eMvvvQ3eoOkqGgK tkKrU3YwsJg5QLvzLaWNhrM9RA== X-Google-Smtp-Source: APBJJlEzbrnno8tMNvQ3OeUKWzuED/8IeQRaqcQag7dwUOCCbEcY3VwgrJDme+hmO3Kc0CFMYucNRA== X-Received: by 2002:a05:6a21:718b:b0:134:b28f:b581 with SMTP id wq11-20020a056a21718b00b00134b28fb581mr20904425pzb.28.1691085619659; Thu, 03 Aug 2023 11:00:19 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.11.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 11:00:19 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 06/21] RISC-V: ACPI: Implement PCI related functionality Date: Thu, 3 Aug 2023 23:29:01 +0530 Message-Id: <20230803175916.3174453-7-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Replace the dummy implementation for PCI related functions with actual implementation. Signed-off-by: Sunil V L --- arch/riscv/kernel/acpi.c | 32 +++++++++++++++----------------- drivers/pci/pci-acpi.c | 2 +- 2 files changed, 16 insertions(+), 18 deletions(-) diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index aa4433bca6d9..01022c5802ec 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -307,29 +307,27 @@ void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) #ifdef CONFIG_PCI /* - * These interfaces are defined just to enable building ACPI core. - * TODO: Update it with actual implementation when external interrupt - * controller support is added in RISC-V ACPI. + * raw_pci_read/write - Platform-specific PCI config space access. */ -int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, - int reg, int len, u32 *val) +int raw_pci_read(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 *val) { - return PCIBIOS_DEVICE_NOT_FOUND; -} + struct pci_bus *b = pci_find_bus(domain, bus); -int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, - int reg, int len, u32 val) -{ - return PCIBIOS_DEVICE_NOT_FOUND; -} + if (!b) + return PCIBIOS_DEVICE_NOT_FOUND; -int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) -{ - return -1; + return b->ops->read(b, devfn, reg, len, val); } -struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +int raw_pci_write(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 val) { - return NULL; + struct pci_bus *b = pci_find_bus(domain, bus); + + if (!b) + return PCIBIOS_DEVICE_NOT_FOUND; + + return b->ops->write(b, devfn, reg, len, val); } #endif /* CONFIG_PCI */ diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index d6b2d64b8237..5af6188cdbe0 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -1521,7 +1521,7 @@ static int __init acpi_pci_init(void) arch_initcall(acpi_pci_init); -#if defined(CONFIG_ARM64) +#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV) /* * Try to assign the IRQ number when probing a new device */ From patchwork Thu Aug 3 17:59:02 2023 Content-Type: text/plain; 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Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 07/21] RISC-V: Kconfig: Select ECAM and MCFG Date: Thu, 3 Aug 2023 23:29:02 +0530 Message-Id: <20230803175916.3174453-8-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enable ECAM and MCFG to support PCIe on ACPI based platforms. Signed-off-by: Sunil V L --- arch/riscv/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index e19f32c12a68..79dc35e89d5f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -13,6 +13,7 @@ config 32BIT config RISCV def_bool y select ACPI_GENERIC_GSI if ACPI + select ACPI_MCFG if (ACPI && PCI) select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ARCH_DMA_DEFAULT_COHERENT select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION @@ -147,6 +148,7 @@ config RISCV select OF_EARLY_FLATTREE select OF_IRQ select PCI_DOMAINS_GENERIC if PCI + select PCI_ECAM if (ACPI && PCI) select PCI_MSI if PCI select RISCV_ALTERNATIVE if !XIP_KERNEL select RISCV_APLIC From patchwork Thu Aug 3 17:59:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340392 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8C7EC001DB for ; Thu, 3 Aug 2023 18:01:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232749AbjHCSB2 (ORCPT ); Thu, 3 Aug 2023 14:01:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235544AbjHCSA6 (ORCPT ); Thu, 3 Aug 2023 14:00:58 -0400 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8B0A469F for ; Thu, 3 Aug 2023 11:00:34 -0700 (PDT) Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-686ba97e4feso1110603b3a.0 for ; Thu, 03 Aug 2023 11:00:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691085634; x=1691690434; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vQhuhHdTYaoWEXKHMdQb/AIiT1M0AyktuFOnKoEYTGc=; b=InAgb86bmzIXD9aMahgzQO9of8OqAMtZa6GKa8YVTVY7PzoIGrnFhABT5iR9yUDpdb eldlLfYqaIJZ0JqKhkz88GT1tI9U1PbaGlbsR4bWfCh1DfbR0ACTXckiDCh17sNzcRLf f2WV3qxyJ/rWBuGW2ue4ffM6KV/QUAchCeozTJs9q5S/XcNQOsvfIpSb1jVFwiZ6oFq3 jlj10cncisuVGqqhaz2WZx3F8TaIGK9I5NjfThtEaXa1XobxVSAqQwN9SPkmA39vlFlT 61lNiezvzG66VfjvuK2JSEbbCShorb/rqB7QdxU1TuTKXQUwQJNjJ66LD7fLCbx8z4t0 5PbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691085634; x=1691690434; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vQhuhHdTYaoWEXKHMdQb/AIiT1M0AyktuFOnKoEYTGc=; b=My8E9CzNi79Z6DWrueZNoJhJrtjw3wI2OOMV1jJF8WSmKCcPirIPPulbepdLjJQzyf QndnOZ/aao9nhAE8b62j5QM/RJY296YeAWLfm9QvkhRYMXsxw/cLyWa/D5df/CzcLNIH ukT37Q0Mf8Im+hN0qg4vmmUKoZSCcLimnC0EKluoK0yw34ZHCxLth514xZ42V+RG1Vmu ogbapGKTRIBWpQzHicci/Be9GgObR4xf6wPK2L11vkIcIRfEb0x/ey49wZ94oj9U21NN KOiGXhJMA7+nygOxvd4onUtasuZlMgEv65OoU6fFc+4ZBa4o1RWylnSnTCjWeNCgU0UV vrMQ== X-Gm-Message-State: ABy/qLbq+GeDYHNGXsU4xwVBRjsO4LjF3vJW4FaRxBjIIigBvSfGIVsc u2TUFrH485b+vjMLbjovPioeTA== X-Google-Smtp-Source: APBJJlFH8jQEzxXg6hi15nylBcj+0LbOiklmHj6H9WKQlfFcoVNBUAfYIpWWjK+zKN9M7HAojMJwCw== X-Received: by 2002:a05:6a21:6d95:b0:134:4f86:7966 with SMTP id wl21-20020a056a216d9500b001344f867966mr25365705pzb.9.1691085634213; Thu, 03 Aug 2023 11:00:34 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.11.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 11:00:33 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 08/21] RISC-V: ACPI: RHCT: Add function to get CBO block sizes Date: Thu, 3 Aug 2023 23:29:03 +0530 Message-Id: <20230803175916.3174453-9-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org CBO related block size in ACPI is provided by RHCT. Add support to read the CMO node in RHCT to get this information. Signed-off-by: Sunil V L --- arch/riscv/include/asm/acpi.h | 9 ++++++ drivers/acpi/riscv/rhct.c | 61 +++++++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index d5604d2073bc..0c4e8b35103e 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -66,6 +66,8 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa); static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; } +int acpi_get_cbo_block_size(struct acpi_table_header *table, unsigned int cpu, u32 *cbom_size, + u32 *cboz_size, u32 *cbop_size); #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) @@ -79,6 +81,13 @@ static inline int acpi_get_riscv_isa(struct acpi_table_header *table, return -EINVAL; } +static inline int acpi_get_cbo_block_size(struct acpi_table_header *table, + unsigned int cpu, u32 *cbom_size, + u32 *cboz_size, u32 *cbop_size) +{ + return -EINVAL; +} + #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/drivers/acpi/riscv/rhct.c b/drivers/acpi/riscv/rhct.c index b280b3e9c7d9..07309525f277 100644 --- a/drivers/acpi/riscv/rhct.c +++ b/drivers/acpi/riscv/rhct.c @@ -81,3 +81,64 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const return -1; } + +/* + * During early boot, the caller should call acpi_get_table() and pass its pointer to + * these functions(and free up later). At run time, since this table can be used + * multiple times, pass NULL so that the table remains in memory + */ +int acpi_get_cbo_block_size(struct acpi_table_header *table, unsigned int cpu, + u32 *cbom_size, u32 *cboz_size, u32 *cbop_size) +{ + struct acpi_rhct_node_header *node, *ref_node, *end; + u32 size_hdr = sizeof(struct acpi_rhct_node_header); + u32 size_hartinfo = sizeof(struct acpi_rhct_hart_info); + struct acpi_rhct_hart_info *hart_info; + struct acpi_rhct_cmo_node *cmo_node; + struct acpi_table_rhct *rhct; + u32 *hart_info_node_offset; + u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + + BUG_ON(acpi_disabled); + + if (!table) { + rhct = (struct acpi_table_rhct *)acpi_get_rhct(); + if (!rhct) + return -ENOENT; + } else { + rhct = (struct acpi_table_rhct *)table; + } + + end = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->header.length); + + for (node = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->node_offset); + node < end; + node = ACPI_ADD_PTR(struct acpi_rhct_node_header, node, node->length)) { + if (node->type == ACPI_RHCT_NODE_TYPE_HART_INFO) { + hart_info = ACPI_ADD_PTR(struct acpi_rhct_hart_info, node, size_hdr); + hart_info_node_offset = ACPI_ADD_PTR(u32, hart_info, size_hartinfo); + if (acpi_cpu_id != hart_info->uid) + continue; + + for (int i = 0; i < hart_info->num_offsets; i++) { + ref_node = ACPI_ADD_PTR(struct acpi_rhct_node_header, + rhct, hart_info_node_offset[i]); + if (ref_node->type == ACPI_RHCT_NODE_TYPE_CMO) { + cmo_node = ACPI_ADD_PTR(struct acpi_rhct_cmo_node, + ref_node, size_hdr); + if (cbom_size) + *cbom_size = 1 << cmo_node->cbom_size; + + if (cboz_size) + *cboz_size = 1 << cmo_node->cboz_size; + + if (cbop_size) + *cbop_size = 1 << cmo_node->cbop_size; + return 0; + } + } + } + } + + return -ENOENT; +} From patchwork Thu Aug 3 17:59:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1A47C04E69 for ; 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Thu, 03 Aug 2023 11:00:41 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.11.00.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 11:00:41 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 09/21] RISC-V: cacheflush: Initialize CBO variables on ACPI systems Date: Thu, 3 Aug 2023 23:29:04 +0530 Message-Id: <20230803175916.3174453-10-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Using new interface to get the CBO block size information in RHCT, initialize the variables on ACPI platforms. Signed-off-by: Sunil V L --- arch/riscv/mm/cacheflush.c | 37 +++++++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index fbc59b3f69f2..63bb56819b37 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -4,6 +4,8 @@ */ #include +#include +#include #include #ifdef CONFIG_SMP @@ -131,15 +133,38 @@ void __init riscv_init_cbo_blocksizes(void) unsigned long cbom_hartid, cboz_hartid; u32 cbom_block_size = 0, cboz_block_size = 0; struct device_node *node; + struct acpi_table_header *rhct; + acpi_status status; + unsigned int cpu; + + if (!acpi_disabled) { + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); + if (ACPI_FAILURE(status)) + return; + } - for_each_of_cpu_node(node) { - /* set block-size for cbom and/or cboz extension if available */ - cbo_get_block_size(node, "riscv,cbom-block-size", - &cbom_block_size, &cbom_hartid); - cbo_get_block_size(node, "riscv,cboz-block-size", - &cboz_block_size, &cboz_hartid); + for_each_possible_cpu(cpu) { + if (acpi_disabled) { + node = of_cpu_device_node_get(cpu); + if (!node) { + pr_warn("Unable to find cpu node\n"); + continue; + } + + /* set block-size for cbom and/or cboz extension if available */ + cbo_get_block_size(node, "riscv,cbom-block-size", + &cbom_block_size, &cbom_hartid); + cbo_get_block_size(node, "riscv,cboz-block-size", + &cboz_block_size, &cboz_hartid); + } else { + acpi_get_cbo_block_size(rhct, cpu, &cbom_block_size, + &cboz_block_size, NULL); + } } + if (!acpi_disabled && rhct) + acpi_put_table((struct acpi_table_header *)rhct); + if (cbom_block_size) riscv_cbom_block_size = cbom_block_size; From patchwork Thu Aug 3 17:59:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6797DEB64DD for ; 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Thu, 03 Aug 2023 11:00:48 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.11.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 11:00:48 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 10/21] clocksource/timer-riscv: ACPI: Add timer_cannot_wakeup_cpu Date: Thu, 3 Aug 2023 23:29:05 +0530 Message-Id: <20230803175916.3174453-11-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The timer capability to wakeup the cpu irrespective of its idle state is provided by the flag in RHCT. Update the timer code to set this flag. Signed-off-by: Sunil V L --- drivers/clocksource/timer-riscv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index da3071b387eb..50198657230e 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -212,6 +212,10 @@ TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); #ifdef CONFIG_ACPI static int __init riscv_timer_acpi_init(struct acpi_table_header *table) { + struct acpi_table_rhct *rhct = (struct acpi_table_rhct *)table; + + riscv_timer_cannot_wake_cpu = rhct->flags & ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU; + return riscv_timer_init_common(); } From patchwork Thu Aug 3 17:59:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F444C001DF for ; Thu, 3 Aug 2023 18:02:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230423AbjHCSCa (ORCPT ); Thu, 3 Aug 2023 14:02:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231235AbjHCSCA (ORCPT ); Thu, 3 Aug 2023 14:02:00 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CAEE4498 for ; Thu, 3 Aug 2023 11:01:12 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-686c06b806cso866686b3a.2 for ; Thu, 03 Aug 2023 11:01:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691085656; x=1691690456; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DyY105ZWYDcmAte3LXmkGWmEUp/pfY0rBCzPBKLc5no=; b=F2No1P8dCodOCJka5dx2xLrl5WcKTOqh0CqE9s2TUtqnLixlF6cr/AUvszgzy2TZTu IpgJ+dCrZugmZepjC/tpy4R5LQ7Pz00gUcQA/TtEMUWoSfT5/uFb1jKxDzT1ZQsqsZTd n/YxBVubsZMRX+XTZS1a6+twWBxpWIcvQgGZi10KPo9NwU+hLzYpn1k3UmbuJPr0c0iN /xxd/mndMDktQMKzqNFO4efMHpBh/HZI7YvgUVyIjmX6wmoATvY7iqn4QFz7f0d+cSG4 WzANehXdmfb0puBdKFejEfzCVDWLv6Eq7vxbamEiMtycsiO96UVNPeRmqmAhUEv2O88s z+Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691085656; x=1691690456; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DyY105ZWYDcmAte3LXmkGWmEUp/pfY0rBCzPBKLc5no=; b=GayzxUfeezC7EOftXzwIFpwrxPuJ13fTxUZmmchdUISTMOf/KuZuUlyPgwv1FuMSE0 pMWzZQUsqfoz52Pr4ZeK18gGEx+emh1yrLndXI4xZq8xhslWfZjGNp+Qv2VLdSDc1BbK srgFRpMHiNU1m79BcU8nNgo30hH6FA9Rr5TIBxgJKM93vqFaP6jqjGojBRXE3PnEZs7t O1aTJT9rrUvYhpgve4AWTlKEdbQd9r6vqakO9VC0YMjX9CthB3ynu5TAZJqcw7+3MFf/ nMhStyzKupLSUpj+LBPSN183qtSPpa1YpvcsBCUI5bx39/5FDgfXIrCHKZFAHx5JCdjq rkJQ== X-Gm-Message-State: ABy/qLYFKFXdJU2ht2950OFTpV2eV9cHwsAPLNSrjngDwj5G7MyHRc/R xz7MAbKqzIZPQEFswi8cvhyJZQ== X-Google-Smtp-Source: APBJJlF1KqR7PBmpd+0ur15adwkWpnUfiC6IMRYgAhf76Ujfi0pbNhhy0c6BhAYpNTIPaEB13Qkk0A== X-Received: by 2002:a05:6a00:1883:b0:666:b254:1c9c with SMTP id x3-20020a056a00188300b00666b2541c9cmr22057156pfh.27.1691085656078; Thu, 03 Aug 2023 11:00:56 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.11.00.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 11:00:55 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Anup Patel , Sunil V L Subject: [RFC PATCH v1 11/21] swnode: Add support to create early during boot Date: Thu, 3 Aug 2023 23:29:06 +0530 Message-Id: <20230803175916.3174453-12-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Anup Patel swnode framework can be used to create fwnode for interrupt controllers. This helps in keeping the drivers same for both DT and ACPI. To enable this, enhance the swnode framework so that it can be created early during boot without dependency on sysfs. Signed-off-by: Anup Patel Co-developed-by: Sunil V L Signed-off-by: Sunil V L --- drivers/base/swnode.c | 117 +++++++++++++++++++++++++++++++++------ include/linux/property.h | 3 + 2 files changed, 103 insertions(+), 17 deletions(-) diff --git a/drivers/base/swnode.c b/drivers/base/swnode.c index 1886995a0b3a..43f191a38980 100644 --- a/drivers/base/swnode.c +++ b/drivers/base/swnode.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "base.h" @@ -21,6 +22,7 @@ struct swnode { /* hierarchy */ struct ida child_ids; + struct list_head early; struct list_head entry; struct list_head children; struct swnode *parent; @@ -32,6 +34,9 @@ struct swnode { static DEFINE_IDA(swnode_root_ids); static struct kset *swnode_kset; +static DEFINE_SPINLOCK(swnode_early_lock); +static LIST_HEAD(swnode_early_list); + #define kobj_to_swnode(_kobj_) container_of(_kobj_, struct swnode, kobj) static const struct fwnode_operations software_node_ops; @@ -73,6 +78,17 @@ software_node_to_swnode(const struct software_node *node) if (!node) return NULL; + spin_lock(&swnode_early_lock); + + list_for_each_entry(swnode, &swnode_early_list, early) { + if (swnode->node == node) { + spin_unlock(&swnode_early_lock); + return swnode; + } + } + + spin_unlock(&swnode_early_lock); + spin_lock(&swnode_kset->list_lock); list_for_each_entry(k, &swnode_kset->list, entry) { @@ -698,6 +714,19 @@ software_node_find_by_name(const struct software_node *parent, const char *name) if (!name) return NULL; + spin_lock(&swnode_early_lock); + + list_for_each_entry(swnode, &swnode_early_list, early) { + if (parent == swnode->node->parent && swnode->node->name && + !strcmp(name, swnode->node->name)) { + kobject_get(&swnode->kobj); + spin_unlock(&swnode_early_lock); + return swnode->node; + } + } + + spin_unlock(&swnode_early_lock); + spin_lock(&swnode_kset->list_lock); list_for_each_entry(k, &swnode_kset->list, entry) { @@ -742,10 +771,16 @@ static void software_node_free(const struct software_node *node) kfree(node); } -static void software_node_release(struct kobject *kobj) +static void software_node_release_common(struct kobject *kobj, bool early) { struct swnode *swnode = kobj_to_swnode(kobj); + if (early) { + spin_lock(&swnode_early_lock); + list_del(&swnode->early); + spin_unlock(&swnode_early_lock); + } + if (swnode->parent) { ida_simple_remove(&swnode->parent->child_ids, swnode->id); list_del(&swnode->entry); @@ -760,6 +795,20 @@ static void software_node_release(struct kobject *kobj) kfree(swnode); } +static void software_node_release(struct kobject *kobj) +{ + software_node_release_common(kobj, false); +} + +static void software_node_release_early(struct kobject *kobj) +{ + software_node_release_common(kobj, true); +} + +static const struct kobj_type software_node_type_early = { + .release = software_node_release_early +}; + static const struct kobj_type software_node_type = { .release = software_node_release, .sysfs_ops = &kobj_sysfs_ops, @@ -767,7 +816,7 @@ static const struct kobj_type software_node_type = { static struct fwnode_handle * swnode_register(const struct software_node *node, struct swnode *parent, - unsigned int allocated) + unsigned int allocated, unsigned int early) { struct swnode *swnode; int ret; @@ -786,21 +835,39 @@ swnode_register(const struct software_node *node, struct swnode *parent, swnode->id = ret; swnode->node = node; swnode->parent = parent; - swnode->kobj.kset = swnode_kset; + swnode->kobj.kset = (!early) ? swnode_kset : NULL; fwnode_init(&swnode->fwnode, &software_node_ops); ida_init(&swnode->child_ids); + INIT_LIST_HEAD(&swnode->early); INIT_LIST_HEAD(&swnode->entry); INIT_LIST_HEAD(&swnode->children); - if (node->name) - ret = kobject_init_and_add(&swnode->kobj, &software_node_type, - parent ? &parent->kobj : NULL, - "%s", node->name); - else - ret = kobject_init_and_add(&swnode->kobj, &software_node_type, - parent ? &parent->kobj : NULL, - "node%d", swnode->id); + if (early) { + ret = 0; + kobject_init(&swnode->kobj, &software_node_type_early); + swnode->kobj.parent = parent ? &parent->kobj : NULL; + if (node->name) + ret = kobject_set_name(&swnode->kobj, + "%s", node->name); + else + ret = kobject_set_name(&swnode->kobj, + "node%d", swnode->id); + if (!ret) { + spin_lock(&swnode_early_lock); + list_add_tail(&swnode->early, &swnode_early_list); + spin_unlock(&swnode_early_lock); + } + } else { + if (node->name) + ret = kobject_init_and_add(&swnode->kobj, &software_node_type, + parent ? &parent->kobj : NULL, + "%s", node->name); + else + ret = kobject_init_and_add(&swnode->kobj, &software_node_type, + parent ? &parent->kobj : NULL, + "node%d", swnode->id); + } if (ret) { kobject_put(&swnode->kobj); return ERR_PTR(ret); @@ -815,7 +882,8 @@ swnode_register(const struct software_node *node, struct swnode *parent, if (parent) list_add_tail(&swnode->entry, &parent->children); - kobject_uevent(&swnode->kobj, KOBJ_ADD); + if (!early) + kobject_uevent(&swnode->kobj, KOBJ_ADD); return &swnode->fwnode; } @@ -892,7 +960,7 @@ int software_node_register(const struct software_node *node) if (node->parent && !parent) return -EINVAL; - return PTR_ERR_OR_ZERO(swnode_register(node, parent, 0)); + return PTR_ERR_OR_ZERO(swnode_register(node, parent, 0, 0)); } EXPORT_SYMBOL_GPL(software_node_register); @@ -910,9 +978,10 @@ void software_node_unregister(const struct software_node *node) } EXPORT_SYMBOL_GPL(software_node_unregister); -struct fwnode_handle * -fwnode_create_software_node(const struct property_entry *properties, - const struct fwnode_handle *parent) +static struct fwnode_handle * +fwnode_create_software_node_common(const struct property_entry *properties, + const struct fwnode_handle *parent, + bool early) { struct fwnode_handle *fwnode; struct software_node *node; @@ -931,12 +1000,26 @@ fwnode_create_software_node(const struct property_entry *properties, node->parent = p ? p->node : NULL; - fwnode = swnode_register(node, p, 1); + fwnode = swnode_register(node, p, 1, early); if (IS_ERR(fwnode)) software_node_free(node); return fwnode; } + +struct fwnode_handle * +fwnode_create_software_node_early(const struct property_entry *properties, + const struct fwnode_handle *parent) +{ + return fwnode_create_software_node_common(properties, parent, true); +} + +struct fwnode_handle * +fwnode_create_software_node(const struct property_entry *properties, + const struct fwnode_handle *parent) +{ + return fwnode_create_software_node_common(properties, parent, false); +} EXPORT_SYMBOL_GPL(fwnode_create_software_node); void fwnode_remove_software_node(struct fwnode_handle *fwnode) diff --git a/include/linux/property.h b/include/linux/property.h index 8c3c6685a2ae..7137338bfabb 100644 --- a/include/linux/property.h +++ b/include/linux/property.h @@ -503,6 +503,9 @@ void software_node_unregister_node_group(const struct software_node **node_group int software_node_register(const struct software_node *node); void software_node_unregister(const struct software_node *node); +struct fwnode_handle * +fwnode_create_software_node_early(const struct property_entry *properties, + const struct fwnode_handle *parent); struct fwnode_handle * fwnode_create_software_node(const struct property_entry *properties, const struct fwnode_handle *parent); From patchwork Thu Aug 3 17:59:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 621ADC001DF for ; Thu, 3 Aug 2023 18:02:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235492AbjHCSCj (ORCPT ); Thu, 3 Aug 2023 14:02:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231905AbjHCSCC (ORCPT ); Thu, 3 Aug 2023 14:02:02 -0400 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4068F44BA for ; Thu, 3 Aug 2023 11:01:15 -0700 (PDT) Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-686f38692b3so1120594b3a.2 for ; Thu, 03 Aug 2023 11:01:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691085663; x=1691690463; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Vqi3iZnSO0pCz4r86HvzjXAIoq/LUkNm+cOCoheLdcU=; b=RGBk6rx5Hg20bOXt+KLaRA26VcrOyNOoG/eZ7AxmlMnjFLn1DtSewmy8B6izdUW0E9 GsvBNf8e3jLCLs9h3DTaOaEA4Km0R9H4SNrQ9+L743IjhhgsHfGIylndzoIQZ265aQGL n3u5HhJfofcxpdy320nz2rQ2QoD01GiNeIZKOW51Fa3p9Z3xFqseEFfup54Xbr4HF94E 1EWqxSsfqSg9VtpcDRRRk5I1Neux3XeF5LvtGw6Xi2P1PAQzmkcPwAZHb9qGJ5o3kBoC gZ6YooLlmoRGD/mmS9270tnx8asDRFY2Qh6PHJuGg7a6wwcl70gJWrfxbZ1zW3Bv9Blq Sc+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691085663; x=1691690463; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vqi3iZnSO0pCz4r86HvzjXAIoq/LUkNm+cOCoheLdcU=; b=PF7uKoNwCPR6zjIMA13DVfXB944WyzfaHC1tFZ96lEz6sE4vFnkOUu/vfHjF7MPwbP HXAUwL9N24LleaIZh/HN/p7MMdAsztvj2MwrfRxH8zfBhgazOsQWKOfARh2k2zFEwZLh PkCmWAtrIOBvmyBTt3iqFF9FN183uEHTX0GNKyEU5Dq33rfYiNaFF54uCM5aXMH+QsVI J0YSo5o94cTAF3mxXbg1jiH/GTYKgKiKZuoYP9/zGUEiZmRLhhihgJfTmCwldfbZkiXf c0FS091pl8h7r+0aYmmhWHgyvClsbQTuw3LShdcsM5TdqFrk3/PFoH6aOsyu4ots/JQb Qk+A== X-Gm-Message-State: ABy/qLbbqpSKfZOYeEnrnPWMFtpky/Brs4S0SeP1CEMHYOT1+Qt3BYC/ 64/+VMIm2oD8nQ9q7/RpOX0LUg== X-Google-Smtp-Source: APBJJlFqOcYVb1YmYRN4MTpyz32muTvUlVIwXMvqlj269qOtTWbHmeKplda1rvUua7TwvFx4MZypxQ== X-Received: by 2002:a05:6a00:2351:b0:687:5c3f:d834 with SMTP id j17-20020a056a00235100b006875c3fd834mr8861510pfj.11.1691085663545; Thu, 03 Aug 2023 11:01:03 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.11.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 11:01:03 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 12/21] irqchip/riscv-intc: Use swnode framework to create fwnode Date: Thu, 3 Aug 2023 23:29:07 +0530 Message-Id: <20230803175916.3174453-13-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org By using swnode framework, all data from ACPI tables can be populated as properties of the swnode. This simplifies the driver code and removes the need for ACPI vs DT checks. Use this framework for RISC-V INTC driver. Signed-off-by: Sunil V L --- Documentation/riscv/acpi.rst | 21 +++++++++++++++ arch/riscv/include/asm/acpi.h | 1 + drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/irqchip.c | 46 ++++++++++++++++++++++++++++++++ drivers/irqchip/irq-riscv-intc.c | 12 ++++----- 5 files changed, 75 insertions(+), 7 deletions(-) create mode 100644 drivers/acpi/riscv/irqchip.c diff --git a/Documentation/riscv/acpi.rst b/Documentation/riscv/acpi.rst index 9870a282815b..e2406546bc16 100644 --- a/Documentation/riscv/acpi.rst +++ b/Documentation/riscv/acpi.rst @@ -8,3 +8,24 @@ The ISA string parsing rules for ACPI are defined by `Version ASCIIDOC Conversion, 12/2022 of the RISC-V specifications, as defined by tag "riscv-isa-release-1239329-2023-05-23" (commit 1239329 ) `_ + +Interrupt Controller Drivers +======= + +ACPI drivers for RISC-V interrupt controllers use software node framework to +create the fwnode for the interrupt controllers. Below properties are +additionally required for some firmware nodes apart from the properties +defined by the device tree bindings for these interrupt controllers. The +properties are created using the data in MADT table. + +1) RISC-V Interrupt Controller (INTC) +----------- +``hartid`` - Hart ID of the hart this interrupt controller belongs to. + +``riscv,imsic-addr`` - Physical base address of the Incoming MSI Controller +(IMSIC) MMIO region of this hart. + +``riscv,imsic-size`` - Size in bytes of the IMSIC MMIO region of this hart. + +``riscv,ext-intc-id`` - The unique ID of the external interrupts connected +to this hart. diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 0c4e8b35103e..0ac2df2dd194 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -68,6 +68,7 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; } int acpi_get_cbo_block_size(struct acpi_table_header *table, unsigned int cpu, u32 *cbom_size, u32 *cboz_size, u32 *cbop_size); +struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc); #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 8b3b126e0b94..8b664190d172 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y += rhct.o +obj-y += rhct.o irqchip.o diff --git a/drivers/acpi/riscv/irqchip.c b/drivers/acpi/riscv/irqchip.c new file mode 100644 index 000000000000..36f066a2cad5 --- /dev/null +++ b/drivers/acpi/riscv/irqchip.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#include +#include +#include +#include +#include + +struct riscv_irqchip_list { + struct fwnode_handle *fwnode; + struct list_head list; +}; + +LIST_HEAD(rintc_list); + +struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc) +{ + struct property_entry props[6] = {}; + struct fwnode_handle *fwnode; + struct riscv_irqchip_list *rintc_element; + + props[0] = PROPERTY_ENTRY_U64("hartid", rintc->hart_id); + props[1] = PROPERTY_ENTRY_U32("riscv,ext-intc-id", rintc->ext_intc_id); + props[2] = PROPERTY_ENTRY_U64("riscv,imsic-addr", rintc->imsic_addr); + props[3] = PROPERTY_ENTRY_U32("riscv,imsic-size", rintc->imsic_size); + props[4] = PROPERTY_ENTRY_U32("#interrupt-cells", 1); + + fwnode = fwnode_create_software_node_early(props, NULL); + if (fwnode) { + rintc_element = kzalloc(sizeof(*rintc_element), GFP_KERNEL); + if (!rintc_element) { + fwnode_remove_software_node(fwnode); + return NULL; + } + + rintc_element->fwnode = fwnode; + list_add_tail(&rintc_element->list, &rintc_list); + } + + return fwnode; +} diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 1a0fc87152c5..1ef9cada1ed3 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -203,6 +203,12 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, rintc = (struct acpi_madt_rintc *)header; + fn = acpi_rintc_create_irqchip_fwnode(rintc); + if (!fn) { + pr_err("unable to create INTC FW node\n"); + return -ENOMEM; + } + /* * The ACPI MADT will have one INTC for each CPU (or HART) * so riscv_intc_acpi_init() function will be called once @@ -212,12 +218,6 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, if (riscv_hartid_to_cpuid(rintc->hart_id) != smp_processor_id()) return 0; - fn = irq_domain_alloc_named_fwnode("RISCV-INTC"); - if (!fn) { - pr_err("unable to allocate INTC FW node\n"); - return -ENOMEM; - } - return riscv_intc_init_common(fn); } From patchwork Thu Aug 3 17:59:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6623EB64DD for ; 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Thu, 03 Aug 2023 11:01:10 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.11.01.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 11:01:10 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 13/21] irqchip/riscv-imsic-early: Add ACPI support Date: Thu, 3 Aug 2023 23:29:08 +0530 Message-Id: <20230803175916.3174453-14-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to probe the IMSIC early driver on ACPI based RISC-V platforms. Signed-off-by: Sunil V L --- arch/riscv/include/asm/acpi.h | 6 +++ drivers/acpi/riscv/irqchip.c | 57 +++++++++++++++++++++++++ drivers/irqchip/irq-riscv-imsic-early.c | 28 ++++++++++++ drivers/irqchip/irq-riscv-imsic-state.c | 33 +++++++++++--- 4 files changed, 119 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 0ac2df2dd194..6dde3d63dc0e 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -69,6 +69,8 @@ static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; } int acpi_get_cbo_block_size(struct acpi_table_header *table, unsigned int cpu, u32 *cbom_size, u32 *cboz_size, u32 *cbop_size); struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc); +struct fwnode_handle *acpi_imsic_create_fwnode(struct acpi_madt_imsic *imsic); +struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev); #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) @@ -89,6 +91,10 @@ static inline int acpi_get_cbo_block_size(struct acpi_table_header *table, return -EINVAL; } +static inline struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev) +{ + return NULL; +} #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/drivers/acpi/riscv/irqchip.c b/drivers/acpi/riscv/irqchip.c index 36f066a2cad5..6e15d45cb229 100644 --- a/drivers/acpi/riscv/irqchip.c +++ b/drivers/acpi/riscv/irqchip.c @@ -18,6 +18,8 @@ struct riscv_irqchip_list { LIST_HEAD(rintc_list); +static struct fwnode_handle *imsic_acpi_fwnode; + struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc) { struct property_entry props[6] = {}; @@ -44,3 +46,58 @@ struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *r return fwnode; } + +static struct fwnode_handle *acpi_imsic_get_rintc_fwnode(u32 idx) +{ + struct riscv_irqchip_list *rintc_element; + struct fwnode_handle *fwnode; + struct list_head *i, *tmp; + unsigned int j = 0; + + list_for_each_safe(i, tmp, &rintc_list) { + rintc_element = list_entry(i, struct riscv_irqchip_list, list); + fwnode = rintc_element->fwnode; + + if (j == idx) + return fwnode; + + j++; + } + + return NULL; +} + +struct fwnode_handle *acpi_imsic_create_fwnode(struct acpi_madt_imsic *imsic) +{ + struct property_entry props[8] = {}; + struct software_node_ref_args *refs; + struct fwnode_handle *parent_fwnode; + unsigned int nr_rintc, i; + + props[0] = PROPERTY_ENTRY_U32("riscv,guest-index-bits", imsic->guest_index_bits); + props[1] = PROPERTY_ENTRY_U32("riscv,hart-index-bits", imsic->hart_index_bits); + props[2] = PROPERTY_ENTRY_U32("riscv,group-index-bits", imsic->group_index_bits); + props[3] = PROPERTY_ENTRY_U32("riscv,group-index-shift", imsic->group_index_shift); + props[4] = PROPERTY_ENTRY_U32("riscv,num-ids", imsic->num_ids); + props[5] = PROPERTY_ENTRY_U32("riscv,num-guest-ids", imsic->num_guest_ids); + + nr_rintc = list_count_nodes(&rintc_list); + refs = kcalloc(nr_rintc, sizeof(*refs), GFP_KERNEL); + if (!refs) + return NULL; + + for (i = 0; i < nr_rintc; i++) { + parent_fwnode = acpi_imsic_get_rintc_fwnode(i); + refs[i] = SOFTWARE_NODE_REFERENCE(to_software_node(parent_fwnode), RV_IRQ_EXT); + } + props[6] = PROPERTY_ENTRY_REF_ARRAY_LEN("interrupts-extended", refs, nr_rintc); + + imsic_acpi_fwnode = fwnode_create_software_node_early(props, NULL); + + return imsic_acpi_fwnode; +} + +struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev) +{ + return imsic_acpi_fwnode; +} diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c index 1de89ce1ec2f..93f4d748ca6d 100644 --- a/drivers/irqchip/irq-riscv-imsic-early.c +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -256,3 +257,30 @@ static int __init imsic_early_dt_init(struct device_node *node, return 0; } IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_early_dt_init); + +#ifdef CONFIG_ACPI +static int __init imsic_early_acpi_init(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct fwnode_handle *fwnode; + int rc; + + /* + * There should be only one IMSIC node. + */ + fwnode = acpi_imsic_create_fwnode((struct acpi_madt_imsic *)header); + if (!fwnode) { + pr_err("unable to create IMSIC FW node\n"); + return -ENOMEM; + } + + rc = imsic_early_probe(fwnode); + if (!rc) + pci_msi_register_fwnode_provider(&acpi_riscv_get_msi_fwnode); + + return rc; +} + +IRQCHIP_ACPI_DECLARE(riscv_imsic, ACPI_MADT_TYPE_IMSIC, + NULL, 1, imsic_early_acpi_init); +#endif diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c index 412b5b919dcc..d0e09e51e8ae 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -225,15 +225,38 @@ static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode, return riscv_get_intc_hartid(parent.fwnode, hartid); } +static int __init imsic_acpi_get_mmio_resource(struct fwnode_handle *fwnode, + u32 index, struct resource *res) +{ + int rc; + struct fwnode_reference_args parent; + u64 base; + u32 size; + + rc = fwnode_property_get_reference_args(fwnode, + "interrupts-extended", NULL, + 0, index, &parent); + if (rc) + return rc; + + rc = fwnode_property_read_u64_array(parent.fwnode, "riscv,imsic-addr", + &base, 1); + rc = fwnode_property_read_u32_array(parent.fwnode, "riscv,imsic-size", + &size, 1); + if (!rc) { + res->start = base; + res->end = res->start + size - 1; + } + + return 0; +} + static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, u32 index, struct resource *res) { - /* - * Currently, only OF fwnode is support so extend this function - * for other types of fwnode for ACPI support. - */ if (!is_of_node(fwnode)) - return -EINVAL; + return imsic_acpi_get_mmio_resource(fwnode, index, res); + return of_address_to_resource(to_of_node(fwnode), index, res); } From patchwork Thu Aug 3 17:59:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340450 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C518C41513 for ; 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Thu, 03 Aug 2023 11:01:18 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.11.01.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 11:01:18 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 14/21] ACPI: bus: Add acpi_riscv_init function Date: Thu, 3 Aug 2023 23:29:09 +0530 Message-Id: <20230803175916.3174453-15-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add a new function for RISC-V to do any architecture specific initialization. This function will be used to create platform devices like APLIC, IMSIC MSI controller, RISC-V IOMMU etc. Signed-off-by: Sunil V L --- drivers/acpi/bus.c | 1 + drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/init.c | 12 ++++++++++++ include/linux/acpi.h | 6 ++++++ 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 drivers/acpi/riscv/init.c diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 2fc2b43a4ed3..9a8c16170a4b 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -1388,6 +1388,7 @@ static int __init acpi_init(void) pci_mmcfg_late_init(); acpi_arm_init(); + acpi_riscv_init(); acpi_viot_early_init(); acpi_hest_init(); acpi_ghes_init(); diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 8b664190d172..3433a19c421d 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y += rhct.o irqchip.o +obj-y += rhct.o irqchip.o init.o diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c new file mode 100644 index 000000000000..b5807bbdb171 --- /dev/null +++ b/drivers/acpi/riscv/init.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#include + +void __init acpi_riscv_init(void) +{ +} diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 641dc4843987..d16739928888 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1511,6 +1511,12 @@ void acpi_arm_init(void); static inline void acpi_arm_init(void) { } #endif +#ifdef CONFIG_RISCV +void acpi_riscv_init(void); +#else +static inline void acpi_riscv_init(void) { } +#endif + #ifdef CONFIG_ACPI_PCC void acpi_init_pcc(void); #else From patchwork Thu Aug 3 17:59:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D74D4C04FE1 for ; Thu, 3 Aug 2023 18:03:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232575AbjHCSDR (ORCPT ); Thu, 3 Aug 2023 14:03:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235065AbjHCSCU (ORCPT ); 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Thu, 03 Aug 2023 11:01:26 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 15/21] ACPI: RISC-V: Create IMSIC platform device Date: Thu, 3 Aug 2023 23:29:10 +0530 Message-Id: <20230803175916.3174453-16-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The MSI controller functionality of the RISC-V IMSIC is probed as a platform device by the driver. So, create the IMSIC platform device if the IMSIC was discovered in MADT during early IMSIC driver probe. Signed-off-by: Sunil V L --- drivers/acpi/riscv/init.c | 2 ++ drivers/acpi/riscv/init.h | 4 ++++ drivers/acpi/riscv/irqchip.c | 23 +++++++++++++++++++++++ 3 files changed, 29 insertions(+) create mode 100644 drivers/acpi/riscv/init.h diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index b5807bbdb171..be61c08ea385 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -6,7 +6,9 @@ */ #include +#include "init.h" void __init acpi_riscv_init(void) { + riscv_acpi_imsic_platform_init(); } diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h new file mode 100644 index 000000000000..a2f72bb294d3 --- /dev/null +++ b/drivers/acpi/riscv/init.h @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +void __init riscv_acpi_imsic_platform_init(void); diff --git a/drivers/acpi/riscv/irqchip.c b/drivers/acpi/riscv/irqchip.c index 6e15d45cb229..ca96bf109cf7 100644 --- a/drivers/acpi/riscv/irqchip.c +++ b/drivers/acpi/riscv/irqchip.c @@ -9,7 +9,10 @@ #include #include #include +#include +#include #include +#include "../../../drivers/pci/pci.h" struct riscv_irqchip_list { struct fwnode_handle *fwnode; @@ -101,3 +104,23 @@ struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev) { return imsic_acpi_fwnode; } + +void __init riscv_acpi_imsic_platform_init(void) +{ + struct platform_device *pdev; + int ret; + + if (!acpi_riscv_get_msi_fwnode(NULL)) { + pci_no_msi(); + return; + } + + pdev = platform_device_alloc("riscv-imsic", 0); + if (!pdev) + return; + + pdev->dev.fwnode = acpi_riscv_get_msi_fwnode(NULL); + ret = platform_device_add(pdev); + if (ret) + platform_device_put(pdev); +} From patchwork Thu Aug 3 17:59:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340452 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E830EB64DD for ; Thu, 3 Aug 2023 18:03:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233096AbjHCSDS (ORCPT ); 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Thu, 03 Aug 2023 11:01:33 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 16/21] ACPI: Add APLIC IRQ model for RISC-V Date: Thu, 3 Aug 2023 23:29:11 +0530 Message-Id: <20230803175916.3174453-17-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add the IRQ model for RISC-V APLIC so that acpi_set_irq_model can use this for RISC-V. Signed-off-by: Sunil V L --- drivers/acpi/bus.c | 3 +++ include/linux/acpi.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 9a8c16170a4b..dd9d80630bf6 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -1132,6 +1132,9 @@ static int __init acpi_bus_init_irq(void) case ACPI_IRQ_MODEL_LPIC: message = "LPIC"; break; + case ACPI_IRQ_MODEL_APLIC: + message = "APLIC"; + break; default: pr_info("Unknown interrupt routing model\n"); return -ENODEV; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index d16739928888..698d120a1bd2 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -95,6 +95,7 @@ enum acpi_irq_model_id { ACPI_IRQ_MODEL_PLATFORM, ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_LPIC, + ACPI_IRQ_MODEL_APLIC, ACPI_IRQ_MODEL_COUNT }; From patchwork Thu Aug 3 17:59:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50DA2C001DB for ; Thu, 3 Aug 2023 18:03:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232585AbjHCSDg (ORCPT ); Thu, 3 Aug 2023 14:03:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235645AbjHCSDE (ORCPT ); Thu, 3 Aug 2023 14:03:04 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D32F64220 for ; Thu, 3 Aug 2023 11:01:50 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-686d8c8fc65so915107b3a.0 for ; Thu, 03 Aug 2023 11:01:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691085702; x=1691690502; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MqlDPHKEWaBxTYs/0M8htriIKOWDT6nuJRMhsrHXzuE=; b=Mck7EqqRTTHdMEBXbHLoZwfOLdXJUnVodFv/es6odb8/Qq21nUhzlxmcrCQpHegUV1 qKWa65jRjHgYqT8ANyBw+GVASKqCOwBtVtvNwTQ9NuaGjcZ06UVpzTbD4zoHTAFAiZAq bC+kKVzDGdpGns7pLFPMO4CYn2tXf14kK4mXYgydh1+8YK5+ZpXO+dgkvzgwmGncgRDC EBqiRVaPJMAiim+QopcXM5/33h+EYYtGMCn9nVz286lZO7qUY51KfF5NwHxIJsTOYCRL nNpgZRPcRYp3J92EJNQFHRsHz+vYpZwdP4h6z60CpUAwZ3rmeewQu9jN+Ugw4weQY+0J wUTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691085702; x=1691690502; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MqlDPHKEWaBxTYs/0M8htriIKOWDT6nuJRMhsrHXzuE=; b=SkNAXirfOdyeGfwtAjLRmIoPdb6OeIsWM7S48qvbgPb78kdO8aWd7f/N7Pptx8sdZY a/dMl8v7X9FyNpBjYyEUv7pEBW9w6g7oh8WIv/uP4CZtV+7sw3g3a+Bw8q0GT3oEF/Wh jRItCpWPAh/R8k2Q1o7zFdRbb6qch4UKNz4m2NYlWV8VpOL7ypadvYKQL5rYokhyee4g 9G6H2klHmaSQV06FzQA1tRZl8QXNwewYtFmKyH7COZVgPjq9CJM7wsysku0L1p0X1qEf P2EjqUu6dejHoze7DtCu3psTCjs9QI9aqv7s5Hq05852k9CHgeIjrLjYCtkmMtBprcAM A2Yg== X-Gm-Message-State: ABy/qLbyNXaHSzLDl6mT4s95KCmudL+PjnnKiKJmeEccHfsW6GwopLLP +qSon8Pfqg8u9A9Etk92P7j0wA== X-Google-Smtp-Source: APBJJlEpOrcULPp+uHqf2SkiWQTzFmTJeS1yI+fASG26f/nZjZ0ASal13fAyFeapUfbB4CtpRCGyhA== X-Received: by 2002:a05:6a21:3b44:b0:130:9638:36d4 with SMTP id zy4-20020a056a213b4400b00130963836d4mr15110479pzb.33.1691085701012; Thu, 03 Aug 2023 11:01:41 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.11.01.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 11:01:40 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 17/21] ACPI: RISC-V: Create APLIC platform device Date: Thu, 3 Aug 2023 23:29:12 +0530 Message-Id: <20230803175916.3174453-18-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Since APLIC needs to be a platform device, probe the MADT and create platform devices for each APLIC in the system. Use software node framework for the fwnode which allows to create properties and hence the actual irqchip driver doesn't need to do anything different for ACPI vs DT. Signed-off-by: Sunil V L --- Documentation/riscv/acpi.rst | 6 ++ drivers/acpi/riscv/init.c | 1 + drivers/acpi/riscv/init.h | 1 + drivers/acpi/riscv/irqchip.c | 183 +++++++++++++++++++++++++++++++++++ 4 files changed, 191 insertions(+) diff --git a/Documentation/riscv/acpi.rst b/Documentation/riscv/acpi.rst index e2406546bc16..9ea9008288ea 100644 --- a/Documentation/riscv/acpi.rst +++ b/Documentation/riscv/acpi.rst @@ -29,3 +29,9 @@ properties are created using the data in MADT table. ``riscv,ext-intc-id`` - The unique ID of the external interrupts connected to this hart. + +2) RISC-V Advanced Platform Level Interrupt Controller (APLIC) +----------- + +``riscv,gsi-base`` - The global system interrupt number where this APLIC’s +interrupt inputs start. diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index be61c08ea385..ee747211174f 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -11,4 +11,5 @@ void __init acpi_riscv_init(void) { riscv_acpi_imsic_platform_init(); + riscv_acpi_aplic_platform_init(); } diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h index a2f72bb294d3..17bcf0baaadb 100644 --- a/drivers/acpi/riscv/init.h +++ b/drivers/acpi/riscv/init.h @@ -2,3 +2,4 @@ #include void __init riscv_acpi_imsic_platform_init(void); +void __init riscv_acpi_aplic_platform_init(void); diff --git a/drivers/acpi/riscv/irqchip.c b/drivers/acpi/riscv/irqchip.c index ca96bf109cf7..7fb7befdb303 100644 --- a/drivers/acpi/riscv/irqchip.c +++ b/drivers/acpi/riscv/irqchip.c @@ -23,6 +23,8 @@ LIST_HEAD(rintc_list); static struct fwnode_handle *imsic_acpi_fwnode; +LIST_HEAD(aplic_list); + struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc) { struct property_entry props[6] = {}; @@ -124,3 +126,184 @@ void __init riscv_acpi_imsic_platform_init(void) if (ret) platform_device_put(pdev); } + +/* + * The ext_intc_id format is as follows: + * Bits [31:24] APLIC/PLIC ID + * Bits [15:0] APLIC IDC ID / PLIC S-Mode Context ID for this hart + */ +#define APLIC_PLIC_ID(x) ((x) >> 24) +#define IDC_CONTEXT_ID(x) ((x) & 0x0000ffff) + +static struct fwnode_handle *acpi_ext_intc_get_rintc_fwnode(u8 aplic_plic_id, u16 index) +{ + struct riscv_irqchip_list *rintc_element; + struct fwnode_handle *fwnode; + struct list_head *i, *tmp; + u32 id; + int rc; + + list_for_each_safe(i, tmp, &rintc_list) { + rintc_element = list_entry(i, struct riscv_irqchip_list, list); + fwnode = rintc_element->fwnode; + rc = fwnode_property_read_u32_array(fwnode, "riscv,ext-intc-id", &id, 1); + if (rc) + continue; + + if ((APLIC_PLIC_ID(id) == aplic_plic_id) && (IDC_CONTEXT_ID(id) == index)) + return fwnode; + } + + return NULL; +} + +static struct fwnode_handle *acpi_aplic_create_fwnode(struct acpi_madt_aplic *aplic) +{ + struct fwnode_handle *fwnode, *parent_fwnode; + struct riscv_irqchip_list *aplic_element; + struct software_node_ref_args *refs; + struct property_entry props[8] = {}; + unsigned int i; + + props[0] = PROPERTY_ENTRY_U32("riscv,gsi-base", aplic->gsi_base); + props[1] = PROPERTY_ENTRY_U32("riscv,num-sources", aplic->num_sources); + props[2] = PROPERTY_ENTRY_U32("riscv,num-idcs", aplic->num_idcs); + props[3] = PROPERTY_ENTRY_U32("riscv,aplic-id", aplic->id); + props[4] = PROPERTY_ENTRY_U64("riscv,aplic-base", aplic->base_addr); + props[5] = PROPERTY_ENTRY_U32("riscv,aplic-size", aplic->size); + if (aplic->num_idcs) { + refs = kcalloc(aplic->num_idcs, sizeof(*refs), GFP_KERNEL); + if (!refs) + return NULL; + + for (i = 0; i < aplic->num_idcs; i++) { + parent_fwnode = acpi_ext_intc_get_rintc_fwnode(aplic->id, i); + refs[i] = SOFTWARE_NODE_REFERENCE(to_software_node(parent_fwnode), + RV_IRQ_EXT); + } + props[6] = PROPERTY_ENTRY_REF_ARRAY_LEN("interrupts-extended", + refs, aplic->num_idcs); + } else { + props[6] = PROPERTY_ENTRY_BOOL("msi-parent"); + } + + fwnode = fwnode_create_software_node_early(props, NULL); + + if (fwnode) { + aplic_element = kzalloc(sizeof(*aplic_element), GFP_KERNEL); + if (!aplic_element) { + fwnode_remove_software_node(fwnode); + return NULL; + } + + aplic_element->fwnode = fwnode; + list_add_tail(&aplic_element->list, &aplic_list); + } + + return fwnode; +} + +static struct fwnode_handle *aplic_get_gsi_domain_id(u32 gsi) +{ + struct riscv_irqchip_list *aplic_element; + struct fwnode_handle *fwnode; + struct list_head *i, *tmp; + u32 gsi_base; + u32 nr_irqs; + int rc; + + list_for_each_safe(i, tmp, &aplic_list) { + aplic_element = list_entry(i, struct riscv_irqchip_list, list); + fwnode = aplic_element->fwnode; + rc = fwnode_property_read_u32_array(fwnode, "riscv,gsi-base", &gsi_base, 1); + if (!rc) { + rc = fwnode_property_read_u32_array(fwnode, "riscv,num-sources", + &nr_irqs, 1); + if (!rc && (gsi >= gsi_base && gsi < gsi_base + nr_irqs)) + return fwnode; + } + } + + return NULL; +} + +static u32 __init aplic_gsi_to_irq(u32 gsi) +{ + return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH); +} + +static int __init aplic_create_platform_device(struct fwnode_handle *fwnode) +{ + struct platform_device *pdev; + u32 aplic_size, aplic_id; + struct resource *res; + u64 aplic_base; + int ret; + + if (!fwnode) + return -ENODEV; + + ret = fwnode_property_read_u64_array(fwnode, "riscv,aplic-base", &aplic_base, 1); + if (ret) + return -ENODEV; + + ret = fwnode_property_read_u32_array(fwnode, "riscv,aplic-size", &aplic_size, 1); + if (ret) + return -ENODEV; + + ret = fwnode_property_read_u32_array(fwnode, "riscv,aplic-id", &aplic_id, 1); + if (ret) + return -ENODEV; + + pdev = platform_device_alloc("riscv-aplic", aplic_id); + if (!pdev) + return -ENOMEM; + + res = kcalloc(1, sizeof(*res), GFP_KERNEL); + if (!res) { + ret = -ENOMEM; + goto dev_put; + } + + res->start = aplic_base; + res->end = res->start + aplic_size - 1; + res->flags = IORESOURCE_MEM; + ret = platform_device_add_resources(pdev, res, 1); + /* + * Resources are duplicated in platform_device_add_resources, + * free their allocated memory + */ + kfree(res); + + pdev->dev.fwnode = fwnode; + ret = platform_device_add(pdev); + if (ret) + goto dev_put; + + return 0; + +dev_put: + platform_device_put(pdev); + return ret; +} + +static int __init aplic_parse_madt(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_aplic *aplic = (struct acpi_madt_aplic *)header; + struct fwnode_handle *fwnode; + + fwnode = acpi_aplic_create_fwnode(aplic); + if (fwnode) + aplic_create_platform_device(fwnode); + + return 0; +} + +void __init riscv_acpi_aplic_platform_init(void) +{ + if (acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, aplic_parse_madt, 0) > 0) { + acpi_set_irq_model(ACPI_IRQ_MODEL_APLIC, aplic_get_gsi_domain_id); + acpi_set_gsi_to_irq_fallback(aplic_gsi_to_irq); + } +} From patchwork Thu Aug 3 17:59:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340454 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86436C41513 for ; Thu, 3 Aug 2023 18:03:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235203AbjHCSDq (ORCPT ); Thu, 3 Aug 2023 14:03:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235712AbjHCSDL (ORCPT ); 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Thu, 03 Aug 2023 11:01:48 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 18/21] irqchip/irq-riscv-aplic-msi: Add ACPI support Date: Thu, 3 Aug 2023 23:29:13 +0530 Message-Id: <20230803175916.3174453-19-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Search and configure the MSI domain for the APLIC on ACPI based systems. Signed-off-by: Sunil V L --- drivers/irqchip/irq-riscv-aplic-msi.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-riscv-aplic-msi.c b/drivers/irqchip/irq-riscv-aplic-msi.c index 086d00e0429e..1948444c9e0c 100644 --- a/drivers/irqchip/irq-riscv-aplic-msi.c +++ b/drivers/irqchip/irq-riscv-aplic-msi.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "irq-riscv-aplic-main.h" @@ -178,6 +179,8 @@ static void aplic_msi_write_msg(struct msi_desc *desc, struct msi_msg *msg) int aplic_msi_setup(struct device *dev, void __iomem *regs) { const struct imsic_global_config *imsic_global; + struct irq_domain *msi_domain = NULL; + struct fwnode_handle *msi_fwnode; struct irq_domain *irqdomain; struct aplic_priv *priv; struct aplic_msicfg *mc; @@ -261,8 +264,17 @@ int aplic_msi_setup(struct device *dev, void __iomem *regs) * IMSIC and the IMSIC MSI domains are created later through * the platform driver probing so we set it explicitly here. */ - if (is_of_node(dev->fwnode)) + if (is_of_node(dev->fwnode)) { of_msi_configure(dev, to_of_node(dev->fwnode)); + } else { + msi_fwnode = acpi_riscv_get_msi_fwnode(dev); + if (msi_fwnode) + msi_domain = irq_find_matching_fwnode(msi_fwnode, + DOMAIN_BUS_PLATFORM_MSI); + + if (msi_domain) + dev_set_msi_domain(dev, msi_domain); + } } /* Create irq domain instance for the APLIC MSI-mode */ From patchwork Thu Aug 3 17:59:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2054BEB64DD for ; Thu, 3 Aug 2023 18:03:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235344AbjHCSD5 (ORCPT ); Thu, 3 Aug 2023 14:03:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235751AbjHCSDN (ORCPT ); Thu, 3 Aug 2023 14:03:13 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 040384231 for ; Thu, 3 Aug 2023 11:02:05 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-6873a30d02eso866550b3a.3 for ; Thu, 03 Aug 2023 11:02:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691085716; x=1691690516; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oa5JuUdn7+qjYPf/m5YirkX0l5WPw2pxjpAQ3vHoF5I=; b=KQbJbLeA4TGtIxIuFW6WC8NJApS9TUoRPunkwh/7C0r1L0sLBDwJGs8OUTxRfQN8yL IZgS1FD+/A7me33MFHYJD0l0yTtrtfiDYXF3e8iNfPm93ITz3TvFfxLpZrkvFjfajmGf EMdRXrFFA3X7X7YRRnEWo+UPpR2JQ9GgdKaKpv9xyaKOqY2AwIvxxCCF7PewHi3Faua6 jFe8/UkDo4eFfqQ4KvSjqlO/i1RJALvToWFdrastu4Qw7KsNlgXKVspIMSkXJgK5IbJo eJSEBF9ZP7B5NkjyH0BsRNEDtOJgtdIONOGak2Or0tgEW0/gVlXNtRRwCRBHdYyNBhLJ 6pIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691085716; x=1691690516; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oa5JuUdn7+qjYPf/m5YirkX0l5WPw2pxjpAQ3vHoF5I=; b=RoLToI8qGFg3r4x/Crz9bOPBOhM1ro6r618ZDuL2gC4lZPhrXJGUtxsEzNSBJrVsfk leAJS4y0PyIC+xkAduvw8vXqMxxor7aNsmiZVzJepUELuxsatEsklqt6S9w3JqH1otnx bYGzEyv+k4z/TgcdW0GPDHkuWBoRjRyWrWD6m31833b2vuauwIjrjINzNhn/hzQFZAn9 ASgGbGB6H+dq2uE5AjlUmuMtzToUcihEgYpnUWjUXDmWnqe8zmu32QoHueGl3QM8UpRa UCoMJiFx1flGdoyQp5njUEJqh0hgGzLcYhGqifbGdF9P9smJYF46x2pFkcEnZVn+JkT5 6sKA== X-Gm-Message-State: ABy/qLYPLx9z2h8BotX3DK14Ka3gyzEUzhRdfBWBAl8v8Nehy2n/mGe5 n+CncVHrOxpbRkQM+ri/svrm7g== X-Google-Smtp-Source: APBJJlEdZK4VF6uWpmNFHink+0Aa6EYjLEIulHdNF+NehNeb7SxIQC3cwBrCreK5H/j8S4RNIEykOQ== X-Received: by 2002:a05:6a20:191:b0:12f:c61e:7cac with SMTP id 17-20020a056a20019100b0012fc61e7cacmr16449922pzy.31.1691085716659; Thu, 03 Aug 2023 11:01:56 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.11.01.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 11:01:56 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 19/21] ACPI: bus: Add PLIC IRQ model Date: Thu, 3 Aug 2023 23:29:14 +0530 Message-Id: <20230803175916.3174453-20-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add the IRQ model for RISC-V PLIC so that acpi_set_irq_model can use this for RISC-V. Signed-off-by: Haibo Xu Signed-off-by: Sunil V L --- drivers/acpi/bus.c | 3 +++ include/linux/acpi.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index dd9d80630bf6..68b8d38ec48a 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -1135,6 +1135,9 @@ static int __init acpi_bus_init_irq(void) case ACPI_IRQ_MODEL_APLIC: message = "APLIC"; break; + case ACPI_IRQ_MODEL_PLIC: + message = "PLIC"; + break; default: pr_info("Unknown interrupt routing model\n"); return -ENODEV; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 698d120a1bd2..31f080df179d 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -96,6 +96,7 @@ enum acpi_irq_model_id { ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_LPIC, ACPI_IRQ_MODEL_APLIC, + ACPI_IRQ_MODEL_PLIC, ACPI_IRQ_MODEL_COUNT }; From patchwork Thu Aug 3 17:59:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340456 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE94AC001DF for ; Thu, 3 Aug 2023 18:04:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230327AbjHCSEH (ORCPT ); Thu, 3 Aug 2023 14:04:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230163AbjHCSDQ (ORCPT ); Thu, 3 Aug 2023 14:03:16 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6849A49C5 for ; Thu, 3 Aug 2023 11:02:10 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-686ba29ccb1so869752b3a.1 for ; Thu, 03 Aug 2023 11:02:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691085724; x=1691690524; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4+Q8KfNrcpLCQ+Zm4Z9cXmSMTUQ/Cx2NE3GzYzgbHwU=; b=TWzDXrq5rkDXP54lt1KXIhB7yRYTfDMnjicYqveI1Fv/QGFp5xa1yM7dqucAsYbXYH htp+oGPiIC+rC4eCLBCyGmtdcF8p3+QFwFxMOgrtdUFz6o4LbGtNAZWGo0DpXwodLlTq ZKvGdwZtZf2BXqFokABG7lCPfApf0Y8vwZUy+Ee1WBFXJUNK5UGwZsuE5I2KobJ3fI8x 4ByezcpRBxt/a5trnhAacwlm3z1zVcLLfLn4VmW4p4mQ7CmLjEqbX6UzsGsZGFCuov1G RnAKm5FwFaUNNZTLqCG57ZrMHp/PjpulrpD8pmQ6sDJDUl2BfiR0RJb7qyVpPYWSy8SY h7ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691085724; x=1691690524; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4+Q8KfNrcpLCQ+Zm4Z9cXmSMTUQ/Cx2NE3GzYzgbHwU=; b=l3c3gIa+RINACUl1JE92qV3SIm3Bm+E3fd56sYkGp5ZJfkFgBjSo5MkcZDsGsyXmdk IAXS5HZ0p5HShyvJGUfZRwrGQ80msjjQRU6R9QEhLA+WBd6oi7eoj4YOoGMSrAGCc3vM np8vnNGMwz/6jV7ikdQL21CWs9USlY/1V9hJbId3bJ38TEdBiXZ9HJFDbg0FCIDhofFr YFM7pN40EN3Vr+Izmx+ffsfrjJZUEAsvYLrkV6cTHXdp94NJQXzlVsWZypEsjWh/Be0/ aMxS63tBzZ8WwlHtoc4eF9+2VP1ITQ3RBcOyAhqgteml12x3H+PWQlblxCetSx97xR1i W4ew== X-Gm-Message-State: ABy/qLam6WXWAhRpRKMWsjwfl9FiOntcFGePabrhhT51Msi8DKeQYUt6 ZCMdnv5VVLc2gutJR02Y+0oRxQ== X-Google-Smtp-Source: APBJJlH/rurRin9y29M3aaOJtb8cTFXCf64b42mFfS4paTtxGXHirLrg+/10tPI3KDoH92gXeSNR0A== X-Received: by 2002:a05:6a00:2286:b0:687:570c:da2d with SMTP id f6-20020a056a00228600b00687570cda2dmr10882734pfe.12.1691085723889; Thu, 03 Aug 2023 11:02:03 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.11.01.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 11:02:03 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 20/21] RISC-V: ACPI: Create PLIC platform device Date: Thu, 3 Aug 2023 23:29:15 +0530 Message-Id: <20230803175916.3174453-21-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Since PLIC needs to be a platform device, probe the MADT and create platform devices for each PLIC in the system. Use software node framework for the fwnode which allows to create properties and hence the actual irqchip driver doesn't need to do anything different for ACPI vs DT. Signed-off-by: Sunil V L Co-developed-by: Haibo Xu Signed-off-by: Haibo Xu --- Documentation/riscv/acpi.rst | 6 ++ arch/riscv/include/asm/acpi.h | 3 + drivers/acpi/riscv/init.c | 1 + drivers/acpi/riscv/init.h | 1 + drivers/acpi/riscv/irqchip.c | 198 ++++++++++++++++++++++++++++++++++ 5 files changed, 209 insertions(+) diff --git a/Documentation/riscv/acpi.rst b/Documentation/riscv/acpi.rst index 9ea9008288ea..007483dfddc1 100644 --- a/Documentation/riscv/acpi.rst +++ b/Documentation/riscv/acpi.rst @@ -35,3 +35,9 @@ to this hart. ``riscv,gsi-base`` - The global system interrupt number where this APLIC’s interrupt inputs start. + +3) RISC-V Platform Level Interrupt Controller (PLIC) +----------- + +``riscv,gsi-base`` - The global system interrupt number where this PLIC’s +interrupt inputs start. diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 6dde3d63dc0e..163b8eefa744 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -71,6 +71,7 @@ int acpi_get_cbo_block_size(struct acpi_table_header *table, unsigned int cpu, u struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc); struct fwnode_handle *acpi_imsic_create_fwnode(struct acpi_madt_imsic *imsic); struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev); +int acpi_plic_get_context_id(u8 plic_id, u16 idx); #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) @@ -95,6 +96,8 @@ static inline struct fwnode_handle *acpi_riscv_get_msi_fwnode(struct device *dev { return NULL; } + +static inline int acpi_plic_get_context_id(u8 plic_id, u16 idx) { return idx; } #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index ee747211174f..cc733ea9ef1d 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -12,4 +12,5 @@ void __init acpi_riscv_init(void) { riscv_acpi_imsic_platform_init(); riscv_acpi_aplic_platform_init(); + riscv_acpi_plic_platform_init(); } diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h index 17bcf0baaadb..b4b305d83b3a 100644 --- a/drivers/acpi/riscv/init.h +++ b/drivers/acpi/riscv/init.h @@ -3,3 +3,4 @@ void __init riscv_acpi_imsic_platform_init(void); void __init riscv_acpi_aplic_platform_init(void); +void __init riscv_acpi_plic_platform_init(void); diff --git a/drivers/acpi/riscv/irqchip.c b/drivers/acpi/riscv/irqchip.c index 7fb7befdb303..cb70f0f2294b 100644 --- a/drivers/acpi/riscv/irqchip.c +++ b/drivers/acpi/riscv/irqchip.c @@ -25,6 +25,8 @@ static struct fwnode_handle *imsic_acpi_fwnode; LIST_HEAD(aplic_list); +LIST_HEAD(plic_list); + struct fwnode_handle *acpi_rintc_create_irqchip_fwnode(struct acpi_madt_rintc *rintc) { struct property_entry props[6] = {}; @@ -307,3 +309,199 @@ void __init riscv_acpi_aplic_platform_init(void) acpi_set_gsi_to_irq_fallback(aplic_gsi_to_irq); } } + +static int acpi_plic_get_nr_contexts(u8 plic_id) +{ + struct riscv_irqchip_list *rintc_element; + struct fwnode_handle *fwnode; + struct list_head *i, *tmp; + u32 id; + int rc, nr_contexts = 0; + + list_for_each_safe(i, tmp, &rintc_list) { + rintc_element = list_entry(i, struct riscv_irqchip_list, list); + fwnode = rintc_element->fwnode; + rc = fwnode_property_read_u32_array(fwnode, "riscv,ext-intc-id", &id, 1); + if (rc) + continue; + + if (APLIC_PLIC_ID(id) == plic_id) + nr_contexts++; + } + + return nr_contexts * 2; +} + +int acpi_plic_get_context_id(u8 plic_id, u16 idx) +{ + struct riscv_irqchip_list *rintc_element; + struct fwnode_handle *fwnode; + struct list_head *i, *tmp; + u32 id; + int rc, nr_contexts = -1; + + list_for_each_safe(i, tmp, &rintc_list) { + rintc_element = list_entry(i, struct riscv_irqchip_list, list); + fwnode = rintc_element->fwnode; + rc = fwnode_property_read_u32_array(fwnode, "riscv,ext-intc-id", &id, 1); + if (rc) + continue; + + if (APLIC_PLIC_ID(id) == plic_id) + nr_contexts++; + if (nr_contexts == idx) + return IDC_CONTEXT_ID(id); + } + + return -1; +} + +static struct fwnode_handle *acpi_plic_create_fwnode(struct acpi_madt_plic *plic) +{ + struct fwnode_handle *fwnode, *parent_fwnode; + struct riscv_irqchip_list *plic_element; + struct software_node_ref_args *refs; + struct property_entry props[8] = {}; + int nr_contexts; + + props[0] = PROPERTY_ENTRY_U32("riscv,gsi-base", plic->gsi_base); + props[1] = PROPERTY_ENTRY_U32("riscv,ndev", plic->num_irqs); + props[2] = PROPERTY_ENTRY_U32("riscv,max_prio", plic->max_prio); + props[3] = PROPERTY_ENTRY_U8("riscv,plic-id", plic->id); + props[4] = PROPERTY_ENTRY_U64("riscv,plic-base", plic->base_addr); + props[5] = PROPERTY_ENTRY_U32("riscv,plic-size", plic->size); + + nr_contexts = acpi_plic_get_nr_contexts(plic->id); + if (nr_contexts) { + refs = kcalloc(nr_contexts, sizeof(*refs), GFP_KERNEL); + for (int i = 0; i < nr_contexts / 2; i++) { + int context_id = acpi_plic_get_context_id(plic->id, i); + + parent_fwnode = acpi_ext_intc_get_rintc_fwnode(plic->id, context_id); + refs[2 * i] = SOFTWARE_NODE_REFERENCE(to_software_node(parent_fwnode), 0); + refs[2 * i + 1] = SOFTWARE_NODE_REFERENCE(to_software_node(parent_fwnode), + RV_IRQ_EXT); + } + props[6] = PROPERTY_ENTRY_REF_ARRAY_LEN("interrupts-extended", refs, nr_contexts); + } + + fwnode = fwnode_create_software_node_early(props, NULL); + + if (fwnode) { + plic_element = kzalloc(sizeof(*plic_element), GFP_KERNEL); + if (!plic_element) { + fwnode_remove_software_node(fwnode); + return NULL; + } + + plic_element->fwnode = fwnode; + list_add_tail(&plic_element->list, &plic_list); + } + + return fwnode; +} + +static struct fwnode_handle *plic_get_gsi_domain_id(u32 gsi) +{ + struct riscv_irqchip_list *plic_element; + struct fwnode_handle *fwnode; + struct list_head *i, *tmp; + u32 gsi_base; + u32 nr_irqs; + int rc; + + list_for_each_safe(i, tmp, &plic_list) { + plic_element = list_entry(i, struct riscv_irqchip_list, list); + fwnode = plic_element->fwnode; + rc = fwnode_property_read_u32_array(fwnode, "riscv,gsi-base", &gsi_base, 1); + if (!rc) { + rc = fwnode_property_read_u32_array(fwnode, "riscv,ndev", &nr_irqs, 1); + if (!rc && (gsi >= gsi_base && gsi < gsi_base + nr_irqs)) + return fwnode; + } + } + + return NULL; +} + +static u32 plic_gsi_to_irq(u32 gsi) +{ + return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH); +} + +static int __init plic_create_platform_device(struct fwnode_handle *fwnode) +{ + struct platform_device *pdev; + u32 plic_size; + u8 plic_id; + struct resource *res; + u64 plic_base; + int ret; + + if (!fwnode) + return -ENODEV; + + ret = fwnode_property_read_u64_array(fwnode, "riscv,plic-base", &plic_base, 1); + if (ret) + return -ENODEV; + + ret = fwnode_property_read_u32_array(fwnode, "riscv,plic-size", &plic_size, 1); + if (ret) + return -ENODEV; + + ret = fwnode_property_read_u8_array(fwnode, "riscv,plic-id", &plic_id, 1); + if (ret) + return -ENODEV; + + pdev = platform_device_alloc("riscv-plic", plic_id); + if (!pdev) + return -ENOMEM; + + res = kcalloc(1, sizeof(*res), GFP_KERNEL); + if (!res) { + ret = -ENOMEM; + goto dev_put; + } + + res->start = plic_base; + res->end = res->start + plic_size - 1; + res->flags = IORESOURCE_MEM; + ret = platform_device_add_resources(pdev, res, 1); + /* + * Resources are duplicated in platform_device_add_resources, + * free their allocated memory + */ + kfree(res); + + pdev->dev.fwnode = fwnode; + ret = platform_device_add(pdev); + if (ret) + goto dev_put; + + return 0; + +dev_put: + platform_device_put(pdev); + return ret; +} + +static int __init plic_parse_madt(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_plic *plic = (struct acpi_madt_plic *)header; + struct fwnode_handle *fwnode; + + fwnode = acpi_plic_create_fwnode(plic); + if (fwnode) + plic_create_platform_device(fwnode); + + return 0; +} + +void __init riscv_acpi_plic_platform_init(void) +{ + if (acpi_table_parse_madt(ACPI_MADT_TYPE_PLIC, plic_parse_madt, 0) > 0) { + acpi_set_irq_model(ACPI_IRQ_MODEL_PLIC, plic_get_gsi_domain_id); + acpi_set_gsi_to_irq_fallback(plic_gsi_to_irq); + } +} From patchwork Thu Aug 3 17:59:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13340457 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3215DEB64DD for ; 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Thu, 03 Aug 2023 11:02:11 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.190.143]) by smtp.gmail.com with ESMTPSA id s8-20020aa78d48000000b0065a1b05193asm134952pfe.185.2023.08.03.11.02.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Aug 2023 11:02:10 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , Daniel Scally , Heikki Krogerus , Sakari Ailus , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Anup Patel , Marc Zyngier , Bjorn Helgaas , Robert Moore , Haibo Xu , Andrew Jones , Conor Dooley , Atish Kumar Patra , Sunil V L Subject: [RFC PATCH v1 21/21] irqchip/sifive-plic: Add GSI conversion support Date: Thu, 3 Aug 2023 23:29:16 +0530 Message-Id: <20230803175916.3174453-22-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230803175916.3174453-1-sunilvl@ventanamicro.com> References: <20230803175916.3174453-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org ACPI uses flat Global System Interrupt Vector space and hence the GSI number needs to be converted to corresponding local IRQ number of the interrupt controller. Add a new gsi_base field in the priv structure to handle this which will be 0 on DT based systems. Signed-off-by: Sunil V L --- drivers/irqchip/irq-sifive-plic.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 72d6e06ef52b..1c22070e9cdd 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -68,6 +68,7 @@ struct plic_priv { unsigned long plic_quirks; unsigned int nr_irqs; unsigned long *prio_save; + u32 gsi_base; }; struct plic_handler { @@ -314,6 +315,10 @@ static int plic_irq_domain_translate(struct irq_domain *d, { struct plic_priv *priv = d->host_data; + /* For DT, gsi_base is always zero. */ + if (fwspec->param[0] >= priv->gsi_base) + fwspec->param[0] = fwspec->param[0] - priv->gsi_base; + if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) return irq_domain_translate_twocell(d, fwspec, hwirq, type); @@ -453,6 +458,17 @@ static int plic_probe(struct platform_device *pdev) return -EIO; } + /* + * Find out GSI base number + * + * Note: DT does not define "riscv,gsi-base" property so GSI + * base is always zero for DT. + */ + rc = fwnode_property_read_u32_array(dev->fwnode, "riscv,gsi-base", + &priv->gsi_base, 1); + if (rc) + priv->gsi_base = 0; + rc = fwnode_property_read_u32_array(dev->fwnode, "riscv,ndev", &nr_irqs, 1); if (rc) {