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Tue, 8 Aug 2023 05:37:42 -0500 From: Thippeswamy Havalige To: , , , , , CC: , , , , "Thippeswamy Havalige" Subject: [PATCH v2] PCI: xilinx-nwl: Remove unnecessary code which updates primary,secondary and sub-ordinate bus numbers. Date: Tue, 8 Aug 2023 16:07:30 +0530 Message-ID: <20230808103733.93707-1-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D0:EE_|CY8PR12MB7513:EE_ X-MS-Office365-Filtering-Correlation-Id: 3169b7c3-bdca-4510-006c-08db97fb814f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BfQWTNRt9puot0FeQ/fZwxHzvDmMEyoZ1fLvguHUGoJHIglTSukc0lD1ZvRHfAnce/jAuptIR16YscS1gkY4YR2ApOw3ovvLELgf+At1ccx9ndnfkgs1BnjKQDbBZupJzV17qurkBYyQajSLed6uqUtHqsw07+5hYnkqHP7a158w1F1h08tXp86FaM46kMt/OWLx8fO6aU2gmrT6iPdIebffPAgEybaaYYLbcFOiwOviJxR8Bn7FvXO+TOlipD8t/97kB/CfZOZoShk0JVatUWBegvf5RZFBp9Hsb9wPtn2ffETiaAg3kGknR6hexn6oCglYLt8brM0YXsGizXx3f2CzGSuuyFO+MvuivOS6IV12EPotfS/SQ11loQyuUjUVfozXBfkJdsebOM9gGxQ9Oz3Xdus8LX8ohpUJbc4pjpyPzB1gs57rrzK6Xi1ZWaL2/e4xT2IVE+Vq9lRulcXLn8TbLzsK2F+uuWJLnGgp9CmcI5Ir8aALe10+/w1tkSCioAOmhoXKAkzNI6glqFeZgZ2uk0TjoGfWndv5JDP7gbg9mnb04XfRbyBYbdhjSpeCfdCxf/ElAeGdVf7I3lRCL1wTfovYt45wfzg0pVL+rqztbizCXWtKWpzkal0JV+gDSC/CDeCCFld2wnOdmQ6wNzbHh3kVvq2mnmG+h0anYxbf+1Xu+wedemo1jC3ACixXmypfBvM6wePublRT/VBUGvroEMQv97k55VsNTzcWWMRcDVg4dnVKPkKycxavMb9Evk0kb4LE8Iy54Zz5pxGZ5w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(396003)(346002)(136003)(39860400002)(451199021)(186006)(82310400008)(1800799003)(36840700001)(46966006)(40470700004)(81166007)(40480700001)(40460700003)(2616005)(6666004)(86362001)(82740400003)(54906003)(478600001)(26005)(36756003)(356005)(1076003)(15650500001)(4326008)(316002)(5660300002)(8676002)(44832011)(8936002)(2906002)(41300700001)(70206006)(110136005)(70586007)(336012)(47076005)(83380400001)(36860700001)(426003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2023 10:37:46.3987 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3169b7c3-bdca-4510-006c-08db97fb814f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7513 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230808_033755_116840_251532D7 X-CRM114-Status: GOOD ( 14.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The primary,secondary and sub-ordinate bus number registers are updated by Linux PCI core, so remove code which updates repective fields of type 1 header 18th offset of Root Port configuration space. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- changes in v2: - Code increasing ECAM Size value is added into a seperate patch. - Modified commit messages. changes in v1: - Modified commit messages. --- drivers/pci/controller/pcie-xilinx-nwl.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 176686b..a73554e 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -165,8 +165,6 @@ struct nwl_pcie { u32 ecam_size; int irq_intx; int irq_misc; - u32 ecam_value; - u8 last_busno; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -625,7 +623,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) { struct device *dev = pcie->dev; struct platform_device *pdev = to_platform_device(dev); - u32 breg_val, ecam_val, first_busno = 0; + u32 breg_val, ecam_val; int err; breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; @@ -675,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) E_ECAM_CR_ENABLE, E_ECAM_CONTROL); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | - (pcie->ecam_value << E_ECAM_SIZE_SHIFT), + (NWL_ECAM_VALUE_DEFAULT << E_ECAM_SIZE_SHIFT), E_ECAM_CONTROL); nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), @@ -683,15 +681,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), E_ECAM_BASE_HI); - /* Get bus range */ - ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); - pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; - /* Write primary, secondary and subordinate bus numbers */ - ecam_val = first_busno; - ecam_val |= (first_busno + 1) << 8; - ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); - writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); - if (nwl_pcie_link_up(pcie)) dev_info(dev, "Link is UP\n"); else @@ -792,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; - pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; err = nwl_pcie_parse_dt(pcie, pdev); if (err) { From patchwork Tue Aug 8 10:37:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 13345933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB5ACC001B0 for ; Tue, 8 Aug 2023 10:38:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 8 Aug 2023 05:38:06 -0500 From: Thippeswamy Havalige To: , , , , , CC: , , , , "Thippeswamy Havalige" Subject: [PATCH v2 2/2] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses. Date: Tue, 8 Aug 2023 16:07:33 +0530 Message-ID: <20230808103733.93707-4-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230808103733.93707-1-thippeswamy.havalige@amd.com> References: <20230808103733.93707-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529E:EE_|DM6PR12MB5006:EE_ X-MS-Office365-Filtering-Correlation-Id: c71c7a90-78d0-4fa4-f44c-08db97fb8f7d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: C1HcHwRi1P5Ds8zHaIv5JNchDbtsOF2qGm+P0v5Ag453fjbrKCDW/6gjWX5ljVG7EsRJIRmtjkuNlfhruNnguU9MEeHIkx++/DbNg8ErlwY7QOOkTrRl3TJq/KZ6MFZjmi1GYoOGQl1wiSA1MTsojdAh/moy83ER/f4Ea77h4Jje8KncIzbzqca/h+uzpg3eSpKWkYimlTLoAM/cs4oiE+A6D+JMqE79P7JRbdGbEALiAmJ8QoN2iebeCmkJ/DEjq37T5BKjlKGHozGFHzLJzgMpjCOBrP8j3frMTI/OUXn6GuCa9W5WWln06T2WpwU3i0Rf7Dla3KaZVJZLXhymuVjnS8cig8OHIiKjtL+zt57p7vhaLDJdegCF7nsQea2fvQ7QzcRlH3pYqHVl7nW3oli0soJjdNAvC6ry9q/yTE2AiI5Es5DTg3/thBfWWRLQIrXJZfxrU35cxayIRr+J18fEy3DFnMoog7dyfY25mQyPApNUuSR3WT5jnrhX2+oZrxAUY56vn77kTYx5y+y7F2QJJ9Bnefz9GqHR8JtqBT0iich2og5wqI1gfkPOfyBY3lUvmKe4nHjId/26ZUHYDM5iESQYiqW9ZrRJYWismN6GQyZ5nMt9u+19PSjtAucqEhmMoV5a/VmW8hnxkekC97eCR3UvZEGaWOuipWV7xqaDObkvM2GGGr0UxD9gW6yCTGRvDpQC9rs7fI3bD+8XwJz1V/+LzVY2Vf6IsiClieNhpbCvezM7w0YCpKoZQB8D2m8EjY6NwrWwJoIS+PxHJg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(136003)(39860400002)(376002)(346002)(82310400008)(1800799003)(186006)(451199021)(46966006)(36840700001)(40470700004)(2616005)(26005)(1076003)(36756003)(336012)(6666004)(81166007)(478600001)(356005)(82740400003)(110136005)(54906003)(70586007)(70206006)(4326008)(41300700001)(426003)(316002)(8676002)(8936002)(5660300002)(44832011)(40460700003)(2906002)(36860700001)(83380400001)(47076005)(86362001)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2023 10:38:10.2414 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c71c7a90-78d0-4fa4-f44c-08db97fb8f7d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB5006 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230808_033817_432505_544781C8 X-CRM114-Status: GOOD ( 12.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- changes in v2: - Update this changes in a seperate patch. --- drivers/pci/controller/pcie-xilinx-nwl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index a73554e..b515019 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_VALUE_DEFAULT 12 +#define NWL_ECAM_VALUE_DEFAULT 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0)