From patchwork Fri Feb 8 12:25:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10802991 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6798B746 for ; Fri, 8 Feb 2019 12:25:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 52D5A2DCC9 for ; Fri, 8 Feb 2019 12:25:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 42DA72DCED; Fri, 8 Feb 2019 12:25:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E9F6F2DCC9 for ; Fri, 8 Feb 2019 12:25:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=xbuaVDwizQrRSlZ7lRV4pPI0NbHrW41JONNlkCq8Ciw=; b=JXM ahStQLOurA+QyKuM5kGSE6Y4dlOmxsZFYU67L55bC1AkUtbLMnA6tl9NBLy/GcjPcqjBIGHpvhVtp O4avVHNhU9Uum/0IgTDfgqLcbXnwn/KVwrEPEH9rI761DxCMVAyyPAXj3pqxM+yFncy1Nae/lJbA/ gpgQqM/pg3y1TizwxKO/Bn1fQwzR13j48aAigqC7Va2w9WV18qlXK7j5KKTsa0xjyGjUdxUXlOfXQ grkS+uZiU+A3JfPxHr1yUzvcioK+8fMg32y+qeR5zR6Xuxq1dEn/P0P8BBToTjetdAnVakq+L5VRd UDFmJjeFwJFxvn5y1/OMVlY0hW6MUkA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gs5DJ-0005UW-9K; Fri, 08 Feb 2019 12:25:01 +0000 Received: from mx.socionext.com ([202.248.49.38]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gs5DE-0005RO-Go for linux-arm-kernel@lists.infradead.org; Fri, 08 Feb 2019 12:24:58 +0000 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:24:54 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 09A79180D62; Fri, 8 Feb 2019 21:24:55 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:24:54 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 787901A04E1; Fri, 8 Feb 2019 21:24:54 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 640961202F1; Fri, 8 Feb 2019 21:24:54 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 01/15] dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram Date: Fri, 8 Feb 2019 21:25:33 +0900 Message-Id: <1549628733-30171-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_042456_775931_3A81C68F X-CRM114-Status: GOOD ( 17.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Shinji Kanematsu , Masami Hiramatsu , Sugaya Taichi , Jassi Brar , Rob Herring , Takao Orito , Kazuhiro Kasai MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Milbeaut M10V SoC needs a part of sram for smp, so this adds the M10V sram compatible and binding. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- .../devicetree/bindings/sram/milbeaut-smp-sram.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt diff --git a/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt new file mode 100644 index 0000000..194f6a3 --- /dev/null +++ b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt @@ -0,0 +1,24 @@ +Milbeaut SRAM for smp bringup + +Milbeaut SoCs use a part of the sram for the bringup of the secondary cores. +Once they get powered up in the bootloader, they stay at the specific part +of the sram. +Therefore the part needs to be added as the sub-node of mmio-sram. + +Required sub-node properties: +- compatible : should be "socionext,milbeaut-smp-sram" + +Example: + + sram: sram@0 { + compatible = "mmio-sram"; + reg = <0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x10000>; + + smp-sram@f100 { + compatible = "socionext,milbeaut-smp-sram"; + reg = <0xf100 0x20>; + }; + }; From patchwork Fri Feb 8 12:26:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10802993 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 64EE2746 for ; Fri, 8 Feb 2019 12:25:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 52BE92DCC9 for ; Fri, 8 Feb 2019 12:25:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 46D132DCED; Fri, 8 Feb 2019 12:25:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E4F862DCC9 for ; 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Fri, 08 Feb 2019 12:25:38 +0000 Received: from mx.socionext.com ([202.248.49.38]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gs5Df-0006vT-9Z for linux-arm-kernel@lists.infradead.org; Fri, 08 Feb 2019 12:25:26 +0000 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:25:22 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 8D6F860062; Fri, 8 Feb 2019 21:25:22 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:25:22 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 1DE9E1A04E1; Fri, 8 Feb 2019 21:25:22 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 090FC1202F1; Fri, 8 Feb 2019 21:25:22 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 03/15] dt-bindings: Add documentation for Milbeaut SoCs Date: Fri, 8 Feb 2019 21:26:04 +0900 Message-Id: <1549628764-30587-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_042523_530210_8A9D1FC8 X-CRM114-Status: GOOD ( 13.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Shinji Kanematsu , Masami Hiramatsu , Sugaya Taichi , Jassi Brar , Rob Herring , Takao Orito , Kazuhiro Kasai MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This adds a DT binding documentation for the M10V and its evaluation board. Signed-off-by: Sugaya Taichi --- Documentation/devicetree/bindings/arm/milbeaut.txt | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/milbeaut.txt diff --git a/Documentation/devicetree/bindings/arm/milbeaut.txt b/Documentation/devicetree/bindings/arm/milbeaut.txt new file mode 100644 index 0000000..9fd053a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/milbeaut.txt @@ -0,0 +1,6 @@ +Milbeaut platforms device tree bindings +--------------------------------------- + +- Milbeaut M10V Evaluation Board + Required root node properties: + - compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a"; From patchwork Fri Feb 8 12:26:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10802995 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0F14513A4 for ; Fri, 8 Feb 2019 12:26:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EF7C42DCC9 for ; Fri, 8 Feb 2019 12:25:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E370F2DD09; Fri, 8 Feb 2019 12:25:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 538272DCC9 for ; Fri, 8 Feb 2019 12:25:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=Luc6uQHEt6bkq0R9sqY6MstndKi6+dS106qVZLuwM14=; b=AGh 19gh1t5TiCyF3x1TWCikyAGMcI2Kk9udsynO811qZTkJD3m2TvMhTrUMYfnu27a0LWpppeFtsHUt/ BW+OJrqkIw95g4vHEVZmVctwREmtPzcBB+0Wzdc6Bx1W6+c7TwaOxHNisGw5BRI7j5qluQ+BIzWsP Jp3DzfgPEhXtNfTvLNi+OA0jfWdCM73KO81+eDM2ldAd6MZaXkyuYAiU0O9vVFy5BZ3u5EhhwZKxi 5EOtl27lW43RD9XQlA3ZfnrNBgVCZ+91WJli8MRkV3BNIHwVNLJ3U6pQPghbDgDAGDQbGvDjxU+Z8 xnomhNsz05MGbhtgUbOzFlA4GdOn7Zg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gs5EC-0007WL-NQ; Fri, 08 Feb 2019 12:25:56 +0000 Received: from mx.socionext.com ([202.248.49.38]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gs5Ds-0007A4-Cq for linux-arm-kernel@lists.infradead.org; Fri, 08 Feb 2019 12:25:53 +0000 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:25:35 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 6FBE160062; Fri, 8 Feb 2019 21:25:35 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:25:35 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 498921A04E1; Fri, 8 Feb 2019 21:25:35 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 2E5511202F1; Fri, 8 Feb 2019 21:25:35 +0900 (JST) From: Sugaya Taichi To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 04/15] ARM: milbeaut: Add basic support for Milbeaut m10v SoC Date: Fri, 8 Feb 2019 21:26:18 +0900 Message-Id: <1549628778-30785-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_042537_438747_26EC418E X-CRM114-Status: GOOD ( 19.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shinji Kanematsu , Masami Hiramatsu , Sugaya Taichi , Russell King , Jassi Brar , Takao Orito , Kazuhiro Kasai MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This adds the basic M10V SoC support under arch/arm. Since all cores are activated in the custom bootloader before booting linux, it is necessary to wait for the secondary-cores using cpu-enable- method and special sram. Signed-off-by: Sugaya Taichi --- arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/mach-milbeaut/Kconfig | 20 ++++++ arch/arm/mach-milbeaut/Makefile | 1 + arch/arm/mach-milbeaut/platsmp.c | 144 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 168 insertions(+) create mode 100644 arch/arm/mach-milbeaut/Kconfig create mode 100644 arch/arm/mach-milbeaut/Makefile create mode 100644 arch/arm/mach-milbeaut/platsmp.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 664e918..c8cb752 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -750,6 +750,8 @@ source "arch/arm/mach-mediatek/Kconfig" source "arch/arm/mach-meson/Kconfig" +source "arch/arm/mach-milbeaut/Kconfig" + source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-moxart/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 9db3c58..00000e9 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -190,6 +190,7 @@ machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 machine-$(CONFIG_ARCH_MVEBU) += mvebu machine-$(CONFIG_ARCH_MXC) += imx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek +machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut machine-$(CONFIG_ARCH_MXS) += mxs machine-$(CONFIG_ARCH_NETX) += netx machine-$(CONFIG_ARCH_NOMADIK) += nomadik diff --git a/arch/arm/mach-milbeaut/Kconfig b/arch/arm/mach-milbeaut/Kconfig new file mode 100644 index 0000000..6a576fd --- /dev/null +++ b/arch/arm/mach-milbeaut/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0 +menuconfig ARCH_MILBEAUT + bool "Socionext Milbeaut SoCs" + depends on ARCH_MULTI_V7 + select ARM_GIC + help + This enables support for Socionext Milbeaut SoCs + +if ARCH_MILBEAUT + +config ARCH_MILBEAUT_M10V + bool "Milbeaut SC2000/M10V platform" + select ARM_ARCH_TIMER + select MILBEAUT_TIMER + select PINCTRL + select PINCTRL_MILBEAUT + help + Support for Socionext's MILBEAUT M10V based systems + +endif diff --git a/arch/arm/mach-milbeaut/Makefile b/arch/arm/mach-milbeaut/Makefile new file mode 100644 index 0000000..ce5ea06 --- /dev/null +++ b/arch/arm/mach-milbeaut/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-milbeaut/platsmp.c b/arch/arm/mach-milbeaut/platsmp.c new file mode 100644 index 0000000..bdcd98e --- /dev/null +++ b/arch/arm/mach-milbeaut/platsmp.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright: (C) 2018 Socionext Inc. + * Copyright: (C) 2015 Linaro Ltd. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define M10V_MAX_CPU 4 +#define KERNEL_UNBOOT_FLAG 0x12345678 + +static void __iomem *m10v_smp_base; + +static int m10v_boot_secondary(unsigned int l_cpu, struct task_struct *idle) +{ + unsigned int mpidr, cpu, cluster; + + if (!m10v_smp_base) + return -ENXIO; + + mpidr = cpu_logical_map(l_cpu); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + + if (cpu >= M10V_MAX_CPU) + return -EINVAL; + + pr_info("%s: cpu %u l_cpu %u cluster %u\n", + __func__, cpu, l_cpu, cluster); + + writel(__pa_symbol(secondary_startup), m10v_smp_base + cpu * 4); + arch_send_wakeup_ipi_mask(cpumask_of(l_cpu)); + + return 0; +} + +static void m10v_smp_init(unsigned int max_cpus) +{ + unsigned int mpidr, cpu, cluster; + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "socionext,milbeaut-smp-sram"); + if (!np) + return; + + m10v_smp_base = of_iomap(np, 0); + if (!m10v_smp_base) + return; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + pr_info("MCPM boot on cpu_%u cluster_%u\n", cpu, cluster); + + for (cpu = 0; cpu < M10V_MAX_CPU; cpu++) + writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4); +} + +static void m10v_cpu_die(unsigned int l_cpu) +{ + gic_cpu_if_down(0); + v7_exit_coherency_flush(louis); + wfi(); +} + +static int m10v_cpu_kill(unsigned int l_cpu) +{ + unsigned int mpidr, cpu; + + mpidr = cpu_logical_map(l_cpu); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + + writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4); + + return 1; +} + +static struct smp_operations m10v_smp_ops __initdata = { + .smp_prepare_cpus = m10v_smp_init, + .smp_boot_secondary = m10v_boot_secondary, + .cpu_die = m10v_cpu_die, + .cpu_kill = m10v_cpu_kill, +}; +CPU_METHOD_OF_DECLARE(m10v_smp, "socionext,milbeaut-m10v-smp", &m10v_smp_ops); + +static int m10v_pm_valid(suspend_state_t state) +{ + return (state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM); +} + +typedef void (*phys_reset_t)(unsigned long); +static phys_reset_t phys_reset; + +static int m10v_die(unsigned long arg) +{ + setup_mm_for_reboot(); + asm("wfi"); + /* Boot just like a secondary */ + phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset); + phys_reset(virt_to_phys(cpu_resume)); + + return 0; +} + +static int m10v_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + pr_err("STANDBY\n"); + asm("wfi"); + break; + case PM_SUSPEND_MEM: + pr_err("SUSPEND\n"); + cpu_pm_enter(); + cpu_suspend(0, m10v_die); + cpu_pm_exit(); + break; + } + return 0; +} + +static const struct platform_suspend_ops m10v_pm_ops = { + .valid = m10v_pm_valid, + .enter = m10v_pm_enter, +}; + +struct clk *m10v_clclk_register(struct device *cpu_dev); + +static int __init m10v_pm_init(void) +{ + suspend_set_ops(&m10v_pm_ops); + + return 0; +} +late_initcall(m10v_pm_init); From patchwork Fri Feb 8 12:26:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10803027 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B71F113BF for ; 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bh=8ctHlCnGk4GG2lH3vb0rp43bRUPTwOYTSFNDdbGgdPo=; b=sCr o9fjk6Nc6NKbbp0CTvi9iUnMSlq7rjM8rIruCojmOW7IUErL9O2msXuKhAjoWE/WvfFiSkwjtUslK IQoFZNcsk9wiMVDk4wEb1VKXLGwAy363jnOpjkpr9vSOmdmtZ4teywYeYf5TxURP9o/8c6k5AFpCQ I9dKzrJu8MtTzNQi7iS+smm75OCqSkpeq7TFnarH2Tc0y4shh30P4W81SokqVOfwez4J3NpvvsgGZ to/ItWSoAjIH1j+IP9UevaKhhyUyAufn2F4N9QFhs1KgXXQycqbJ3VG6I6tPcpUHMKfjern5FpkFb 6GEDarViMLIFDukoVz6McAtjaS7SNUA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gs5PL-0007GD-HK; Fri, 08 Feb 2019 12:37:27 +0000 Received: from mx.socionext.com ([202.248.49.38]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gs5EA-0007Ub-BA for linux-arm-kernel@lists.infradead.org; Fri, 08 Feb 2019 12:26:16 +0000 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:25:53 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 8B115180D62; Fri, 8 Feb 2019 21:25:53 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:25:53 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 355291A04E1; Fri, 8 Feb 2019 21:25:53 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 1DC471202F1; Fri, 8 Feb 2019 21:25:53 +0900 (JST) From: Sugaya Taichi To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 05/15] dt-bindings: timer: Add Milbeaut M10V timer description Date: Fri, 8 Feb 2019 21:26:30 +0900 Message-Id: <1549628790-30960-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_042554_675804_6A403081 X-CRM114-Status: GOOD ( 15.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Shinji Kanematsu , Masami Hiramatsu , Sugaya Taichi , Daniel Lezcano , Jassi Brar , Rob Herring , Takao Orito , Thomas Gleixner , Kazuhiro Kasai MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add DT bindings document for Milbeaut M10V timer. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- .../bindings/timer/socionext,milbeaut-timer.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt diff --git a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt new file mode 100644 index 0000000..ac44c4b --- /dev/null +++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt @@ -0,0 +1,17 @@ +Milbeaut SoCs Timer Controller + +Required properties: + +- compatible : should be "socionext,milbeaut-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : The interrupt of the first timer. +- clocks: phandle to the input clk. + +Example: + +timer { + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20> + interrupts = <0 91 4>; + clocks = <&clk 4>; +}; From patchwork Fri Feb 8 12:26:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10802999 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 956ED13A4 for ; Fri, 8 Feb 2019 12:26:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 809EF2DCC9 for ; Fri, 8 Feb 2019 12:26:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 71A1C2DCED; Fri, 8 Feb 2019 12:26:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BC4C02DCC9 for ; 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Fri, 08 Feb 2019 12:26:28 +0000 Received: from mx.socionext.com ([202.248.49.38]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gs5EQ-0007oP-KQ for linux-arm-kernel@lists.infradead.org; Fri, 08 Feb 2019 12:26:26 +0000 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:26:09 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id E2E6760062; Fri, 8 Feb 2019 21:26:09 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:26:09 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id A4D711A04E1; Fri, 8 Feb 2019 21:26:09 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 922AF1202F1; Fri, 8 Feb 2019 21:26:09 +0900 (JST) From: Sugaya Taichi To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 06/15] clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs Date: Fri, 8 Feb 2019 21:26:52 +0900 Message-Id: <1549628812-31235-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_042611_522244_7F0912D2 X-CRM114-Status: GOOD ( 18.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shinji Kanematsu , Masami Hiramatsu , Sugaya Taichi , Daniel Lezcano , Jassi Brar , Takao Orito , Thomas Gleixner , Kazuhiro Kasai MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add timer driver for Milbeaut SoCs series. The timer has two 32-bit width down counters, one of which is configured as a clockevent device and the other is configured as a clock source. Signed-off-by: Sugaya Taichi Acked-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 9 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-milbeaut.c | 161 +++++++++++++++++++++++++++++++++++ 3 files changed, 171 insertions(+) create mode 100644 drivers/clocksource/timer-milbeaut.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index a9e26f6..9101b8f 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -634,4 +634,13 @@ config GX6605S_TIMER help This option enables support for gx6605s SOC's timer. +config MILBEAUT_TIMER + bool "Milbeaut timer driver" if COMPILE_TEST + depends on OF + depends on ARM + select TIMER_OF + select CLKSRC_MMIO + help + Enables the support for Milbeaut timer driver. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index cdd210f..6f2543b 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o obj-$(CONFIG_OWL_TIMER) += timer-owl.o +obj-$(CONFIG_MILBEAUT_TIMER) += timer-milbeaut.o obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o obj-$(CONFIG_RDA_TIMER) += timer-rda.o diff --git a/drivers/clocksource/timer-milbeaut.c b/drivers/clocksource/timer-milbeaut.c new file mode 100644 index 0000000..f2019a8 --- /dev/null +++ b/drivers/clocksource/timer-milbeaut.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Socionext Inc. + */ + +#include +#include +#include +#include +#include +#include "timer-of.h" + +#define MLB_TMR_TMCSR_OFS 0x0 +#define MLB_TMR_TMR_OFS 0x4 +#define MLB_TMR_TMRLR1_OFS 0x8 +#define MLB_TMR_TMRLR2_OFS 0xc +#define MLB_TMR_REGSZPCH 0x10 + +#define MLB_TMR_TMCSR_OUTL BIT(5) +#define MLB_TMR_TMCSR_RELD BIT(4) +#define MLB_TMR_TMCSR_INTE BIT(3) +#define MLB_TMR_TMCSR_UF BIT(2) +#define MLB_TMR_TMCSR_CNTE BIT(1) +#define MLB_TMR_TMCSR_TRG BIT(0) + +#define MLB_TMR_TMCSR_CSL_DIV2 0 +#define MLB_TMR_DIV_CNT 2 + +#define MLB_TMR_SRC_CH (1) +#define MLB_TMR_EVT_CH (0) + +#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH) +#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH) + +#define MLB_TMR_SRC_TMCSR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMCSR_OFS) +#define MLB_TMR_SRC_TMR_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMR_OFS) +#define MLB_TMR_SRC_TMRLR1_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR1_OFS) +#define MLB_TMR_SRC_TMRLR2_OFS (MLB_TMR_SRC_CH_OFS + MLB_TMR_TMRLR2_OFS) + +#define MLB_TMR_EVT_TMCSR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMCSR_OFS) +#define MLB_TMR_EVT_TMR_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMR_OFS) +#define MLB_TMR_EVT_TMRLR1_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR1_OFS) +#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS) + +#define MLB_TIMER_RATING 500 + +static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *clk = dev_id; + struct timer_of *to = to_timer_of(clk); + u32 val; + + val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + val &= ~MLB_TMR_TMCSR_UF; + writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + + clk->event_handler(clk); + + return IRQ_HANDLED; +} + +static int mlb_set_state_periodic(struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + u32 val = MLB_TMR_TMCSR_CSL_DIV2; + + writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + + writel_relaxed(to->of_clk.period, timer_of_base(to) + + MLB_TMR_EVT_TMRLR1_OFS); + val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE | + MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE; + writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + return 0; +} + +static int mlb_set_state_oneshot(struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + u32 val = MLB_TMR_TMCSR_CSL_DIV2; + + writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + return 0; +} + +static int mlb_clkevt_next_event(unsigned long event, + struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + + writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS); + writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 | + MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_INTE | + MLB_TMR_TMCSR_TRG, timer_of_base(to) + + MLB_TMR_EVT_TMCSR_OFS); + return 0; +} + +static int mlb_config_clock_source(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS); + writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMR_OFS); + writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS); + writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS); + writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) + + MLB_TMR_SRC_TMCSR_OFS); + return 0; +} + +static int mlb_config_clock_event(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS); + return 0; +} + +static struct timer_of to = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, + + .clkevt = { + .name = "mlb-clkevt", + .rating = MLB_TIMER_RATING, + .cpumask = cpu_possible_mask, + .features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT, + .set_state_oneshot = mlb_set_state_oneshot, + .set_state_periodic = mlb_set_state_periodic, + .set_next_event = mlb_clkevt_next_event, + }, + + .of_irq = { + .flags = IRQF_TIMER | IRQF_IRQPOLL, + .handler = mlb_timer_interrupt, + }, +}; + +static u64 notrace mlb_timer_sched_read(void) +{ + return ~readl_relaxed(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS); +} + +static int __init mlb_timer_init(struct device_node *node) +{ + int ret; + unsigned long rate; + + ret = timer_of_init(node, &to); + if (ret) + return ret; + + rate = timer_of_rate(&to) / MLB_TMR_DIV_CNT; + mlb_config_clock_source(&to); + clocksource_mmio_init(timer_of_base(&to) + MLB_TMR_SRC_TMR_OFS, + node->name, rate, MLB_TIMER_RATING, 32, + clocksource_mmio_readl_down); + sched_clock_register(mlb_timer_sched_read, 32, rate); + mlb_config_clock_event(&to); + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 15, + 0xffffffff); + return 0; +} +TIMER_OF_DECLARE(mlb_peritimer, "socionext,milbeaut-timer", + mlb_timer_init); From patchwork Fri Feb 8 12:27:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10803003 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A37B2746 for ; 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Fri, 8 Feb 2019 21:26:18 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:26:18 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id AA4EA4036D; Fri, 8 Feb 2019 21:26:18 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 874BD1202F1; Fri, 8 Feb 2019 21:26:18 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 07/15] ndings: clock: milbeaut: add Milbeaut clock description Date: Fri, 8 Feb 2019 21:27:03 +0900 Message-Id: <1549628823-31388-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_042619_493936_16662964 X-CRM114-Status: GOOD ( 16.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Shinji Kanematsu , Sugaya Taichi , Masami Hiramatsu , Stephen Boyd , Michael Turquette , Jassi Brar , Rob Herring , Takao Orito , Kazuhiro Kasai MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add DT bindings document for Milbeaut clock. Signed-off-by: Sugaya Taichi --- .../devicetree/bindings/clock/milbeaut-clock.txt | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/milbeaut-clock.txt diff --git a/Documentation/devicetree/bindings/clock/milbeaut-clock.txt b/Documentation/devicetree/bindings/clock/milbeaut-clock.txt new file mode 100644 index 0000000..bcfc5df --- /dev/null +++ b/Documentation/devicetree/bindings/clock/milbeaut-clock.txt @@ -0,0 +1,49 @@ +Milbeaut SoCs Clock Controller Binding +---------------------------------------- +Milbeaut SoCs Clock controller is an integrated clock controller, which +generates and supplies to all modules. + +This binding uses common clock bindings +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: should be one of the following: + "socionext,milbeaut-m10v-ccu" - for M10V SoC +- reg: shall contain base address and length of clock registers +- #clock-cells: shall be 1 +- clocks: shall be an external clock + +Example: Clock controller node: + + clk: m10v-clk-ctrl@1d021000 { + compatible = "socionext,milbeaut-m10v-clk-ccu"; + reg = <0x1d021000 0x4000>; + #clock-cells = <1> + clocks = <&clki40mhz> + }; + +Example: Required an external clock for Clock controller node: + + clocks { + clki40mhz: clki40mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + /* other clocks */ + }; + +The clock consumer shall specify the desired clock-output of the clock +controller as below by specifying output-id in its "clk" phandle cell. +2: uart +4: 32-bit timer + +Example: uart1 node: + uart1: serial@1e700010 { + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&clk 2>; + }; From patchwork Fri Feb 8 12:27:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10803005 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AB1BA746 for ; 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bh=TZYy02yatNPLJngNtEN1zKwTxlZvlyowz9azfucLnjA=; b=YCG TYy0oW286wWxhQc34uReNOJuktQ1fAhguDXU7cqjgkOqShT3RXchoy20L9C0oIxrzwWahcb4tpHku ogjEf4fW9rZwY4xKwMaic0v0X1tYq9JLoLdni/VN76okmVdzbNgMnlKJrASmRoAXxrD85EAnHM8M5 0A2hVQP3tv9HBEnkyMrjRYe3HsP4gZ5FnmqUJE9MZe/+ILJHK8bJOxMaZEC6muwkL8/WON3qIc1dx DrCjqkLfusLfiPOElqkJudXVSDdOLVJs3z067JaJRjZiNTsKL0YcqAF7o10fNc11is2BhwJar8TGr 4HyEC25y5jvfaff+W9ZkHRitdXYnBfA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gs5FJ-0008TS-4P; Fri, 08 Feb 2019 12:27:05 +0000 Received: from mx.socionext.com ([202.248.49.38]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gs5Eo-00083F-0j for linux-arm-kernel@lists.infradead.org; Fri, 08 Feb 2019 12:26:49 +0000 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:26:33 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 3E47F60062; Fri, 8 Feb 2019 21:26:33 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:26:33 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id A073E4036D; Fri, 8 Feb 2019 21:26:32 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 8BA491202F1; Fri, 8 Feb 2019 21:26:32 +0900 (JST) From: Sugaya Taichi To: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 08/15] clock: milbeaut: Add Milbeaut M10V clock controller Date: Fri, 8 Feb 2019 21:27:17 +0900 Message-Id: <1549628837-31574-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_042635_450395_ECA5E760 X-CRM114-Status: GOOD ( 21.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shinji Kanematsu , Sugaya Taichi , Masami Hiramatsu , Stephen Boyd , Michael Turquette , Jassi Brar , Takao Orito , Kazuhiro Kasai MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The M10V of the Milbeaut SoCs has an on-chip controller that derive mostly clocks from a single external clock, using PLLs, dividers, multiplexers and gates. Since the PLLs have already been started and will not stop / restart, they are fixed factor. Gates will be added in later patch (all gates are off state). Signed-off-by: Sugaya Taichi --- drivers/clk/Makefile | 1 + drivers/clk/clk-milbeaut.c | 626 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 627 insertions(+) create mode 100644 drivers/clk/clk-milbeaut.c diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 8a9440a..84a78e8 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o +obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-milbeaut.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o diff --git a/drivers/clk/clk-milbeaut.c b/drivers/clk/clk-milbeaut.c new file mode 100644 index 0000000..f798939 --- /dev/null +++ b/drivers/clk/clk-milbeaut.c @@ -0,0 +1,626 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Socionext Inc. + * Copyright (C) 2016 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define M10V_CLKSEL1 0x0 +#define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1) + +#define M10V_PLL1 "pll1" +#define M10V_PLL1DIV2 "pll1-2" +#define M10V_PLL2 "pll2" +#define M10V_PLL2DIV2 "pll2-2" +#define M10V_PLL6 "pll6" +#define M10V_PLL6DIV2 "pll6-2" +#define M10V_PLL6DIV3 "pll6-3" +#define M10V_PLL7 "pll7" +#define M10V_PLL7DIV2 "pll7-2" +#define M10V_PLL7DIV5 "pll7-5" +#define M10V_PLL9 "pll9" +#define M10V_PLL10 "pll10" +#define M10V_PLL10DIV2 "pll10-2" +#define M10V_PLL11 "pll11" + +#define M10V_SPI_PARENT0 "spi-parent0" +#define M10V_SPI_PARENT1 "spi-parent1" +#define M10V_SPI_PARENT2 "spi-parent2" +#define M10V_UHS1CLK2_PARENT0 "uhs1clk2-parent0" +#define M10V_UHS1CLK2_PARENT1 "uhs1clk2-parent1" +#define M10V_UHS1CLK2_PARENT2 "uhs1clk2-parent2" +#define M10V_UHS1CLK1_PARENT0 "uhs1clk1-parent0" +#define M10V_UHS1CLK1_PARENT1 "uhs1clk1-parent1" +#define M10V_NFCLK_PARENT0 "nfclk-parent0" +#define M10V_NFCLK_PARENT1 "nfclk-parent1" +#define M10V_NFCLK_PARENT2 "nfclk-parent2" +#define M10V_NFCLK_PARENT3 "nfclk-parent3" +#define M10V_NFCLK_PARENT4 "nfclk-parent4" +#define M10V_NFCLK_PARENT5 "nfclk-parent5" + +#define M10V_DCHREQ 1 +#define M10V_UPOLL_RATE 1 +#define M10V_UTIMEOUT 250 + +#define M10V_EMMCCLK_ID 0 +#define M10V_ACLK_ID 1 +#define M10V_HCLK_ID 2 +#define M10V_PCLK_ID 3 +#define M10V_RCLK_ID 4 +#define M10V_SPICLK_ID 5 +#define M10V_NFCLK_ID 6 +#define M10V_NUM_CLKS 7 + +#define to_m10v_div(_hw) container_of(_hw, struct m10v_clk_divider, hw) + +static struct clk_hw_onecell_data *m10v_clk_data; + +static DEFINE_SPINLOCK(m10v_crglock); + +struct m10v_clk_pll_factors { + const char *name; + const char *parent_name; + u32 div; + u32 mult; +}; +struct m10v_clk_div_factors { + const char *name; + const char *parent_name; + u32 offset; + u8 shift; + u8 width; + const struct clk_div_table *table; + unsigned long div_flags; + int onecell_idx; +}; +struct m10v_clk_div_fixed_data { + const char *name; + const char *parent_name; + u8 div; + u8 mult; + int onecell_idx; +}; +struct m10v_clk_mux_factors { + const char *name; + const char * const *parent_names; + u8 num_parents; + u32 offset; + u8 shift; + u8 mask; + u32 *table; + unsigned long mux_flags; + int onecell_idx; +}; + +static const struct clk_div_table emmcclk_table[] = { + { .val = 0, .div = 8 }, + { .val = 1, .div = 9 }, + { .val = 2, .div = 10 }, + { .val = 3, .div = 15 }, + { .div = 0 }, +}; +static const struct clk_div_table mclk400_table[] = { + { .val = 1, .div = 2 }, + { .val = 3, .div = 4 }, + { .div = 0 }, +}; +static const struct clk_div_table mclk200_table[] = { + { .val = 3, .div = 4 }, + { .val = 7, .div = 8 }, + { .div = 0 }, +}; +static const struct clk_div_table aclk400_table[] = { + { .val = 1, .div = 2 }, + { .val = 3, .div = 4 }, + { .div = 0 }, +}; +static const struct clk_div_table aclk300_table[] = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 3 }, + { .div = 0 }, +}; +static const struct clk_div_table aclk_table[] = { + { .val = 3, .div = 4 }, + { .val = 7, .div = 8 }, + { .div = 0 }, +}; +static const struct clk_div_table aclkexs_table[] = { + { .val = 3, .div = 4 }, + { .val = 4, .div = 5 }, + { .val = 5, .div = 6 }, + { .val = 7, .div = 8 }, + { .div = 0 }, +}; +static const struct clk_div_table hclk_table[] = { + { .val = 7, .div = 8 }, + { .val = 15, .div = 16 }, + { .div = 0 }, +}; +static const struct clk_div_table hclkbmh_table[] = { + { .val = 3, .div = 4 }, + { .val = 7, .div = 8 }, + { .div = 0 }, +}; +static const struct clk_div_table pclk_table[] = { + { .val = 15, .div = 16 }, + { .val = 31, .div = 32 }, + { .div = 0 }, +}; +static const struct clk_div_table rclk_table[] = { + { .val = 0, .div = 8 }, + { .val = 1, .div = 16 }, + { .val = 2, .div = 24 }, + { .val = 3, .div = 32 }, + { .div = 0 }, +}; +static const struct clk_div_table uhs1clk0_table[] = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 3 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 8 }, + { .val = 4, .div = 16 }, + { .div = 0 }, +}; +static const struct clk_div_table uhs2clk_table[] = { + { .val = 0, .div = 9 }, + { .val = 1, .div = 10 }, + { .val = 2, .div = 11 }, + { .val = 3, .div = 12 }, + { .val = 4, .div = 13 }, + { .val = 5, .div = 14 }, + { .val = 6, .div = 16 }, + { .val = 7, .div = 18 }, + { .div = 0 }, +}; + +static u32 spi_mux_table[] = {0, 1, 2}; +static const char * const spi_mux_names[] = { + M10V_SPI_PARENT0, M10V_SPI_PARENT1, M10V_SPI_PARENT2 +}; + +static u32 uhs1clk2_mux_table[] = {2, 3, 4, 8}; +static const char * const uhs1clk2_mux_names[] = { + M10V_UHS1CLK2_PARENT0, M10V_UHS1CLK2_PARENT1, + M10V_UHS1CLK2_PARENT2, M10V_PLL6DIV2 +}; + +static u32 uhs1clk1_mux_table[] = {3, 4, 8}; +static const char * const uhs1clk1_mux_names[] = { + M10V_UHS1CLK1_PARENT0, M10V_UHS1CLK1_PARENT1, M10V_PLL6DIV2 +}; + +static u32 nfclk_mux_table[] = {0, 1, 2, 3, 4, 8}; +static const char * const nfclk_mux_names[] = { + M10V_NFCLK_PARENT0, M10V_NFCLK_PARENT1, M10V_NFCLK_PARENT2, + M10V_NFCLK_PARENT3, M10V_NFCLK_PARENT4, M10V_NFCLK_PARENT5 +}; + +static const struct m10v_clk_pll_factors m10v_pll_fixed_data[] = { + {M10V_PLL1, NULL, 1, 40}, + {M10V_PLL2, NULL, 1, 30}, + {M10V_PLL6, NULL, 1, 35}, + {M10V_PLL7, NULL, 1, 40}, + {M10V_PLL9, NULL, 1, 33}, + {M10V_PLL10, NULL, 5, 108}, + {M10V_PLL10DIV2, M10V_PLL10, 2, 1}, + {M10V_PLL11, NULL, 2, 75}, +}; + +static const struct m10v_clk_div_fixed_data m10v_div_fixed_data[] = { + {"usb2", NULL, 2, 1, -1}, + {"pcisuppclk", NULL, 20, 1, -1}, + {M10V_PLL1DIV2, M10V_PLL1, 2, 1, -1}, + {M10V_PLL2DIV2, M10V_PLL2, 2, 1, -1}, + {M10V_PLL6DIV2, M10V_PLL6, 2, 1, -1}, + {M10V_PLL6DIV3, M10V_PLL6, 3, 1, -1}, + {M10V_PLL7DIV2, M10V_PLL7, 2, 1, -1}, + {M10V_PLL7DIV5, M10V_PLL7, 5, 1, -1}, + {"ca7wd", M10V_PLL2DIV2, 12, 1, -1}, + {"pclkca7wd", M10V_PLL1DIV2, 16, 1, -1}, + {M10V_SPI_PARENT0, M10V_PLL10DIV2, 2, 1, -1}, + {M10V_SPI_PARENT1, M10V_PLL10DIV2, 4, 1, -1}, + {M10V_SPI_PARENT2, M10V_PLL7DIV2, 8, 1, -1}, + {M10V_UHS1CLK2_PARENT0, M10V_PLL7, 4, 1, -1}, + {M10V_UHS1CLK2_PARENT1, M10V_PLL7, 8, 1, -1}, + {M10V_UHS1CLK2_PARENT2, M10V_PLL7, 16, 1, -1}, + {M10V_UHS1CLK1_PARENT0, M10V_PLL7, 8, 1, -1}, + {M10V_UHS1CLK1_PARENT1, M10V_PLL7, 16, 1, -1}, + {M10V_NFCLK_PARENT0, M10V_PLL7DIV2, 8, 1, -1}, + {M10V_NFCLK_PARENT1, M10V_PLL7DIV2, 10, 1, -1}, + {M10V_NFCLK_PARENT2, M10V_PLL7DIV2, 13, 1, -1}, + {M10V_NFCLK_PARENT3, M10V_PLL7DIV2, 16, 1, -1}, + {M10V_NFCLK_PARENT4, M10V_PLL7DIV2, 40, 1, -1}, + {M10V_NFCLK_PARENT5, M10V_PLL7DIV5, 10, 1, -1}, +}; + +static const struct m10v_clk_div_factors m10v_div_factor_data[] = { + {"emmc", M10V_PLL11, CLKSEL(1), 28, 3, emmcclk_table, 0, + M10V_EMMCCLK_ID}, + {"mclk400", M10V_PLL1DIV2, CLKSEL(10), 7, 3, mclk400_table, 0, -1}, + {"mclk200", M10V_PLL1DIV2, CLKSEL(10), 3, 4, mclk200_table, 0, -1}, + {"aclk400", M10V_PLL1DIV2, CLKSEL(10), 0, 3, aclk400_table, 0, -1}, + {"aclk300", M10V_PLL2DIV2, CLKSEL(12), 0, 2, aclk300_table, 0, -1}, + {"aclk", M10V_PLL1DIV2, CLKSEL(9), 20, 4, aclk_table, 0, M10V_ACLK_ID}, + {"aclkexs", M10V_PLL1DIV2, CLKSEL(9), 16, 4, aclkexs_table, 0, -1}, + {"hclk", M10V_PLL1DIV2, CLKSEL(9), 7, 5, hclk_table, 0, M10V_HCLK_ID}, + {"hclkbmh", M10V_PLL1DIV2, CLKSEL(9), 12, 4, hclkbmh_table, 0, -1}, + {"pclk", M10V_PLL1DIV2, CLKSEL(9), 0, 7, pclk_table, 0, M10V_PCLK_ID}, + {"uhs1clk0", M10V_PLL7, CLKSEL(1), 3, 5, uhs1clk0_table, 0, -1}, + {"uhs2clk", M10V_PLL6DIV3, CLKSEL(1), 18, 4, uhs2clk_table, 0, -1}, +}; + +static const struct m10v_clk_mux_factors m10v_mux_factor_data[] = { + {"spi", spi_mux_names, ARRAY_SIZE(spi_mux_names), + CLKSEL(8), 3, 7, spi_mux_table, 0, M10V_SPICLK_ID}, + {"uhs1clk2", uhs1clk2_mux_names, ARRAY_SIZE(uhs1clk2_mux_names), + CLKSEL(1), 13, 31, uhs1clk2_mux_table, 0, -1}, + {"uhs1clk1", uhs1clk1_mux_names, ARRAY_SIZE(uhs1clk1_mux_names), + CLKSEL(1), 8, 31, uhs1clk1_mux_table, 0, -1}, + {"nfclk", nfclk_mux_names, ARRAY_SIZE(nfclk_mux_names), + CLKSEL(1), 22, 127, nfclk_mux_table, 0, M10V_NFCLK_ID}, +}; + +static u8 m10v_mux_get_parent(struct clk_hw *hw) +{ + struct clk_mux *mux = to_clk_mux(hw); + u32 val; + + val = clk_readl(mux->reg) >> mux->shift; + val &= mux->mask; + + return clk_mux_val_to_index(hw, mux->table, mux->flags, val); +} + +static int m10v_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_mux *mux = to_clk_mux(hw); + u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); + unsigned long flags = 0; + u32 reg; + u32 write_en = BIT(fls(mux->mask) - 1); + + if (mux->lock) + spin_lock_irqsave(mux->lock, flags); + else + __acquire(mux->lock); + + reg = clk_readl(mux->reg); + reg &= ~(mux->mask << mux->shift); + + val = (val | write_en) << mux->shift; + reg |= val; + clk_writel(reg, mux->reg); + + if (mux->lock) + spin_unlock_irqrestore(mux->lock, flags); + else + __release(mux->lock); + + return 0; +} + +static const struct clk_ops m10v_mux_ops = { + .get_parent = m10v_mux_get_parent, + .set_parent = m10v_mux_set_parent, + .determine_rate = __clk_mux_determine_rate, +}; + +static struct clk_hw *m10v_clk_hw_register_mux(struct device *dev, + const char *name, const char * const *parent_names, + u8 num_parents, unsigned long flags, void __iomem *reg, + u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, + spinlock_t *lock) +{ + struct clk_mux *mux; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + mux = kzalloc(sizeof(*mux), GFP_KERNEL); + if (!mux) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &m10v_mux_ops; + init.flags = flags; + init.parent_names = parent_names; + init.num_parents = num_parents; + + mux->reg = reg; + mux->shift = shift; + mux->mask = mask; + mux->flags = clk_mux_flags; + mux->lock = lock; + mux->table = table; + mux->hw.init = &init; + + hw = &mux->hw; + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(mux); + hw = ERR_PTR(ret); + } + + return hw; + +} + +struct m10v_clk_divider { + struct clk_hw hw; + void __iomem *reg; + u8 shift; + u8 width; + u8 flags; + const struct clk_div_table *table; + spinlock_t *lock; + void __iomem *write_valid_reg; +}; + +static unsigned long m10v_clk_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct m10v_clk_divider *divider = to_m10v_div(hw); + unsigned int val; + + val = clk_readl(divider->reg) >> divider->shift; + val &= clk_div_mask(divider->width); + + return divider_recalc_rate(hw, parent_rate, val, divider->table, + divider->flags, divider->width); +} + +static long m10v_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct m10v_clk_divider *divider = to_m10v_div(hw); + + /* if read only, just return current value */ + if (divider->flags & CLK_DIVIDER_READ_ONLY) { + u32 val; + + val = clk_readl(divider->reg) >> divider->shift; + val &= clk_div_mask(divider->width); + + return divider_ro_round_rate(hw, rate, prate, divider->table, + divider->width, divider->flags, + val); + } + + return divider_round_rate(hw, rate, prate, divider->table, + divider->width, divider->flags); +} + +static int m10v_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct m10v_clk_divider *divider = to_m10v_div(hw); + int value; + unsigned long flags = 0; + u32 val; + u32 write_en = BIT(divider->width - 1); + + value = divider_get_val(rate, parent_rate, divider->table, + divider->width, divider->flags); + if (value < 0) + return value; + + if (divider->lock) + spin_lock_irqsave(divider->lock, flags); + else + __acquire(divider->lock); + + val = clk_readl(divider->reg); + val &= ~(clk_div_mask(divider->width) << divider->shift); + + val |= ((u32)value | write_en) << divider->shift; + clk_writel(val, divider->reg); + + if (divider->write_valid_reg) { + clk_writel(M10V_DCHREQ, divider->write_valid_reg); + if (readl_poll_timeout(divider->write_valid_reg, val, + !val, M10V_UPOLL_RATE, M10V_UTIMEOUT)) + pr_err("%s:%s couldn't stabilize\n", + __func__, divider->hw.init->name); + } + + if (divider->lock) + spin_unlock_irqrestore(divider->lock, flags); + else + __release(divider->lock); + + return 0; +} + +static const struct clk_ops m10v_clk_divider_ops = { + .recalc_rate = m10v_clk_divider_recalc_rate, + .round_rate = m10v_clk_divider_round_rate, + .set_rate = m10v_clk_divider_set_rate, +}; + +static const struct clk_ops m10v_clk_divider_ro_ops = { + .recalc_rate = m10v_clk_divider_recalc_rate, + .round_rate = m10v_clk_divider_round_rate, +}; + +static struct clk_hw *m10v_clk_hw_register_divider(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table, + spinlock_t *lock, void __iomem *write_valid_reg) +{ + struct m10v_clk_divider *div; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + init.name = name; + if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) + init.ops = &m10v_clk_divider_ro_ops; + else + init.ops = &m10v_clk_divider_ops; + init.flags = flags; + init.parent_names = &parent_name; + init.num_parents = 1; + + div->reg = reg; + div->shift = shift; + div->width = width; + div->flags = clk_divider_flags; + div->lock = lock; + div->hw.init = &init; + div->table = table; + div->write_valid_reg = write_valid_reg; + + /* register the clock */ + hw = &div->hw; + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(div); + hw = ERR_PTR(ret); + } + + return hw; +} + +static int m10v_clk_probe(struct platform_device *pdev) +{ + int id; + struct resource *res; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct clk_hw *hw; + void __iomem *base, *write_valid_reg; + const char *parent_name; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + parent_name = of_clk_get_parent_name(np, 0); + for (id = 0; id < ARRAY_SIZE(m10v_div_factor_data); ++id) { + const struct m10v_clk_div_factors *dfd = + &m10v_div_factor_data[id]; + /* + * The registers on CLKSEL(9) or CLKSEL(10) need additional + * writing to become valid. + */ + if ((dfd->offset == CLKSEL(9)) || (dfd->offset == CLKSEL(10))) + write_valid_reg = base + CLKSEL(11); + else + write_valid_reg = NULL; + hw = m10v_clk_hw_register_divider(NULL, dfd->name, + dfd->parent_name, + CLK_SET_RATE_PARENT, + base + dfd->offset, dfd->shift, + dfd->width, dfd->div_flags, dfd->table, + &m10v_crglock, write_valid_reg); + if (dfd->onecell_idx >= 0) + m10v_clk_data->hws[dfd->onecell_idx] = hw; + } + for (id = 0; id < ARRAY_SIZE(m10v_div_fixed_data); ++id) { + const struct m10v_clk_div_fixed_data *dfd = + &m10v_div_fixed_data[id]; + const char *pn = dfd->parent_name ? + dfd->parent_name : parent_name; + hw = clk_hw_register_fixed_factor(NULL, dfd->name, + pn, 0, dfd->mult, dfd->div); + if (dfd->onecell_idx >= 0) + m10v_clk_data->hws[dfd->onecell_idx] = hw; + } + for (id = 0; id < ARRAY_SIZE(m10v_mux_factor_data); ++id) { + const struct m10v_clk_mux_factors *mfd = + &m10v_mux_factor_data[id]; + hw = m10v_clk_hw_register_mux(NULL, mfd->name, + mfd->parent_names, mfd->num_parents, + CLK_SET_RATE_PARENT, + base + mfd->offset, mfd->shift, + mfd->mask, mfd->mux_flags, mfd->table, + &m10v_crglock); + if (mfd->onecell_idx >= 0) + m10v_clk_data->hws[mfd->onecell_idx] = hw; + } + + for (id = 0; id < M10V_NUM_CLKS; id++) { + if (IS_ERR(m10v_clk_data->hws[id])) + return PTR_ERR(m10v_clk_data->hws[id]); + } + + return 0; +} + +static const struct of_device_id m10v_clk_dt_ids[] = { + { .compatible = "socionext,milbeaut-m10v-ccu", }, + { }, +}; + +static struct platform_driver m10v_clk_driver = { + .probe = m10v_clk_probe, + .driver = { + .name = "m10v-ccu", + .of_match_table = m10v_clk_dt_ids, + }, +}; +builtin_platform_driver(m10v_clk_driver); + +static void __init m10v_cc_init(struct device_node *np) +{ + int id; + void __iomem *base; + const char *parent_name; + struct clk_hw *hw; + + m10v_clk_data = kzalloc(struct_size(m10v_clk_data, hws, + M10V_NUM_CLKS), + GFP_KERNEL); + if (!m10v_clk_data) + return; + + base = of_iomap(np, 0); + parent_name = of_clk_get_parent_name(np, 0); + if (!parent_name) + return; + + /* + * This way all clocks fetched before the platform device probes, + * except those we assign here for early use, will be deferred. + */ + for (id = 0; id < M10V_NUM_CLKS; id++) + m10v_clk_data->hws[id] = ERR_PTR(-EPROBE_DEFER); + + /* + * PLLs are set by bootloader so this driver registers them as the + * fixed factor. + */ + for (id = 0; id < ARRAY_SIZE(m10v_pll_fixed_data); ++id) { + const struct m10v_clk_pll_factors *pfd = + &m10v_pll_fixed_data[id]; + hw = clk_hw_register_fixed_factor(NULL, pfd->name, + pfd->parent_name ? pfd->parent_name : parent_name, + 0, pfd->mult, pfd->div); + } + + /* + * timer consumes "rclk" so it needs to register here. + */ + hw = m10v_clk_hw_register_divider(NULL, "rclk", M10V_PLL10DIV2, 0, + base + CLKSEL(1), 0, 3, 0, rclk_table, + &m10v_crglock, 0); + m10v_clk_data->hws[M10V_RCLK_ID] = hw; + + m10v_clk_data->num = M10V_NUM_CLKS; + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, m10v_clk_data); +} +CLK_OF_DECLARE_DRIVER(m10v_cc, "socionext,milbeaut-m10v-ccu", m10v_cc_init); From patchwork Fri Feb 8 12:27:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10803007 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 985C9746 for ; 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Fri, 8 Feb 2019 21:26:45 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:26:45 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 4FAA31A04E1; Fri, 8 Feb 2019 21:26:45 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 380C51202F1; Fri, 8 Feb 2019 21:26:45 +0900 (JST) From: Sugaya Taichi To: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/15] dt-bindings: serial: Add Milbeaut serial driver description Date: Fri, 8 Feb 2019 21:27:29 +0900 Message-Id: <1549628849-31726-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_042646_867188_D034860E X-CRM114-Status: GOOD ( 16.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Shinji Kanematsu , Masami Hiramatsu , Sugaya Taichi , Greg Kroah-Hartman , Jassi Brar , Rob Herring , Takao Orito , Kazuhiro Kasai MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add DT bindings document for Milbeaut serial driver. Signed-off-by: Sugaya Taichi --- .../devicetree/bindings/serial/milbeaut-uart.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt diff --git a/Documentation/devicetree/bindings/serial/milbeaut-uart.txt b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt new file mode 100644 index 0000000..8f61c38 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt @@ -0,0 +1,21 @@ +Socionext Milbeaut UART controller + +Required properties: +- compatible: should be "socionext,milbeaut-usio-uart". +- reg: offset and length of the register set for the device. +- interrupts: two interrupts specifier. +- clocks: phandle to the input clock. +- interrupt-names: should be "rx", "tx". + +Optional properties: +- uart-flow-enable: flow control enable. + +Example: + usio1: usio_uart@1e700010 { + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&clk 2>; + uart-flow-enable; + }; From patchwork Fri Feb 8 12:27:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10803009 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 67A4113A4 for ; Fri, 8 Feb 2019 12:27:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5346D2DCED for ; Fri, 8 Feb 2019 12:27:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 46EA22DD0E; Fri, 8 Feb 2019 12:27:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2764D2DCED for ; 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Fri, 08 Feb 2019 12:27:45 +0000 Received: from mx.socionext.com ([202.248.49.38]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gs5FA-0008Mk-6r for linux-arm-kernel@lists.infradead.org; Fri, 08 Feb 2019 12:27:09 +0000 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:26:55 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 3A89B180D62; Fri, 8 Feb 2019 21:26:55 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:26:55 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id DD6B34036D; Fri, 8 Feb 2019 21:26:54 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id C89A51217C2; Fri, 8 Feb 2019 21:26:54 +0900 (JST) From: Sugaya Taichi To: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 10/15] serial: Add Milbeaut serial control Date: Fri, 8 Feb 2019 21:27:40 +0900 Message-Id: <1549628860-31903-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_042657_582721_F9E46EC4 X-CRM114-Status: GOOD ( 26.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shinji Kanematsu , Masami Hiramatsu , Sugaya Taichi , Greg Kroah-Hartman , Jiri Slaby , Jassi Brar , Takao Orito , Kazuhiro Kasai MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add Milbeaut serial control including earlycon and console. Signed-off-by: Sugaya Taichi --- drivers/tty/serial/Kconfig | 25 ++ drivers/tty/serial/Makefile | 1 + drivers/tty/serial/milbeaut_usio.c | 621 +++++++++++++++++++++++++++++++++++++ include/uapi/linux/serial_core.h | 3 + 4 files changed, 650 insertions(+) create mode 100644 drivers/tty/serial/milbeaut_usio.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 089a6f2..1420195 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1560,6 +1560,31 @@ config SERIAL_RDA_CONSOLE Say 'Y' here if you wish to use the RDA8810PL UART as the system console. Only earlycon is implemented currently. +config SERIAL_MILBEAUT_USIO + tristate "Milbeaut USIO/UART serial port support" + depends on ARCH_MILBEAUT + default y + select SERIAL_CORE + help + This selects the USIO/UART IP found in Socionext Milbeaut SoCs. + +config SERIAL_MILBEAUT_USIO_PORTS + int "Maximum number of CSIO/UART ports (1-8)" + range 1 8 + depends on SERIAL_MILBEAUT_USIO + default "4" + +config SERIAL_MILBEAUT_USIO_CONSOLE + bool "Support for console on MILBEAUT USIO/UART serial port" + depends on SERIAL_MILBEAUT_USIO=y + select SERIAL_CORE_CONSOLE + select SERIAL_EARLYCON + help + Say 'Y' here if you wish to use a USIO/UART of Socionext Milbeaut + SoCs as the system console (the system console is the device which + receives all kernel messages and warnings and which allows logins in + single user mode). + endmenu config SERIAL_MCTRL_GPIO diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 1511e8a..fd6fdbe 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -91,6 +91,7 @@ obj-$(CONFIG_SERIAL_PIC32) += pic32_uart.o obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o obj-$(CONFIG_SERIAL_OWL) += owl-uart.o obj-$(CONFIG_SERIAL_RDA) += rda-uart.o +obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o # GPIOLIB helpers for modem control lines obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o diff --git a/drivers/tty/serial/milbeaut_usio.c b/drivers/tty/serial/milbeaut_usio.c new file mode 100644 index 0000000..43729ee --- /dev/null +++ b/drivers/tty/serial/milbeaut_usio.c @@ -0,0 +1,621 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Socionext Inc. + */ + +#if defined(CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + +#define USIO_NAME "mlb-usio-uart" +#define USIO_UART_DEV_NAME "ttyUSI" + +static struct uart_port mlb_usio_ports[CONFIG_SERIAL_MILBEAUT_USIO_PORTS]; + +#define RX 0 +#define TX 1 +static int mlb_usio_irq[CONFIG_SERIAL_MILBEAUT_USIO_PORTS][2]; + +#define MLB_USIO_REG_SMR 0 +#define MLB_USIO_REG_SCR 1 +#define MLB_USIO_REG_ESCR 2 +#define MLB_USIO_REG_SSR 3 +#define MLB_USIO_REG_DR 4 +#define MLB_USIO_REG_BGR 6 +#define MLB_USIO_REG_FCR 12 +#define MLB_USIO_REG_FBYTE 14 + +#define MLB_USIO_SMR_SOE BIT(0) +#define MLB_USIO_SMR_SBL BIT(3) +#define MLB_USIO_SCR_TXE BIT(0) +#define MLB_USIO_SCR_RXE BIT(1) +#define MLB_USIO_SCR_TBIE BIT(2) +#define MLB_USIO_SCR_TIE BIT(3) +#define MLB_USIO_SCR_RIE BIT(4) +#define MLB_USIO_SCR_UPCL BIT(7) +#define MLB_USIO_ESCR_L_8BIT 0 +#define MLB_USIO_ESCR_L_5BIT 1 +#define MLB_USIO_ESCR_L_6BIT 2 +#define MLB_USIO_ESCR_L_7BIT 3 +#define MLB_USIO_ESCR_P BIT(3) +#define MLB_USIO_ESCR_PEN BIT(4) +#define MLB_USIO_ESCR_FLWEN BIT(7) +#define MLB_USIO_SSR_TBI BIT(0) +#define MLB_USIO_SSR_TDRE BIT(1) +#define MLB_USIO_SSR_RDRF BIT(2) +#define MLB_USIO_SSR_ORE BIT(3) +#define MLB_USIO_SSR_FRE BIT(4) +#define MLB_USIO_SSR_PE BIT(5) +#define MLB_USIO_SSR_REC BIT(7) +#define MLB_USIO_SSR_BRK BIT(8) +#define MLB_USIO_FCR_FE1 BIT(0) +#define MLB_USIO_FCR_FE2 BIT(1) +#define MLB_USIO_FCR_FCL1 BIT(2) +#define MLB_USIO_FCR_FCL2 BIT(3) +#define MLB_USIO_FCR_FSET BIT(4) +#define MLB_USIO_FCR_FTIE BIT(9) +#define MLB_USIO_FCR_FDRQ BIT(10) +#define MLB_USIO_FCR_FRIIE BIT(11) + +static void mlb_usio_stop_tx(struct uart_port *port) +{ + writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, + port->membase + MLB_USIO_REG_FCR); + writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE, + port->membase + MLB_USIO_REG_SCR); +} + +static void mlb_usio_tx_chars(struct uart_port *port) +{ + struct circ_buf *xmit = &port->state->xmit; + int count; + + writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, + port->membase + MLB_USIO_REG_FCR); + writeb(readb(port->membase + MLB_USIO_REG_SCR) & + ~(MLB_USIO_SCR_TIE | MLB_USIO_SCR_TBIE), + port->membase + MLB_USIO_REG_SCR); + + if (port->x_char) { + writew(port->x_char, port->membase + MLB_USIO_REG_DR); + port->icount.tx++; + port->x_char = 0; + return; + } + if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { + mlb_usio_stop_tx(port); + return; + } + + count = port->fifosize - + (readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff); + + do { + writew(xmit->buf[xmit->tail], port->membase + MLB_USIO_REG_DR); + + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + if (uart_circ_empty(xmit)) + break; + + } while (--count > 0); + + writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FDRQ, + port->membase + MLB_USIO_REG_FCR); + + writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE, + port->membase + MLB_USIO_REG_SCR); + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); + + if (uart_circ_empty(xmit)) + mlb_usio_stop_tx(port); +} + +static void mlb_usio_start_tx(struct uart_port *port) +{ + u16 fcr = readw(port->membase + MLB_USIO_REG_FCR); + + writew(fcr | MLB_USIO_FCR_FTIE, port->membase + MLB_USIO_REG_FCR); + if (!(fcr & MLB_USIO_FCR_FDRQ)) + return; + + writeb(readb(port->membase + MLB_USIO_REG_SCR) | MLB_USIO_SCR_TBIE, + port->membase + MLB_USIO_REG_SCR); + + if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI) + mlb_usio_tx_chars(port); +} + +static void mlb_usio_stop_rx(struct uart_port *port) +{ + writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_RIE, + port->membase + MLB_USIO_REG_SCR); +} + +static void mlb_usio_enable_ms(struct uart_port *port) +{ + writeb(readb(port->membase + MLB_USIO_REG_SCR) | + MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE, + port->membase + MLB_USIO_REG_SCR); +} + +static void mlb_usio_rx_chars(struct uart_port *port) +{ + struct tty_port *ttyport = &port->state->port; + unsigned long flag = 0; + char ch = 0; + u8 status; + int max_count = 2; + + while (max_count--) { + status = readb(port->membase + MLB_USIO_REG_SSR); + + if (!(status & MLB_USIO_SSR_RDRF)) + break; + + if (!(status & (MLB_USIO_SSR_ORE | MLB_USIO_SSR_FRE | + MLB_USIO_SSR_PE))) { + ch = readw(port->membase + MLB_USIO_REG_DR); + flag = TTY_NORMAL; + port->icount.rx++; + if (uart_handle_sysrq_char(port, ch)) + continue; + uart_insert_char(port, status, MLB_USIO_SSR_ORE, + ch, flag); + continue; + } + if (status & MLB_USIO_SSR_PE) + port->icount.parity++; + if (status & MLB_USIO_SSR_ORE) + port->icount.overrun++; + status &= port->read_status_mask; + if (status & MLB_USIO_SSR_BRK) { + flag = TTY_BREAK; + ch = 0; + } else + if (status & MLB_USIO_SSR_PE) { + flag = TTY_PARITY; + ch = 0; + } else + if (status & MLB_USIO_SSR_FRE) { + flag = TTY_FRAME; + ch = 0; + } + if (flag) + uart_insert_char(port, status, MLB_USIO_SSR_ORE, + ch, flag); + + writeb(readb(port->membase + MLB_USIO_REG_SSR) | + MLB_USIO_SSR_REC, + port->membase + MLB_USIO_REG_SSR); + + max_count = readw(port->membase + MLB_USIO_REG_FBYTE) >> 8; + writew(readw(port->membase + MLB_USIO_REG_FCR) | + MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE, + port->membase + MLB_USIO_REG_FCR); + } + + tty_flip_buffer_push(ttyport); +} + +static irqreturn_t mlb_usio_rx_irq(int irq, void *dev_id) +{ + struct uart_port *port = dev_id; + + spin_lock(&port->lock); + mlb_usio_rx_chars(port); + spin_unlock(&port->lock); + + return IRQ_HANDLED; +} + +static irqreturn_t mlb_usio_tx_irq(int irq, void *dev_id) +{ + struct uart_port *port = dev_id; + + spin_lock(&port->lock); + if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI) + mlb_usio_tx_chars(port); + spin_unlock(&port->lock); + + return IRQ_HANDLED; +} + +static unsigned int mlb_usio_tx_empty(struct uart_port *port) +{ + return (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI) ? + TIOCSER_TEMT : 0; +} + +static void mlb_usio_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ +} + +static unsigned int mlb_usio_get_mctrl(struct uart_port *port) +{ + return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; + +} + +static void mlb_usio_break_ctl(struct uart_port *port, int break_state) +{ +} + +static int mlb_usio_startup(struct uart_port *port) +{ + const char *portname = to_platform_device(port->dev)->name; + unsigned long flags; + int ret, index = port->line; + unsigned char escr; + + ret = request_irq(mlb_usio_irq[index][RX], mlb_usio_rx_irq, + 0, portname, port); + if (ret) + return ret; + ret = request_irq(mlb_usio_irq[index][TX], mlb_usio_tx_irq, + 0, portname, port); + if (ret) { + free_irq(mlb_usio_irq[index][RX], port); + return ret; + } + + escr = readb(port->membase + MLB_USIO_REG_ESCR); + if (of_property_read_bool(port->dev->of_node, "uart-flow-enable")) + escr |= MLB_USIO_ESCR_FLWEN; + spin_lock_irqsave(&port->lock, flags); + writeb(0, port->membase + MLB_USIO_REG_SCR); + writeb(escr, port->membase + MLB_USIO_REG_ESCR); + writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR); + writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR); + writew(0, port->membase + MLB_USIO_REG_FCR); + writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2, + port->membase + MLB_USIO_REG_FCR); + writew(MLB_USIO_FCR_FE1 | MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE, + port->membase + MLB_USIO_REG_FCR); + writew(0, port->membase + MLB_USIO_REG_FBYTE); + writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE); + + writeb(MLB_USIO_SCR_TXE | MLB_USIO_SCR_RIE | MLB_USIO_SCR_TBIE | + MLB_USIO_SCR_RXE, port->membase + MLB_USIO_REG_SCR); + spin_unlock_irqrestore(&port->lock, flags); + + return 0; +} + +static void mlb_usio_shutdown(struct uart_port *port) +{ + int index = port->line; + + free_irq(mlb_usio_irq[index][RX], port); + free_irq(mlb_usio_irq[index][TX], port); +} + +static void mlb_usio_set_termios(struct uart_port *port, + struct ktermios *termios, struct ktermios *old) +{ + unsigned int escr, smr = MLB_USIO_SMR_SOE; + unsigned long flags, baud, quot; + + switch (termios->c_cflag & CSIZE) { + case CS5: + escr = MLB_USIO_ESCR_L_5BIT; + break; + case CS6: + escr = MLB_USIO_ESCR_L_6BIT; + break; + case CS7: + escr = MLB_USIO_ESCR_L_7BIT; + break; + case CS8: + default: + escr = MLB_USIO_ESCR_L_8BIT; + break; + } + + if (termios->c_cflag & CSTOPB) + smr |= MLB_USIO_SMR_SBL; + + if (termios->c_cflag & PARENB) { + escr |= MLB_USIO_ESCR_PEN; + if (termios->c_cflag & PARODD) + escr |= MLB_USIO_ESCR_P; + } + /* Set hard flow control */ + if (of_property_read_bool(port->dev->of_node, "uart-flow-enable") || + (termios->c_cflag & CRTSCTS)) + escr |= MLB_USIO_ESCR_FLWEN; + + baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk); + if (baud > 1) + quot = port->uartclk / baud - 1; + else + quot = 0; + + spin_lock_irqsave(&port->lock, flags); + uart_update_timeout(port, termios->c_cflag, baud); + port->read_status_mask = MLB_USIO_SSR_ORE | MLB_USIO_SSR_RDRF | + MLB_USIO_SSR_TDRE; + if (termios->c_iflag & INPCK) + port->read_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE; + + port->ignore_status_mask = 0; + if (termios->c_iflag & IGNPAR) + port->ignore_status_mask |= MLB_USIO_SSR_FRE | MLB_USIO_SSR_PE; + if ((termios->c_iflag & IGNBRK) && (termios->c_iflag & IGNPAR)) + port->ignore_status_mask |= MLB_USIO_SSR_ORE; + if ((termios->c_cflag & CREAD) == 0) + port->ignore_status_mask |= MLB_USIO_SSR_RDRF; + + writeb(0, port->membase + MLB_USIO_REG_SCR); + writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR); + writeb(MLB_USIO_SSR_REC, port->membase + MLB_USIO_REG_SSR); + writew(0, port->membase + MLB_USIO_REG_FCR); + writeb(smr, port->membase + MLB_USIO_REG_SMR); + writeb(escr, port->membase + MLB_USIO_REG_ESCR); + writew(quot, port->membase + MLB_USIO_REG_BGR); + writew(0, port->membase + MLB_USIO_REG_FCR); + writew(MLB_USIO_FCR_FCL1 | MLB_USIO_FCR_FCL2 | MLB_USIO_FCR_FE1 | + MLB_USIO_FCR_FE2 | MLB_USIO_FCR_FRIIE, + port->membase + MLB_USIO_REG_FCR); + writew(0, port->membase + MLB_USIO_REG_FBYTE); + writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE); + writeb(MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE | MLB_USIO_SCR_TBIE | + MLB_USIO_SCR_TXE, port->membase + MLB_USIO_REG_SCR); + spin_unlock_irqrestore(&port->lock, flags); +} + +static const char *mlb_usio_type(struct uart_port *port) +{ + return ((port->type == PORT_MLB_USIO) ? USIO_NAME : NULL); +} + +static void mlb_usio_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE) + port->type = PORT_MLB_USIO; +} + +static const struct uart_ops mlb_usio_ops = { + .tx_empty = mlb_usio_tx_empty, + .set_mctrl = mlb_usio_set_mctrl, + .get_mctrl = mlb_usio_get_mctrl, + .stop_tx = mlb_usio_stop_tx, + .start_tx = mlb_usio_start_tx, + .stop_rx = mlb_usio_stop_rx, + .enable_ms = mlb_usio_enable_ms, + .break_ctl = mlb_usio_break_ctl, + .startup = mlb_usio_startup, + .shutdown = mlb_usio_shutdown, + .set_termios = mlb_usio_set_termios, + .type = mlb_usio_type, + .config_port = mlb_usio_config_port, +}; + +#ifdef CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE + +static void mlb_usio_console_putchar(struct uart_port *port, int c) +{ + while (!(readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TDRE)) + cpu_relax(); + + writew(c, port->membase + MLB_USIO_REG_DR); +} + +static void mlb_usio_console_write(struct console *co, const char *s, + unsigned int count) +{ + struct uart_port *port = &mlb_usio_ports[co->index]; + + uart_console_write(port, s, count, mlb_usio_console_putchar); +} + +static int __init mlb_usio_console_setup(struct console *co, char *options) +{ + struct uart_port *port; + int baud = 115200; + int parity = 'n'; + int flow = 'n'; + int bits = 8; + + if (co->index >= CONFIG_SERIAL_MILBEAUT_USIO_PORTS) + return -ENODEV; + + port = &mlb_usio_ports[co->index]; + if (!port->membase) + return -ENODEV; + + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + if (of_property_read_bool(port->dev->of_node, "uart-flow-enable")) + flow = 'r'; + + return uart_set_options(port, co, baud, parity, bits, flow); +} + + +static struct uart_driver mlb_usio_uart_driver; +static struct console mlb_usio_console = { + .name = USIO_UART_DEV_NAME, + .write = mlb_usio_console_write, + .device = uart_console_device, + .setup = mlb_usio_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &mlb_usio_uart_driver, +}; + +static int __init mlb_usio_console_init(void) +{ + register_console(&mlb_usio_console); + return 0; +} +console_initcall(mlb_usio_console_init); + + +static void mlb_usio_early_console_write(struct console *co, const char *s, + u_int count) +{ + struct earlycon_device *dev = co->data; + + uart_console_write(&dev->port, s, count, mlb_usio_console_putchar); +} + +static int __init mlb_usio_early_console_setup(struct earlycon_device *device, + const char *opt) +{ + if (!device->port.membase) + return -ENODEV; + device->con->write = mlb_usio_early_console_write; + return 0; +} + +OF_EARLYCON_DECLARE(mlb_usio, "socionext,milbeaut-usio-uart", + mlb_usio_early_console_setup); + +#define USIO_CONSOLE (&mlb_usio_console) +#else +#define USIO_CONSOLE NULL +#endif + +static struct uart_driver mlb_usio_uart_driver = { + .owner = THIS_MODULE, + .driver_name = USIO_NAME, + .dev_name = USIO_UART_DEV_NAME, + .cons = USIO_CONSOLE, + .nr = CONFIG_SERIAL_MILBEAUT_USIO_PORTS, +}; + +static int mlb_usio_probe(struct platform_device *pdev) +{ + struct clk *clk = devm_clk_get(&pdev->dev, 0); + struct uart_port *port; + struct resource *res; + int index = 0; + int ret; + + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "Missing clock\n"); + return PTR_ERR(clk); + } + ret = clk_prepare_enable(clk); + if (ret) { + dev_err(&pdev->dev, "Clock enable failed: %d\n", ret); + return ret; + } + of_property_read_u32(pdev->dev.of_node, "index", &index); + port = &mlb_usio_ports[index]; + + port->private_data = (void *)clk; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "Missing regs\n"); + ret = -ENODEV; + goto failed; + } + port->mapbase = res->start; + port->membase = ioremap(res->start, (res->end - res->start + 1)); + port->membase = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + + ret = platform_get_irq_byname(pdev, "rx"); + mlb_usio_irq[index][RX] = ret; + + ret = platform_get_irq_byname(pdev, "tx"); + mlb_usio_irq[index][TX] = ret; + + port->irq = mlb_usio_irq[index][RX]; + port->uartclk = clk_get_rate(clk); + port->fifosize = 128; + port->iotype = UPIO_MEM32; + port->flags = UPF_BOOT_AUTOCONF | UPF_SPD_VHI; + port->line = index; + port->ops = &mlb_usio_ops; + port->dev = &pdev->dev; + + ret = uart_add_one_port(&mlb_usio_uart_driver, port); + if (ret) { + dev_err(&pdev->dev, "Adding port failed: %d\n", ret); + goto failed1; + } + return 0; + +failed1: + iounmap(port->membase); + +failed: + clk_disable_unprepare(clk); + clk_put(clk); + + return ret; +} + +static int mlb_usio_remove(struct platform_device *pdev) +{ + struct uart_port *port = &mlb_usio_ports[pdev->id]; + struct clk *clk = port->private_data; + + uart_remove_one_port(&mlb_usio_uart_driver, port); + clk_disable_unprepare(clk); + clk_put(clk); + + return 0; +} + +static const struct of_device_id mlb_usio_dt_ids[] = { + { .compatible = "socionext,milbeaut-usio-uart" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mlb_usio_dt_ids); + +static struct platform_driver mlb_usio_driver = { + .probe = mlb_usio_probe, + .remove = mlb_usio_remove, + .driver = { + .name = USIO_NAME, + .of_match_table = mlb_usio_dt_ids, + }, +}; + +static int __init mlb_usio_init(void) +{ + int ret = uart_register_driver(&mlb_usio_uart_driver); + + if (ret) { + pr_err("%s: uart registration failed: %d\n", __func__, ret); + return ret; + } + ret = platform_driver_register(&mlb_usio_driver); + if (ret) { + uart_unregister_driver(&mlb_usio_uart_driver); + pr_err("%s: drv registration failed: %d\n", __func__, ret); + return ret; + } + + return 0; +} + +static void __exit mlb_usio_exit(void) +{ + platform_driver_unregister(&mlb_usio_driver); + uart_unregister_driver(&mlb_usio_uart_driver); +} + +module_init(mlb_usio_init); +module_exit(mlb_usio_exit); + +MODULE_AUTHOR("SOCIONEXT"); +MODULE_DESCRIPTION("MILBEAUT_USIO/UART Driver"); +MODULE_LICENSE("GPL"); diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index df4a753..0f8a3bf 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -284,4 +284,7 @@ /* RDA UART */ #define PORT_RDA 118 +/* Socionext Milbeaut UART */ +#define PORT_MLB_USIO 119 + #endif /* _UAPILINUX_SERIAL_CORE_H */ From patchwork Fri Feb 8 12:33:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10803021 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 729A213BF for ; Fri, 8 Feb 2019 12:32:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6115A2DE6E for ; Fri, 8 Feb 2019 12:32:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 50BAE2DEA4; Fri, 8 Feb 2019 12:32:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 27C7F2DEA4 for ; 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Fri, 08 Feb 2019 12:32:26 +0000 Received: from mx.socionext.com ([202.248.49.38]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gs5KR-0004ne-V5 for linux-arm-kernel@lists.infradead.org; Fri, 08 Feb 2019 12:32:25 +0000 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:32:23 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 26F8560062; Fri, 8 Feb 2019 21:32:23 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:32:23 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id E6D174036D; Fri, 8 Feb 2019 21:32:22 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id CDC701202F1; Fri, 8 Feb 2019 21:32:22 +0900 (JST) From: Sugaya Taichi To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 11/15] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description Date: Fri, 8 Feb 2019 21:33:07 +0900 Message-Id: <1549629187-3177-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_043224_126716_D9FFC3FE X-CRM114-Status: GOOD ( 17.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Shinji Kanematsu , Masami Hiramatsu , Sugaya Taichi , Linus Walleij , Jassi Brar , Rob Herring , Takao Orito , Kazuhiro Kasai MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add DT bindings document for Milbeaut M10V pinctrl. Signed-off-by: Sugaya Taichi --- .../pinctrl/socionext,milbeaut-pinctrl.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt new file mode 100644 index 0000000..6b54191 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt @@ -0,0 +1,35 @@ +Milbeaut SoCs pin controller + +Required properties: +- compatible: should be one of the following: + "socionext,milbeaut-m10v-pinctrl" - for m10v SoC +- reg: offset and length of the register set. +- reg-names: should be "pinctrl", "exiu". +- gpio-controller: marks the device node as a gpio controller. +- gpio-cells: should be 2. +- interrupt-controller: marks the device node as a interrupt controller. +- interrupt-cells: should be 2. +- clocks: phandle to the input clock. +- interrupts: three interrupts specifer. +- interrupt-names: corresponds "interrupts" factor. + +Example: + pinctrl: pinctrl@1d022000 { + compatible = "socionext,milbeaut-m10v-pinctrl"; + reg = <0x1d022000 0x1000>, + <0x1c26f000 0x1000>; + reg-names = "pinctrl", "exiu"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk 2>; + interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>, + <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>, + <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>, + <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>; + interrupt-names = "pin-48", "pin-49", "pin-50", "pin-51", + "pin-52", "pin-53", "pin-54", "pin-55", + "pin-56", "pin-57", "pin-58", "pin-59", + "pin-60", "pin-61", "pin-62", "pin-63"; + } From patchwork Fri Feb 8 12:28:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10803011 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 78A21746 for ; Fri, 8 Feb 2019 12:28:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 636262DCED for ; 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Fri, 8 Feb 2019 21:27:39 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:27:39 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 30DD41A04E1; Fri, 8 Feb 2019 21:27:39 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 1D2681202F1; Fri, 8 Feb 2019 21:27:39 +0900 (JST) From: Sugaya Taichi To: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 12/15] pinctrl: milbeaut: Add Milbeaut M10V pinctrl Date: Fri, 8 Feb 2019 21:28:17 +0900 Message-Id: <1549628897-32345-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_042741_457008_971DA958 X-CRM114-Status: GOOD ( 24.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shinji Kanematsu , Masami Hiramatsu , Sugaya Taichi , Linus Walleij , Jassi Brar , Takao Orito , Kazuhiro Kasai MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add Milbeaut M10V pinctrl. The M10V has the pins that can be used GPIOs or take multiple other functions. Signed-off-by: Sugaya Taichi --- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-milbeaut.c | 759 +++++++++++++++++++++++++++++++++++++ 3 files changed, 769 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-milbeaut.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 2764d71..d968910 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -177,6 +177,15 @@ config PINCTRL_OXNAS select GPIOLIB_IRQCHIP select MFD_SYSCON +config PINCTRL_MILBEAUT + bool + select PINMUX + select PINCONF + select GENERIC_PINCONF + select OF_GPIO + select REGMAP_MMIO + select GPIOLIB_IRQCHIP + config PINCTRL_ROCKCHIP bool select PINMUX diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 712184b..ade9aea 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o obj-$(CONFIG_PINCTRL_MESON) += meson/ +obj-$(CONFIG_PINCTRL_MILBEAUT) += pinctrl-milbeaut.o obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o diff --git a/drivers/pinctrl/pinctrl-milbeaut.c b/drivers/pinctrl/pinctrl-milbeaut.c new file mode 100644 index 0000000..c9a7da4 --- /dev/null +++ b/drivers/pinctrl/pinctrl-milbeaut.c @@ -0,0 +1,759 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Socionext Inc. + * Copyright (C) 2015 Linaro Ltd. + * Author: Jassi Brar + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-utils.h" + +#define EIMASK 0x0 +#define EISRCSEL 0x4 +#define EIREQSTA 0x8 +#define EIRAWREQSTA 0xc +#define EIREQCLR 0x10 +#define EILVL 0x14 +#define EIEDG 0x18 +#define EISIR 0x1c + +#define PDR 0x0 +#define PDR_S 0x50 +#define PDR_C 0xa0 +#define DDR 0x100 +#define EPCR 0x200 +#define PUDER 0x300 +#define PUDCR 0x400 + +#define M10V_BANKS 26 +#define PINS_PER_BANK 8 +#define M10V_TOTAL_PINS (M10V_BANKS * PINS_PER_BANK) +#define PINS_PER_REG 16 + +struct pin_irq_map { + int pin; /* offset of pin in the managed range */ + int irq; /* virq of the pin as fpint */ + int type; + char irqname[8]; +}; + +struct m10v_pinctrl { + void __iomem *base; + void __iomem *exiu; + struct gpio_chip gc; + struct pinctrl_desc pd; + char pin_names[4 * M10V_TOTAL_PINS]; + struct pinctrl_pin_desc pins[M10V_TOTAL_PINS]; + unsigned int gpins[M10V_TOTAL_PINS][1]; /* 1 pin-per-group */ + struct irq_domain *irqdom; + spinlock_t irq_lock, lock; + int extints; + struct pin_irq_map fpint[]; /* keep at end */ +}; + +struct milbeaut_function { + const char *name; + const char * const *groups; + unsigned int ngroups; +}; + +static const char m10v_bank_name[] = {'0', '1', '2', '3', '4', '5', '6', '7', + '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', + 'G', 'H', 'W', 'J', 'K', 'L', 'M', 'N', + 'Y', 'P'}; +static const char * const usio0_m10v_grps[] = {"PE2", "PE3", "PF0"}; +static const char * const usio1_m10v_grps[] = {"PE4", "PE5", "PF1"}; +static const char * const usio2_m10v_grps[] = {"PE0", "PE1"}; +static const char * const usio3_m10v_grps[] = {"PY0", "PY1", "PY2"}; +static const char * const usio4_m10v_grps[] = {"PP0", "PP1", "PP2"}; +static const char * const usio5_m10v_grps[] = {"PM0", "PM1", "PM3"}; +static const char * const usio6_m10v_grps[] = {"PN0", "PN1", "PN3"}; +static const char * const usio7_m10v_grps[] = {"PY3", "PY5", "PY6"}; +static const char *gpio_m10v_grps[M10V_TOTAL_PINS]; + +static const struct milbeaut_function m10v_functions[] = { +#define FUNC_M10V(fname) \ + { \ + .name = #fname, \ + .groups = fname##_m10v_grps, \ + .ngroups = ARRAY_SIZE(fname##_m10v_grps), \ + } + FUNC_M10V(gpio), /* GPIO always at index 0 */ + FUNC_M10V(usio0), + FUNC_M10V(usio1), + FUNC_M10V(usio2), + FUNC_M10V(usio3), + FUNC_M10V(usio4), + FUNC_M10V(usio5), + FUNC_M10V(usio6), + FUNC_M10V(usio7), +}; + +static const char *bank_name; +static const struct milbeaut_function *milbeaut_functions; + +static int m10v_pconf_group_set(struct pinctrl_dev *pctldev, + unsigned int group, + unsigned long *configs, + unsigned int num_configs) +{ + struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + u32 pin, val, reg, offset; + unsigned long flags; + int i; + + pin = pctl->gpins[group][0]; + reg = pin / PINS_PER_REG * 4; + offset = pin % PINS_PER_REG; + + spin_lock_irqsave(&pctl->lock, flags); + + for (i = 0; i < num_configs; i++) { + switch (pinconf_to_config_param(configs[i])) { + case PIN_CONFIG_BIAS_PULL_UP: + /* enable Pull-Up/Down resistance */ + val = readl_relaxed(pctl->base + PUDER + reg); + val |= BIT(offset); + writel_relaxed(val, pctl->base + PUDER + reg); + /* enable Pull-Up */ + val = readl_relaxed(pctl->base + PUDCR + reg); + val |= BIT(offset); + writel_relaxed(val, pctl->base + PUDCR + reg); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + /* enable Pull-Up/Down resistance */ + val = readl_relaxed(pctl->base + PUDER + reg); + val |= BIT(offset); + writel_relaxed(val, pctl->base + PUDER + reg); + /* enable Pull-Down */ + val = readl_relaxed(pctl->base + PUDCR + reg); + val &= ~BIT(offset); + writel_relaxed(val, pctl->base + PUDCR + reg); + break; + case PIN_CONFIG_BIAS_DISABLE: + val = readl_relaxed(pctl->base + PUDER + reg); + val &= ~BIT(offset); + writel_relaxed(val, pctl->base + PUDER + reg); + break; + default: + break; + } + } + + spin_unlock_irqrestore(&pctl->lock, flags); + + return 0; +} + +static const struct pinconf_ops m10v_pconf_ops = { + .pin_config_group_set = m10v_pconf_group_set, +}; + +static int m10v_pctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return M10V_TOTAL_PINS; +} + +static const char *m10v_pctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int pin) +{ + struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return &pctl->pin_names[4 * pin]; +} + +static int m10v_pctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *pins = pctl->gpins[group]; + *num_pins = 1; + return 0; +} + +static const struct pinctrl_ops m10v_pctrl_ops = { + .get_groups_count = m10v_pctrl_get_groups_count, + .get_group_name = m10v_pctrl_get_group_name, + .get_group_pins = m10v_pctrl_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int m10v_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(m10v_functions); +} + +static const char *m10v_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return milbeaut_functions[function].name; +} + +static int m10v_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned * const num_groups) +{ + *groups = milbeaut_functions[function].groups; + *num_groups = milbeaut_functions[function].ngroups; + return 0; +} + +static void _set_mux(struct m10v_pinctrl *pctl, unsigned int pin, bool gpio) +{ + u32 val, reg, offset; + unsigned long flags; + + reg = pin / PINS_PER_REG * 4; + offset = pin % PINS_PER_REG; + + reg += EPCR; + + spin_lock_irqsave(&pctl->lock, flags); + + val = readl_relaxed(pctl->base + reg); + + if (gpio) + val &= ~BIT(offset); + else + val |= BIT(offset); + + writel_relaxed(val, pctl->base + reg); + + spin_unlock_irqrestore(&pctl->lock, flags); +} + +static int m10v_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + u32 pin = pctl->gpins[group][0]; /* each group has exactly 1 pin */ + + _set_mux(pctl, pin, !function); + + return 0; +} + +static int _set_direction(struct m10v_pinctrl *pctl, + unsigned int pin, bool input) +{ + u32 val, reg, offset; + unsigned long flags; + + reg = pin / PINS_PER_REG * 4; + offset = pin % PINS_PER_REG; + + reg += DDR; + + spin_lock_irqsave(&pctl->lock, flags); + + val = readl_relaxed(pctl->base + reg); + + if (input) + val &= ~BIT(offset); + else + val |= BIT(offset); + + writel_relaxed(val, pctl->base + reg); + + spin_unlock_irqrestore(&pctl->lock, flags); + + return 0; +} + +static int +m10v_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin, bool input) +{ + struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return _set_direction(pctl, pin, input); +} + +static int +m10v_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + + _set_mux(pctl, pin, true); + return 0; +} + +static const struct pinmux_ops m10v_pmx_ops = { + .get_functions_count = m10v_pmx_get_funcs_cnt, + .get_function_name = m10v_pmx_get_func_name, + .get_function_groups = m10v_pmx_get_func_groups, + .set_mux = m10v_pmx_set_mux, + .gpio_set_direction = m10v_pmx_gpio_set_direction, + .gpio_request_enable = m10v_pmx_gpio_request_enable, +}; + +static int m10v_gpio_get(struct gpio_chip *gc, unsigned int group) +{ + struct m10v_pinctrl *pctl = + container_of(gc, struct m10v_pinctrl, gc); + u32 pin, val, reg, offset; + + pin = pctl->gpins[group][0]; + reg = PDR + pin / PINS_PER_REG * 4; + offset = pin % PINS_PER_REG; + val = readl_relaxed(pctl->base + reg); + + return !!(val & BIT(offset)); +} + +static void m10v_gpio_set(struct gpio_chip *gc, unsigned int group, int set) +{ + struct m10v_pinctrl *pctl = + container_of(gc, struct m10v_pinctrl, gc); + u32 pin, reg, offset, val; + + pin = pctl->gpins[group][0]; + reg = PDR + pin / PINS_PER_REG * 4; + offset = pin % PINS_PER_REG; + + val = BIT(offset + 16); + if (set) + val |= BIT(offset); + + writel_relaxed(val, pctl->base + reg); +} + +static void (*gpio_set)(struct gpio_chip *, unsigned int, int); + +static int m10v_gpio_direction_input(struct gpio_chip *gc, + unsigned int offset) +{ + return pinctrl_gpio_direction_input(gc->base + offset); +} + +static int m10v_gpio_direction_output(struct gpio_chip *gc, + unsigned int offset, int value) +{ + int ret; + + ret = pinctrl_gpio_direction_output(gc->base + offset); + if (!ret) + gpio_set(gc, offset, value); + + return ret; +} + +static int m10v_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) +{ + struct m10v_pinctrl *pctl = + container_of(gc, struct m10v_pinctrl, gc); + + return irq_linear_revmap(pctl->irqdom, offset); +} + +static struct lock_class_key gpio_lock_class; +static struct lock_class_key gpio_request_class; + +static int pin_to_extint(struct m10v_pinctrl *pctl, int pin) +{ + int extint; + + for (extint = 0; extint < pctl->extints; extint++) + if (pctl->fpint[extint].pin == pin) + break; + + if (extint == pctl->extints) + return -1; + + return extint; +} + +static void update_trigger(struct m10v_pinctrl *pctl, int extint) +{ + int type = pctl->fpint[extint].type; + int pin = pctl->fpint[extint].pin; + u32 masked, val, eilvl, eiedg; + int lvl; + u32 reg, offset; + + reg = pin / PINS_PER_REG * 4; + offset = pin % PINS_PER_REG; + + /* sense gpio */ + val = readl_relaxed(pctl->base + PDR + reg); + lvl = (val >> offset) & 1; + + eilvl = readl_relaxed(pctl->exiu + EILVL); + eiedg = readl_relaxed(pctl->exiu + EIEDG); + + if (type == IRQ_TYPE_LEVEL_LOW || + (lvl && (type & IRQ_TYPE_LEVEL_LOW))) { + eilvl &= ~BIT(extint); + eiedg &= ~BIT(extint); + } + + if (type == IRQ_TYPE_EDGE_FALLING || + (lvl && (type & IRQ_TYPE_EDGE_FALLING))) { + eilvl &= ~BIT(extint); + eiedg |= BIT(extint); + } + + if (type == IRQ_TYPE_LEVEL_HIGH || + (!lvl && (type & IRQ_TYPE_LEVEL_HIGH))) { + eilvl |= BIT(extint); + eiedg &= ~BIT(extint); + } + + if (type == IRQ_TYPE_EDGE_RISING || + (!lvl && (type & IRQ_TYPE_EDGE_RISING))) { + eilvl |= BIT(extint); + eiedg |= BIT(extint); + } + + /* Mask the interrupt */ + val = readl_relaxed(pctl->exiu + EIMASK); + masked = val & BIT(extint); /* save status */ + val |= BIT(extint); + writel_relaxed(val, pctl->exiu + EIMASK); + + /* Program trigger */ + writel_relaxed(eilvl, pctl->exiu + EILVL); + writel_relaxed(eiedg, pctl->exiu + EIEDG); + + if (masked) + return; + + /* UnMask the interrupt */ + val = readl_relaxed(pctl->exiu + EIMASK); + val &= ~BIT(extint); + writel_relaxed(val, pctl->exiu + EIMASK); +} + +static irqreturn_t m10v_gpio_irq_handler(int irq, void *data) +{ + struct m10v_pinctrl *pctl = data; + int i, pin; + u32 val; + + for (i = 0; i < pctl->extints; i++) + if (pctl->fpint[i].irq == irq) + break; + if (i == pctl->extints) { + pr_err("%s:%d IRQ(%d)!\n", __func__, __LINE__, irq); + return IRQ_NONE; + } + + if (!pctl->exiu) + return IRQ_NONE; + + val = readl_relaxed(pctl->exiu + EIREQSTA); + if (!(val & BIT(i))) { + pr_err("%s:%d i=%d EIREQSTA=0x%x IRQ(%d)!\n", + __func__, __LINE__, i, val, irq); + return IRQ_NONE; + } + + pin = pctl->fpint[i].pin; + generic_handle_irq(irq_linear_revmap(pctl->irqdom, pin)); + + return IRQ_HANDLED; +} + +static void m10v_gpio_irq_enable(struct irq_data *data) +{ + struct m10v_pinctrl *pctl = irq_data_get_irq_chip_data(data); + int extint = pin_to_extint(pctl, irqd_to_hwirq(data)); + unsigned long flags; + u32 val; + + if (extint < 0 || !pctl->exiu) + return; + + _set_mux(pctl, irqd_to_hwirq(data), true); + _set_direction(pctl, irqd_to_hwirq(data), true); + + spin_lock_irqsave(&pctl->irq_lock, flags); + + /* Clear before enabling */ + writel_relaxed(BIT(extint), pctl->exiu + EIREQCLR); + + /* UnMask the interrupt */ + val = readl_relaxed(pctl->exiu + EIMASK); + val &= ~BIT(extint); + writel_relaxed(val, pctl->exiu + EIMASK); + + spin_unlock_irqrestore(&pctl->irq_lock, flags); +} + +static void m10v_gpio_irq_disable(struct irq_data *data) +{ + struct m10v_pinctrl *pctl = irq_data_get_irq_chip_data(data); + int extint = pin_to_extint(pctl, irqd_to_hwirq(data)); + unsigned long flags; + u32 val; + + if (extint < 0 || !pctl->exiu) + return; + + spin_lock_irqsave(&pctl->irq_lock, flags); + + /* Mask the interrupt */ + val = readl_relaxed(pctl->exiu + EIMASK); + val |= BIT(extint); + writel_relaxed(val, pctl->exiu + EIMASK); + + spin_unlock_irqrestore(&pctl->irq_lock, flags); +} + +static int m10v_gpio_irq_set_type(struct irq_data *data, unsigned int type) +{ + struct m10v_pinctrl *pctl = irq_data_get_irq_chip_data(data); + int extint = pin_to_extint(pctl, irqd_to_hwirq(data)); + unsigned long flags; + + if (extint < 0 || !pctl->exiu) + return -EINVAL; + + spin_lock_irqsave(&pctl->irq_lock, flags); + + pctl->fpint[extint].type = type; + update_trigger(pctl, extint); + + spin_unlock_irqrestore(&pctl->irq_lock, flags); + + return 0; +} + +void m10v_gpio_irq_ack(struct irq_data *data) +{ + struct m10v_pinctrl *pctl = irq_data_get_irq_chip_data(data); + int extint = pin_to_extint(pctl, irqd_to_hwirq(data)); + + if (extint < 0 || !pctl->exiu) + return; + + writel_relaxed(BIT(extint), pctl->exiu + EIREQCLR); +} + +void m10v_gpio_irq_mask(struct irq_data *data) +{ + struct m10v_pinctrl *pctl = irq_data_get_irq_chip_data(data); + int extint = pin_to_extint(pctl, irqd_to_hwirq(data)); + unsigned long flags; + u32 val; + + if (extint < 0 || !pctl->exiu) + return; + + spin_lock_irqsave(&pctl->irq_lock, flags); + + val = readl_relaxed(pctl->exiu + EIMASK); + val |= BIT(extint); + writel_relaxed(val, pctl->exiu + EIMASK); + + spin_unlock_irqrestore(&pctl->irq_lock, flags); +} + +void m10v_gpio_irq_unmask(struct irq_data *data) +{ + struct m10v_pinctrl *pctl = irq_data_get_irq_chip_data(data); + int extint = pin_to_extint(pctl, irqd_to_hwirq(data)); + unsigned long flags; + u32 val; + + if (extint < 0 || !pctl->exiu) + return; + + spin_lock_irqsave(&pctl->irq_lock, flags); + + update_trigger(pctl, extint); + + val = readl_relaxed(pctl->exiu + EIMASK); + val &= ~BIT(extint); + writel_relaxed(val, pctl->exiu + EIMASK); + + spin_unlock_irqrestore(&pctl->irq_lock, flags); +} + +static struct irq_chip m10v_gpio_irq_chip = { + .name = "m10v-pin-irq", + .irq_enable = m10v_gpio_irq_enable, + .irq_disable = m10v_gpio_irq_disable, + .irq_set_type = m10v_gpio_irq_set_type, + .irq_mask = m10v_gpio_irq_mask, + .irq_unmask = m10v_gpio_irq_unmask, + .irq_ack = m10v_gpio_irq_ack, +}; + +static const struct of_device_id m10v_pmatch[] = { + { .compatible = "socionext,milbeaut-m10v-pinctrl" }, + {}, +}; + +static int m10v_pinctrl_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct pinctrl_dev *pctl_dev; + struct pin_irq_map fpint[32]; + struct m10v_pinctrl *pctl; + struct pinctrl_desc *pd; + struct gpio_chip *gc; + struct resource *res; + int idx, i, ret, extints, tpins; + + extints = of_irq_count(np); + + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl) + + sizeof(struct pin_irq_map) * extints, + GFP_KERNEL); + if (!pctl) + return -ENOMEM; + + gpio_set = m10v_gpio_set; + bank_name = m10v_bank_name; + milbeaut_functions = m10v_functions; + tpins = M10V_TOTAL_PINS; + + pd = &pctl->pd; + gc = &pctl->gc; + spin_lock_init(&pctl->lock); + spin_lock_init(&pctl->irq_lock); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pinctrl"); + pctl->base = devm_ioremap_resource(&pdev->dev, res); + if (!pctl->base) + return -EINVAL; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "exiu"); + if (res) + pctl->exiu = devm_ioremap_resource(&pdev->dev, res); + if (res && !IS_ERR(pctl->exiu)) { + writel_relaxed(~0, pctl->exiu + EIMASK); /* mask all */ + writel_relaxed(~0, pctl->exiu + EIREQCLR); /* eoi all */ + writel_relaxed(0, pctl->exiu + EISRCSEL); /* all fpint */ + writel_relaxed(~0, pctl->exiu + EILVL); /* rising edge type*/ + writel_relaxed(~0, pctl->exiu + EIEDG); + } else { + dev_info(&pdev->dev, "continuing without EXIU support\n"); + pctl->exiu = NULL; + } + + for (i = 0; i < tpins; i++) { + pctl->pins[i].number = i; + pctl->pins[i].name = &pctl->pin_names[4 * i]; + snprintf(&pctl->pin_names[4 * i], 4, "P%c%d", + bank_name[i / PINS_PER_BANK], i % PINS_PER_BANK); + gpio_m10v_grps[i] = &pctl->pin_names[4 * i]; + pctl->gpins[i][0] = i; + } + /* absent or incomplete entries allow all access */ + pd->name = dev_name(&pdev->dev); + pd->pins = pctl->pins; + pd->npins = tpins; + pd->pctlops = &m10v_pctrl_ops; + pd->pmxops = &m10v_pmx_ops; + pd->confops = &m10v_pconf_ops; + pd->owner = THIS_MODULE; + pctl_dev = pinctrl_register(pd, &pdev->dev, pctl); + if (!pctl_dev) { + dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); + return -EINVAL; + } + + pctl->extints = extints; + + pctl->irqdom = irq_domain_add_linear(np, tpins, + &irq_domain_simple_ops, pctl); + idx = 0; + for (i = 0; i < tpins && idx < pctl->extints; i++) { + int irq; + + snprintf(fpint[idx].irqname, 8, "pin-%d", i); + irq = platform_get_irq_byname(pdev, fpint[idx].irqname); + if (irq < 0) + continue; + fpint[idx].irq = irq; + fpint[idx].pin = i; + idx++; + } + + for (idx = 0, i = 0; i < pctl->extints; i++) { + int j = 0, irq = platform_get_irq(pdev, i); + + while (fpint[j].irq != irq) + j++; + + snprintf(pctl->fpint[idx].irqname, 8, "pin-%d", fpint[j].pin); + pctl->fpint[idx].irq = fpint[j].irq; + pctl->fpint[idx].pin = fpint[j].pin; + idx++; + } + + for (i = 0; i < pctl->extints; i++) { + int irq, err = devm_request_irq(&pdev->dev, pctl->fpint[i].irq, + m10v_gpio_irq_handler, IRQF_SHARED, + pctl->fpint[i].irqname, pctl); + if (err) + continue; + + irq = irq_create_mapping(pctl->irqdom, pctl->fpint[i].pin); + irq_set_lockdep_class(irq, &gpio_lock_class, + &gpio_request_class); + irq_set_chip_and_handler(irq, &m10v_gpio_irq_chip, + handle_level_irq); + irq_set_chip_data(irq, pctl); + } + + gc->base = -1; + gc->ngpio = tpins; + gc->label = dev_name(&pdev->dev); + gc->owner = THIS_MODULE; + gc->of_node = np; + gc->direction_input = m10v_gpio_direction_input; + gc->direction_output = m10v_gpio_direction_output; + gc->get = m10v_gpio_get; + gc->set = gpio_set; + gc->to_irq = m10v_gpio_to_irq; + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; + ret = gpiochip_add(gc); + if (ret) { + dev_err(&pdev->dev, "Failed register gpiochip\n"); + return ret; + } + + ret = gpiochip_add_pin_range(gc, dev_name(&pdev->dev), + 0, 0, tpins); + if (ret) { + dev_err(&pdev->dev, "Failed to add pin range\n"); + gpiochip_remove(gc); + return ret; + } + + return 0; +} + +static struct platform_driver m10v_pinctrl_driver = { + .probe = m10v_pinctrl_probe, + .driver = { + .name = "m10v-pinctrl", + .of_match_table = m10v_pmatch, + }, +}; +builtin_platform_driver(m10v_pinctrl_driver); From patchwork Fri Feb 8 12:28:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10803035 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4BD5913BF for ; Fri, 8 Feb 2019 12:43:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 046552DE2D for ; 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Fri, 8 Feb 2019 21:28:00 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id DC9571202F1; Fri, 8 Feb 2019 21:27:59 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 13/15] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board Date: Fri, 8 Feb 2019 21:28:40 +0900 Message-Id: <1549628920-32623-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_122807_963080_9AFCFFF1 X-CRM114-Status: GOOD ( 19.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Shinji Kanematsu , Masami Hiramatsu , Sugaya Taichi , Jassi Brar , Rob Herring , Takao Orito , Kazuhiro Kasai MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add devicetree for Milbeaut M10V SoC and M10V Evaluation board. Signed-off-by: Sugaya Taichi --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/milbeaut-m10v-evb.dts | 32 ++++++++ arch/arm/boot/dts/milbeaut-m10v.dtsi | 131 ++++++++++++++++++++++++++++++++ 3 files changed, 164 insertions(+) create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148..f697d87 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1233,6 +1233,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ mt8127-moose.dtb \ mt8135-evbp1.dtb +dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts b/arch/arm/boot/dts/milbeaut-m10v-evb.dts new file mode 100644 index 0000000..59e8d73 --- /dev/null +++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Socionext Milbeaut M10V Evaluation Board */ +/dts-v1/; +#include "milbeaut-m10v.dtsi" + +/ { + model = "Socionext M10V EVB"; + compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a"; + + aliases { + serial1 = &uart1; + }; + + chosen { + bootargs = "init=/sbin/finit rootwait earlycon"; + stdout-path = "serial1:115200n8"; + }; + + clocks { + uclk40xi: uclk40xi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + +}; diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi new file mode 100644 index 0000000..4fc2f8b --- /dev/null +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include + +/ { + compatible = "socionext,sc2000a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "socionext,milbeaut-m10v-smp"; + cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + }; + cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + }; + cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + }; + cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + }; + }; + + timer { /* The Generic Timer */ + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <40000000>; + always-on; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&gic>; + + gic: interrupt-controller@1d000000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1d001000 0x1000>, + <0x1d002000 0x1000>; /* CPU I/f base and size */ + }; + + clk: m10v-clock-ctrl@1d021000 { + compatible = "socionext,milbeaut-m10v-ccu"; + #clock-cells = <1>; + reg = <0x1d021000 0x1000>; + clocks = <&uclk40xi>; + }; + + timer@1e000050 { /* 32-bit Reload Timers */ + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20>; + interrupts = <0 91 4>; + clocks = <&clk 4>; + }; + + pinctrl: pinctrl@1d022000 { + compatible = "socionext,milbeaut-m10v-pinctrl"; + reg = <0x1d022000 0x1000>, + <0x1c26f000 0x1000>; + reg-names = "pinctrl", "exiu"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk 4>; + interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>, + <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>, + <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>, + <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>; + interrupt-names = "pin-48", "pin-49", "pin-50", + "pin-51", "pin-52", "pin-53", + "pin-54", "pin-55", "pin-56", + "pin-57", "pin-58", "pin-59", + "pin-60", "pin-61", "pin-62", + "pin-63"; + + usio1pins: usio1pins { + pins = "PE4", "PE5", "P87"; + function = "usio1"; + }; + }; + + uart1: serial@1e700010 { /* PE4, PE5 */ + /* Enable this as ttyUSI0 */ + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&clk 2>; + }; + + }; + + sram@0 { + compatible = "mmio-sram"; + reg = <0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x10000>; + smp-sram@f100 { + compatible = "socionext,milbeaut-smp-sram"; + reg = <0xf100 0x20>; + }; + }; +}; From patchwork Fri Feb 8 12:28:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10803037 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 382DE922 for ; Fri, 8 Feb 2019 12:44:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 25B9E20602 for ; Fri, 8 Feb 2019 12:44:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1582327F91; 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Fri, 8 Feb 2019 21:28:12 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id BCE6D1202F1; Fri, 8 Feb 2019 21:28:12 +0900 (JST) From: Sugaya Taichi To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 14/15] ARM: configs: Add Milbeaut M10V defconfig Date: Fri, 8 Feb 2019 21:28:57 +0900 Message-Id: <1549628937-363-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_122814_941312_749787F1 X-CRM114-Status: GOOD ( 20.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shinji Kanematsu , Masami Hiramatsu , Sugaya Taichi , Russell King , Jassi Brar , Takao Orito , Kazuhiro Kasai MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the minimal defconfig for the Milbeaut M10V. Signed-off-by: Sugaya Taichi --- arch/arm/configs/milbeaut_m10v_defconfig | 366 +++++++++++++++++++++++++++++++ 1 file changed, 366 insertions(+) create mode 100644 arch/arm/configs/milbeaut_m10v_defconfig diff --git a/arch/arm/configs/milbeaut_m10v_defconfig b/arch/arm/configs/milbeaut_m10v_defconfig new file mode 100644 index 0000000..c67c87f --- /dev/null +++ b/arch/arm/configs/milbeaut_m10v_defconfig @@ -0,0 +1,366 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEBUG_SEMIHOSTING=y +CONFIG_DEFAULT_HOSTNAME="mlbel" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_FHANDLE=y +CONFIG_NO_HZ_FULL=y +CONFIG_NO_HZ_FULL_ALL=y +CONFIG_NO_HZ_FULL_SYSIDLE=y +CONFIG_NO_HZ_FULL_SYSIDLE_SMALL=4 +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_ARCH_MILBEAUT=y +CONFIG_ARCH_MILBEAUT_M10V=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_775420=y +# CONFIG_PCI is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCIE_SN_DW_PLAT is not set +# CONFIG_PCI_MSI is not set +# CONFIG_PCIEPORTBUS is not set +# CONFIG_PCIEAER is not set +# CONFIG_PCIEASPM is not set +CONFIG_SMP=y +# CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT=y +CONFIG_THUMB2_KERNEL=y +CONFIG_HIGHMEM=y +# CONFIG_COMPACTION is not set +CONFIG_CMA=y +# CONFIG_ATAGS is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_KEXEC=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_PM_RUNTIME=y +CONFIG_PM_DEBUG=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_UDP_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_IP_SCTP=m +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +CONFIG_TIPC=y +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=y +CONFIG_L2TP_ETH=y +CONFIG_IPX=m +CONFIG_NETLINK_MMAP=y +CONFIG_NETLINK_DIAG=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_DEVELOPER_WARNINGS=y +CONFIG_CFG80211_REG_DEBUG=y +CONFIG_CFG80211_INTERNAL_REGDB=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +# CONFIG_MAC80211_RC_MINSTREL is not set +CONFIG_MAC80211_LEDS=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_REGULATOR=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=16 +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_CDN_HPNFC=y +CONFIG_MTD_NAND_CDN_HPNFC_DT=y +CONFIG_MTD_NAND_PLATFORM=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=3 +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=2 +CONFIG_BLK_DEV_RAM=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=y +CONFIG_TUN=y +CONFIG_VETH=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_R8169=y +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_SOCIONEXT_OGMA=y +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_REALTEK_PHY=y +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIO_LIBPS2=y +CONFIG_LEGACY_PTY_COUNT=4 +# CONFIG_DEVKMEM is not set +#CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +#CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DMA is not set +#CONFIG_SERIAL_8250_EXTENDED=y +#CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_MILBEAUT_USIO=y +CONFIG_SERIAL_MILBEAUT_USIO_CONSOLE=y +# CONFIG_HW_RANDOM is not set +# CONFIG_I2C is not set +# CONFIG_I2C_BOARDINFO is not set +# CONFIG_I2C_COMPAT is not set +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_SNI_M10V is not set +CONFIG_SPI=y +# CONFIG_SPI_SN_USIO=y +#CONFIG_SPI_SNI is not set +#CONFIG_SPI_SPIDEV is not set +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DEBUG=y +CONFIG_REGULATOR_S6AP412=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_ADV_DEBUG=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=y +# CONFIG_USB_GSPCA is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SOC_CAMERA=y +CONFIG_SOC_CAMERA_PLATFORM=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIVID_MAX_DEVS=64 +CONFIG_FB=y +# CONFIG_VGA_ARB is not set +# CONFIG_USB is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_OHCI_HCD_PCI is not set +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_SERIAL is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC3_PCI is not set +# CONFIG_USB_DWC3_OTG is not set +# CONFIG_USB_DWC3_SN is not set +# CONFIG_USB_DWC3_OF_SIMPLE is not set +# CONFIG_USB_GADGET_SN_LAP is not set +# CONFIG_USB_CONFIGFS is not set +# CONFIG_USB_CONFIGFS_ACM is not set +# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set +# CONFIG_USB_CONFIGFS_F_MTP is not set +# CONFIG_USB_CONFIGFS_F_UVC is not set +# CONFIG_USB_CONFIGFS_UEVENT is not set +# CONFIG_MMC is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SDHCI_PLTFM is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDHCI_F_EMMC50 is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_HCTOSYS is not set +# CONFIG_RTC_SYSTOHC is not set +CONFIG_RTC_DEBUG=y +CONFIG_RTC_DRV_RX8025=y +CONFIG_DMADEVICES=y +CONFIG_MB86S7X_HDMAC=y +CONFIG_MB8AC0300_XDMAC=y +CONFIG_UIO=y +CONFIG_UIO_SNI=y +# CONFIG_IOMMU_SUPPORT is not set +#CONFIG_PWM=y is not set +# CONFIG_PWM_SYSFS is not set +#CONFIG_PWM_M10V=y is not set +CONFIG_RESET_CONTROLLER=y +CONFIG_EXFAT=y +CONFIG_EXT4_FS=y +# CONFIG_EXT4_USE_FOR_EXT23 is not set +# CONFIG_XFS_FS is not set +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_AUTOFS4_FS=y +# CONFIG_FUSE_FS is not set +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +CONFIG_FSCACHE_HISTOGRAM=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=932 +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BOTH=y +CONFIG_NFS_FS=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +CONFIG_NLS_CODEPAGE_874=y +CONFIG_NLS_ISO8859_8=y +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_3=y +CONFIG_NLS_ISO8859_4=y +CONFIG_NLS_ISO8859_5=y +CONFIG_NLS_ISO8859_6=y +CONFIG_NLS_ISO8859_7=y +CONFIG_NLS_ISO8859_9=y +CONFIG_NLS_ISO8859_13=y +CONFIG_NLS_ISO8859_14=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_KOI8_R=y +CONFIG_NLS_KOI8_U=y +CONFIG_NLS_MAC_ROMAN=y +CONFIG_NLS_MAC_CELTIC=y +CONFIG_NLS_MAC_CENTEURO=y +CONFIG_NLS_MAC_CROATIAN=y +CONFIG_NLS_MAC_CYRILLIC=y +CONFIG_NLS_MAC_GAELIC=y +CONFIG_NLS_MAC_GREEK=y +CONFIG_NLS_MAC_ICELAND=y +CONFIG_NLS_MAC_INUIT=y +CONFIG_NLS_MAC_ROMANIAN=y +CONFIG_NLS_MAC_TURKISH=y +CONFIG_NLS_UTF8=y +CONFIG_IPCU_FS=y +# CONFIG_TEST_IPCU_FS is not set +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +#CONFIG_DEBUG_INFO_REDUCED is not set +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_GIC_BL=y +CONFIG_HEADERS_CHECK=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_RCU_TORTURE_TEST=m +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_KGDB=y +CONFIG_DEBUG_USER=y +#CONFIG_DEBUG_LL=y +#CONFIG_DEBUG_LL_MILBEAUT_UART=y +#CONFIG_EARLY_PRINTK=y +CONFIG_SERIAL_EARLYCON=y +# CONFIG_EARLY_PRINTK_DIRECT is not set +CONFIG_KEYS=y +CONFIG_ENCRYPTED_KEYS=y +CONFIG_SECURITY=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +CONFIG_FONTS=y