From patchwork Wed Aug 9 11:55:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13347861 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18B85EB64DD for ; Wed, 9 Aug 2023 11:55:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pUDOYPQW6SRzqA/e2Yn26nmdSzgt7/behOO871gtMAk=; b=s39iaofRlF//G+ NZ8W8bgrzImhUm8cpSmd93bga594A1zYqHGVg0nvnaK/HZYneoMsa3DnItEkyE3nTY2zJ8m0MUh1W wyMtL3dAoR6L2yYT018DXms9XkePo0JtCd8Dtef6ps4WnL5iFv4MchB2jQHV0AK5Hy9AbTDO2rIGs 30foOAuMhTNPSL6HmKNRZHB+zjIHjVqeRl7FM+RV42foCHMsRi6KjR33jHLc7Hb/mGMkKr3Xloy/I UhTP8P4YyS7wPIvh8Vo6Kaxvwd/8jPBPuPzikg1KzNQ+BXhJNhhK3MEdDty26ur0qUWvpk1RLe63K XU1bPK6ZWe0sqz9n+Jag==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qThmd-004pZg-2p; Wed, 09 Aug 2023 11:55:23 +0000 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qThmb-004pYG-12 for linux-riscv@lists.infradead.org; Wed, 09 Aug 2023 11:55:22 +0000 Received: by mail-ed1-x529.google.com with SMTP id 4fb4d7f45d1cf-5234f2c6c1dso1250831a12.1 for ; Wed, 09 Aug 2023 04:55:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691582119; x=1692186919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MYc3fGGvlRKPoX1LJ72knH8Iv56hmasdsXlRut7wO6Q=; b=LRG57w9Y/MmsS4q7HT160Xlg3Rb8vF2qudRqq5Khw7IaOXghz3BKQrl2wgvM8Aopn8 SkrdPXQqd6cg90lwCv/UNFU27Hw/4nwj8NXMgKmR+bnUR2uZ3B5fEgIGyDxW9Dz693Tb FWvdaqodU91QclSpA5rP8kN3KQtDQTBRMhl8G79D9cypDosT+lcecpfqbXmpPbM71zZ1 Lv0Cc/bNsDTofIjJ1mUE4YSswsrz92PKJlGHZ9wcP05D/daXDeqIn+jUyVr4o030AHHi 0BAjuhI5m+swRoYBTFqiMWQ0wBuRyiI8h5dQyl7feiXJa9qBWH8y+rsdfV2akvY51lqJ 5k5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691582119; x=1692186919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MYc3fGGvlRKPoX1LJ72knH8Iv56hmasdsXlRut7wO6Q=; b=i452VrosL2yRNpqa7cel0GVwuvHYnGw5qbghuDNDrn73H5GL8yIK1JOflWvt8zVZec v+0HXA4DS2MZ5KvuPXC8B+By9fh5fS94kRd9UxPQLS5GywZZpKnIWm+UvK3Zy8rU4hdN hP0OLwVluEVzE+KcTDAowuytKnJj6d7UWcioBu/N0F/6i7cXLbmTPGP2a+fVTmBJCuWI pa36JTe+rXJIZUpw5Q3LIAn0VqcoXXzMHc6o9OK65YHLhoLmq4cTSN6nMlfqMbtyU3nI BKChalqdemYgDeG26ISbTdokSk7g8ilqU4cOe+bc00FPq4EHdicsmwAyQjHJb5t7qXZU BDLQ== X-Gm-Message-State: AOJu0YxdpoWQ8hc0tZvFzJ/Q9VETiLBKViOWRKIQDy7HtJh9qmsuKRwl +Ab/pdeQync8UOsj+757z24rZj236kM2RjxRjg10xy/E X-Google-Smtp-Source: AGHT+IHQHrlm4h7gtPPSuIZoE1yHojByM6yl3SveiLBAGX0dofO0IAR4Q4qyqZxbnHHjLQhOLWqrBw== X-Received: by 2002:a17:907:270c:b0:993:d47f:3c84 with SMTP id w12-20020a170907270c00b00993d47f3c84mr1939338ejk.7.1691582119015; Wed, 09 Aug 2023 04:55:19 -0700 (PDT) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id ka21-20020a170907991500b009882e53a42csm7867181ejc.81.2023.08.09.04.55.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 04:55:18 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, evan@rivosinc.com, conor.dooley@microchip.com, apatel@ventanamicro.com Subject: [PATCH 1/6] RISC-V: Make zicbom/zicboz errors consistent Date: Wed, 9 Aug 2023 13:55:18 +0200 Message-ID: <20230809115516.214537-9-ajones@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115516.214537-8-ajones@ventanamicro.com> References: <20230809115516.214537-8-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230809_045521_374857_2B94576E X-CRM114-Status: GOOD ( 10.62 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org commit c818fea83de4 ("riscv: say disabling zicbom if no or bad riscv,cbom-block-size found") improved the error messages for zicbom but zicboz was missed since its patches were in flight at the same time. Get 'em now. Signed-off-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index a8f66c015229..31843e9cc80c 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -87,10 +87,10 @@ static bool riscv_isa_extension_check(int id) return true; case RISCV_ISA_EXT_ZICBOZ: if (!riscv_cboz_block_size) { - pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n"); + pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n"); return false; } else if (!is_power_of_2(riscv_cboz_block_size)) { - pr_err("cboz-block-size present, but is not a power-of-2\n"); + pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n"); return false; } return true; From patchwork Wed Aug 9 11:55:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13347858 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B2D2C04A94 for ; Wed, 9 Aug 2023 11:55:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fIrD5vy2oZQmHVprP52dh7v3+IvuE3XTHWO65rhhmhY=; b=AMPhDD9/OPL8MG HrxobVE5ozovsiFe8zkXV14IBLgz7UnS8RmCwExuePo41kPTVrOqdKSFujjk/eb0YiqCrV7PqOe0e EhZlIR1YSYhpTT1xWqO2OJ7vK6dKXXezGBjR/ymY37Mib1sO1V0pqiNGgRZZqginiMPLFD7ljzgZG t5eaAX/L7bpRfTw5q6IdZK7AwbM4hu4JqDYlJsZ8o3YLsI9cNlBFTadAdWdlacmPHkga+IHWu1Gjw L/jYfPzY5mvzPZbL1/9Mwfw0Z+/fDsYPLOMXJf1CF2nHwImZe7CLfOQ8hpKhY30mxggM3hzCii2Pf LJY7pD2By6rXr3+wfZtQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qThmh-004pbT-0W; Wed, 09 Aug 2023 11:55:27 +0000 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qThmc-004pYM-1c for linux-riscv@lists.infradead.org; Wed, 09 Aug 2023 11:55:24 +0000 Received: by mail-ed1-x52e.google.com with SMTP id 4fb4d7f45d1cf-522ab557632so8988940a12.0 for ; Wed, 09 Aug 2023 04:55:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691582120; x=1692186920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q86/J9ygU9Mygo4dhyh+BR9pTnBKbpoD6ByYiXk+KKs=; b=bphwVPRdkvuicuO22fjlSimOIYV7U4HOsL0h8ORZG8lvDXeG8OrnsGmSzTq0XEDdEZ eYc63t5fb30OG9wwkw0ZVNxoUE5nRpwRjzzxRIBwfguwkP6YpJHc2YUyBrysbf63hbBf o/oTkb9RP9ghVnau9iNgwQs8Zc0BJTKGCia5gPPHXTyOWo8nLD0h2vEA1o2QOKKgLjMk V+3GPR3fJGu3LyifgA00jZsRZkjcrr3P7JLo+kqNkyhFlEIsyQZz15ZpaDaJC3qH4ETl PIU2PNcXny+CfBP0hTL98V9nQfOk08P4L2oh0d5R3Cj83HmZL0GU+ro8TKZ2FViFi8T3 dXKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691582120; x=1692186920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q86/J9ygU9Mygo4dhyh+BR9pTnBKbpoD6ByYiXk+KKs=; b=R79Xx9Jbm+zEgDRZQlfOfztQ4MjxSaR7cKIiVnuSXOee1lQMJQO279lJM81BPx31O4 L8MZ4Xsf0E0OQlNlhKcGulxd9XFQbD5888BMZRTmP2tXvpIZ1cg1wAmFD5TLWX3B9P2e gxM8ZiSzt9/4zOYgBKM8vkLlvW7EKU7jNYICEgJzFCpVk2lkoBSFhruyW1Got9VxPDSD UTKl1C5tPt1ZkJNEENWuxH0zKCyrrMpK6r7YQmyzYUfNBzg/7EtVkAlOtpvAAnJEBslv KBNaUz5qocQpSUjbYHY9KlA6Rw+zYZk3GhxwTOzgaLQd6qwXkqxt50PHB7963zKVYGkS siOw== X-Gm-Message-State: AOJu0YzAKh0+V6KtLfEIu3bdD7/Mcdby4yEne2nWz44+KQ+U+7N0mSea uncm1p0VfEQj9M70/Znt240lsI4p27KJFrE0mMdTBJ+m X-Google-Smtp-Source: AGHT+IGPv9Uk1ve4XQWkbqHNrBDjjJg2mqO4TpJGIHOeRpY2dTefwbeuhdH6N530N7S20TnERt8uiQ== X-Received: by 2002:a17:906:1c7:b0:997:c377:b41f with SMTP id 7-20020a17090601c700b00997c377b41fmr2149403ejj.64.1691582120259; Wed, 09 Aug 2023 04:55:20 -0700 (PDT) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id z5-20020a170906434500b00977cad140a8sm7886248ejm.218.2023.08.09.04.55.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 04:55:19 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, evan@rivosinc.com, conor.dooley@microchip.com, apatel@ventanamicro.com Subject: [PATCH 2/6] RISC-V: Enable cbo.zero in usermode Date: Wed, 9 Aug 2023 13:55:19 +0200 Message-ID: <20230809115516.214537-10-ajones@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115516.214537-8-ajones@ventanamicro.com> References: <20230809115516.214537-8-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230809_045522_542395_6195E9DD X-CRM114-Status: GOOD ( 12.61 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When Zicboz is present, enable its instruction (cbo.zero) in usermode by setting its respective senvcfg bit. We don't bother trying to set this bit per-task, which would also require an interface for tasks to request enabling and/or disabling. Instead, permanently set the bit for each hart which has the extension when bringing it online. Signed-off-by: Andrew Jones --- arch/riscv/include/asm/cpufeature.h | 2 ++ arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/hwcap.h | 16 ++++++++++++++++ arch/riscv/kernel/cpufeature.c | 6 ++++++ arch/riscv/kernel/setup.c | 4 ++++ arch/riscv/kernel/smpboot.c | 4 ++++ 6 files changed, 33 insertions(+) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 23fed53b8815..788fd575c21a 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -30,4 +30,6 @@ DECLARE_PER_CPU(long, misaligned_access_speed); /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; +void riscv_user_isa_enable(void); + #endif diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 7bac43a3176e..e187e76e3df4 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -273,6 +273,7 @@ #define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 +#define CSR_SENVCFG 0x10a #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index f041bfa7f6a0..4929faecb75f 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -66,6 +66,7 @@ #ifndef __ASSEMBLY__ #include +#include unsigned long riscv_get_elf_hwcap(void); @@ -130,6 +131,21 @@ riscv_has_extension_unlikely(const unsigned long ext) return true; } +static __always_inline bool riscv_this_cpu_has_extension_likely(const unsigned long ext) +{ + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext)) + return true; + + return __riscv_isa_extension_available(hart_isa[smp_processor_id()].isa, ext); +} + +static __always_inline bool riscv_this_cpu_has_extension_unlikely(const unsigned long ext) +{ + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext)) + return true; + + return __riscv_isa_extension_available(hart_isa[smp_processor_id()].isa, ext); +} #endif #endif /* _ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 31843e9cc80c..fc0bf300acc7 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -391,6 +391,12 @@ unsigned long riscv_get_elf_hwcap(void) return hwcap; } +void riscv_user_isa_enable(void) +{ + if (riscv_this_cpu_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ)) + csr_set(CSR_SENVCFG, ENVCFG_CBZE); +} + #ifdef CONFIG_RISCV_ALTERNATIVE /* * Alternative patch sites consider 48 bits when determining when to patch diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 971fe776e2f8..2f053f0763a1 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -308,9 +309,12 @@ void __init setup_arch(char **cmdline_p) riscv_fill_hwcap(); init_rt_signal_env(); apply_boot_alternatives(); + if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) && riscv_isa_extension_available(NULL, ZICBOM)) riscv_noncoherent_supported(); + + riscv_user_isa_enable(); } static int __init topology_init(void) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index f4d6acb38dd0..502b04abda0b 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -25,6 +25,8 @@ #include #include #include + +#include #include #include #include @@ -252,6 +254,8 @@ asmlinkage __visible void smp_callin(void) elf_hwcap &= ~COMPAT_HWCAP_ISA_V; } + riscv_user_isa_enable(); + /* * Remote TLB flushes are ignored while the CPU is offline, so emit * a local TLB flush right now just in case. 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id a22-20020aa7d756000000b005232cf13b02sm5613604eds.37.2023.08.09.04.55.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 04:55:21 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, evan@rivosinc.com, conor.dooley@microchip.com, apatel@ventanamicro.com Subject: [PATCH 3/6] RISC-V: hwprobe: Expose Zicboz extension and its block size Date: Wed, 9 Aug 2023 13:55:20 +0200 Message-ID: <20230809115516.214537-11-ajones@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115516.214537-8-ajones@ventanamicro.com> References: <20230809115516.214537-8-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230809_045523_891961_B1169C42 X-CRM114-Status: GOOD ( 16.80 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Expose Zicboz through hwprobe and also provide a key to extract its respective block size. Opportunistically add a macro and apply it to current extensions in order to avoid duplicating code. Signed-off-by: Andrew Jones Reviewed-by: Evan Green --- Documentation/riscv/hwprobe.rst | 6 ++++ arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_riscv.c | 41 ++++++++++++++++++--------- 4 files changed, 36 insertions(+), 15 deletions(-) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index 933c715065d6..6a17c2872660 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -77,6 +77,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. @@ -97,3 +100,6 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are not supported at all and will generate a misaligned address fault. + +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which + represents the size of the Zicboz block in bytes. diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h index 78936f4ff513..39df8604fea1 100644 --- a/arch/riscv/include/asm/hwprobe.h +++ b/arch/riscv/include/asm/hwprobe.h @@ -8,6 +8,6 @@ #include -#define RISCV_HWPROBE_MAX_KEY 5 +#define RISCV_HWPROBE_MAX_KEY 6 #endif diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 006bfb48343d..86d08a0e617b 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -29,6 +29,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZBA (1 << 3) #define RISCV_HWPROBE_EXT_ZBB (1 << 4) #define RISCV_HWPROBE_EXT_ZBS (1 << 5) +#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) @@ -36,6 +37,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) +#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */ #endif diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 26ef5526bfb4..7d970358597b 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -145,26 +145,33 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, for_each_cpu(cpu, cpus) { struct riscv_isainfo *isainfo = &hart_isa[cpu]; - if (riscv_isa_extension_available(isainfo->isa, ZBA)) - pair->value |= RISCV_HWPROBE_EXT_ZBA; - else - missing |= RISCV_HWPROBE_EXT_ZBA; - - if (riscv_isa_extension_available(isainfo->isa, ZBB)) - pair->value |= RISCV_HWPROBE_EXT_ZBB; - else - missing |= RISCV_HWPROBE_EXT_ZBB; - - if (riscv_isa_extension_available(isainfo->isa, ZBS)) - pair->value |= RISCV_HWPROBE_EXT_ZBS; - else - missing |= RISCV_HWPROBE_EXT_ZBS; +#define EXT_KEY(ext) \ + do { \ + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_EXT_##ext)) \ + pair->value |= RISCV_HWPROBE_EXT_##ext; \ + else \ + missing |= RISCV_HWPROBE_EXT_##ext; \ + } while (false) + + EXT_KEY(ZBA); + EXT_KEY(ZBB); + EXT_KEY(ZBS); + EXT_KEY(ZICBOZ); +#undef EXT_KEY } /* Now turn off reporting features if any CPU is missing it. */ pair->value &= ~missing; } +static bool hwprobe_ext0_has(const struct cpumask *cpus, unsigned long ext) +{ + struct riscv_hwprobe pair; + + hwprobe_isa_ext0(&pair, cpus); + return (pair.value & ext); +} + static u64 hwprobe_misaligned(const struct cpumask *cpus) { int cpu; @@ -215,6 +222,12 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair, pair->value = hwprobe_misaligned(cpus); break; + case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE: + pair->value = 0; + if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ)) + pair->value = riscv_cboz_block_size; + break; + /* * For forward compatibility, unknown keys don't fail the whole * call, but get their element key set to -1 and value set to 0 From patchwork Wed Aug 9 11:55:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13347855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5E5B5EB64DD for ; Wed, 9 Aug 2023 11:55:31 +0000 (UTC) DKIM-Signature: v=1; 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id j6-20020a1709066dc600b0099d45ed589csm413519ejt.125.2023.08.09.04.55.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 04:55:22 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, evan@rivosinc.com, conor.dooley@microchip.com, apatel@ventanamicro.com Subject: [PATCH 4/6] RISC-V: selftests: Statically link hwprobe test Date: Wed, 9 Aug 2023 13:55:21 +0200 Message-ID: <20230809115516.214537-12-ajones@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115516.214537-8-ajones@ventanamicro.com> References: <20230809115516.214537-8-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230809_045524_534747_EA12C6F2 X-CRM114-Status: UNSURE ( 8.62 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Statically linking makes it more convenient to copy the test to a minimal busybox environment. Signed-off-by: Andrew Jones Reviewed-by: Conor Dooley --- tools/testing/selftests/riscv/hwprobe/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/riscv/hwprobe/Makefile b/tools/testing/selftests/riscv/hwprobe/Makefile index ebdbb3c22e54..5f614c3ba598 100644 --- a/tools/testing/selftests/riscv/hwprobe/Makefile +++ b/tools/testing/selftests/riscv/hwprobe/Makefile @@ -7,4 +7,4 @@ TEST_GEN_PROGS := hwprobe include ../../lib.mk $(OUTPUT)/hwprobe: hwprobe.c sys_hwprobe.S - $(CC) -o$@ $(CFLAGS) $(LDFLAGS) $^ + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ From patchwork Wed Aug 9 11:55:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13347859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67AF5EB64DD for ; Wed, 9 Aug 2023 11:55:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=d1VHy/YDV1mvD8a931oEOqXD5PBWt6ybwjhyng7AAxw=; b=0R1JG3amNJmVaT 6VGwPSyP+UGO3dmweOyHjsQwm957WtIEehDqt2Ap+KX2yGqmOd1p6gtR8FSY5uLhYzwLwN6ouyUSP aIFl0axosm0SEx7Q1iNWdmFpo5bByKzY3IOl0c1I1cA9xgWW9BXrNxYDmPCgc2zpDLGjpFg0F6Vad 6N7samwM1tlNj+NKD5/VdI+o9FKyRhYEjtcYBf4lAWbTjFR8Xlr3HLmDQoFA6TB/XN41hOqfnVRTz ClbZI+3s1qen3UadWQnYqeJwuYHrsLEO76AM3e/FxZG/OPAYhlQRmg5fiHNTRXwSpVTuL7GFrOUc2 g7VqF3tGpRlctw3W2Rfg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qThml-004pdN-05; Wed, 09 Aug 2023 11:55:31 +0000 Received: from mail-lf1-x133.google.com ([2a00:1450:4864:20::133]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qThmg-004paT-1e for linux-riscv@lists.infradead.org; Wed, 09 Aug 2023 11:55:27 +0000 Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4fe61ae020bso6723488e87.2 for ; Wed, 09 Aug 2023 04:55:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1691582124; x=1692186924; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GCGTSuqvvD5txfHJJaQYik4t5PK/mtwBdizG3ZZUj7w=; b=k7vOwfh8pO7D9mmiQHTm4vJqXRtCZ4BwLsFaIUts49fDEzzhZq6aDnBdoaXcagLmZC ItuoE8KFrpI08ZUh6can+MkLKQMcgIjo6DzRuD55Fl11oJKpcHUEajqQV4sq9ycrreAg 2rIhmJ+KP6qmMhGMPXK5NSqZaW5syiBi+7kbYEzf00jcJwxAozApcwNyxFSK5Jg5QR/E SdZ9GgsPh1dUvAW5WKdYb5Enx78FfpVU/zd+LYyWP0U4GkeJJ6KqkT97mdWTsc3YI/fR Yo5s5QPThY5+SaAffOQfHDejWuYuWZs+9S9QTYmOrj7QnsZKnh5KJQsvYsdtW4gxMzdJ 7CDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691582124; x=1692186924; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GCGTSuqvvD5txfHJJaQYik4t5PK/mtwBdizG3ZZUj7w=; b=RXNDDpSTjcxrOMgHNivYj1+6t6TI+bu/4w3Podl7QDDhh08LyGbrGXaU1PmOFmQcqe j0Skln4VEPVkXfvrdmFPiWjH6uhWea0GxIOgprwFbR7DO8EjGPeY37d7Iuqb+R6V4NuR uckX4LnKMXbO4YYdK9zxpVJqfWFGHIN2irH0hojMSmmp/EFxUsCV/RFf20XEvXvXjXOE tLJ+OnzvhtCsAEiKfV7kA7ZhCn2mryd8TceY0A96Uv1ehdSamzfAHaENMfIfYC7PHwX1 vbeDpsULjnqQLDuYtpA4Sk/FV7SVE6DgCgnCtcMzaYXuloCXOaRQ4b5iQX/hRxC2i7GK FKqg== X-Gm-Message-State: AOJu0YxwGBJtPJFY9nAhcTQ5HrztmtR0PLsSvs0dOTcOPlgMQrYtqmFC 6U21x1lI1vjEpn+Fql9AgDGoIN4M0kU9fKCncDBLBAin X-Google-Smtp-Source: AGHT+IHD+CjBY8mgfl0MKPyYRq+KY4iLGGOTkr8Xmh1dHX9dpFWHsduFrzHWcUZPrNCxCrNgwReB5A== X-Received: by 2002:ac2:48a2:0:b0:4fd:e113:f5fa with SMTP id u2-20020ac248a2000000b004fde113f5famr1593160lfg.7.1691582123715; Wed, 09 Aug 2023 04:55:23 -0700 (PDT) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id h4-20020aa7c944000000b0052369aa9956sm567617edt.26.2023.08.09.04.55.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 04:55:23 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, evan@rivosinc.com, conor.dooley@microchip.com, apatel@ventanamicro.com Subject: [PATCH 5/6] RISC-V: selftests: Convert hwprobe test to kselftest API Date: Wed, 9 Aug 2023 13:55:22 +0200 Message-ID: <20230809115516.214537-13-ajones@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115516.214537-8-ajones@ventanamicro.com> References: <20230809115516.214537-8-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230809_045526_547719_D35C9688 X-CRM114-Status: GOOD ( 17.77 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Returning (exiting with) negative exit codes isn't user friendly, because the user must output the exit code with the shell, convert it from its unsigned 8-bit value back to the negative value, and then look up where that comes from in the code (which may be multiple places). Use the kselftests TAP interface, instead. Signed-off-by: Andrew Jones --- .../testing/selftests/riscv/hwprobe/hwprobe.c | 54 +++++++------------ 1 file changed, 20 insertions(+), 34 deletions(-) diff --git a/tools/testing/selftests/riscv/hwprobe/hwprobe.c b/tools/testing/selftests/riscv/hwprobe/hwprobe.c index 09f290a67420..4f15f1f3b4c3 100644 --- a/tools/testing/selftests/riscv/hwprobe/hwprobe.c +++ b/tools/testing/selftests/riscv/hwprobe/hwprobe.c @@ -2,6 +2,8 @@ #include #include +#include "../../kselftest.h" + /* * Rather than relying on having a new enough libc to define this, just do it * ourselves. This way we don't need to be coupled to a new-enough libc to @@ -16,6 +18,9 @@ int main(int argc, char **argv) unsigned long cpus; long out; + ksft_print_header(); + ksft_set_plan(5); + /* Fake the CPU_SET ops. */ cpus = -1; @@ -25,13 +30,16 @@ int main(int argc, char **argv) */ for (long i = 0; i < 8; i++) pairs[i].key = i; + out = riscv_hwprobe(pairs, 8, 1, &cpus, 0); if (out != 0) - return -1; + ksft_exit_fail_msg("hwprobe() failed with %ld\n", out); + for (long i = 0; i < 4; ++i) { /* Fail if the kernel claims not to recognize a base key. */ if ((i < 4) && (pairs[i].key != i)) - return -2; + ksft_exit_fail_msg("Failed to recognize base key: key != i, " + "key=%ld, i=%ld\n", pairs[i].key, i); if (pairs[i].key != RISCV_HWPROBE_KEY_BASE_BEHAVIOR) continue; @@ -39,52 +47,30 @@ int main(int argc, char **argv) if (pairs[i].value & RISCV_HWPROBE_BASE_BEHAVIOR_IMA) continue; - return -3; + ksft_exit_fail_msg("Unexpected pair: (%ld, %ld)\n", pairs[i].key, pairs[i].value); } - /* - * This should also work with a NULL CPU set, but should not work - * with an improperly supplied CPU set. - */ out = riscv_hwprobe(pairs, 8, 0, 0, 0); - if (out != 0) - return -4; + ksft_test_result(out == 0, "NULL CPU set\n"); out = riscv_hwprobe(pairs, 8, 0, &cpus, 0); - if (out == 0) - return -5; + ksft_test_result(out != 0, "Bad CPU set\n"); out = riscv_hwprobe(pairs, 8, 1, 0, 0); - if (out == 0) - return -6; + ksft_test_result(out != 0, "NULL CPU set with non-zero count\n"); - /* - * Check that keys work by providing one that we know exists, and - * checking to make sure the resultig pair is what we asked for. - */ pairs[0].key = RISCV_HWPROBE_KEY_BASE_BEHAVIOR; out = riscv_hwprobe(pairs, 1, 1, &cpus, 0); - if (out != 0) - return -7; - if (pairs[0].key != RISCV_HWPROBE_KEY_BASE_BEHAVIOR) - return -8; + ksft_test_result(out == 0 && pairs[0].key == RISCV_HWPROBE_KEY_BASE_BEHAVIOR, + "Existing key is maintained\n"); - /* - * Check that an unknown key gets overwritten with -1, - * but doesn't block elements after it. - */ pairs[0].key = 0x5555; pairs[1].key = 1; pairs[1].value = 0xAAAA; out = riscv_hwprobe(pairs, 2, 0, 0, 0); - if (out != 0) - return -9; - - if (pairs[0].key != -1) - return -10; - - if ((pairs[1].key != 1) || (pairs[1].value == 0xAAAA)) - return -11; + ksft_test_result(out == 0 && pairs[0].key == -1 && + pairs[1].key == 1 && pairs[1].value != 0xAAAA, + "Unknown key overwritten with -1 and doesn't block other elements\n"); - return 0; + ksft_finished(); } From patchwork Wed Aug 9 11:55:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13347860 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7E6DC04E69 for ; Wed, 9 Aug 2023 11:55:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id lr4-20020a170906fb8400b0098748422178sm7840535ejb.56.2023.08.09.04.55.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 04:55:24 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, evan@rivosinc.com, conor.dooley@microchip.com, apatel@ventanamicro.com Subject: [PATCH 6/6] RISC-V: selftests: Add CBO tests Date: Wed, 9 Aug 2023 13:55:23 +0200 Message-ID: <20230809115516.214537-14-ajones@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230809115516.214537-8-ajones@ventanamicro.com> References: <20230809115516.214537-8-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230809_045526_424739_DF387063 X-CRM114-Status: GOOD ( 24.01 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add hwprobe test for Zicboz and its block size. Also, when Zicboz is present, test that cbo.zero may be issued and works. Additionally test that the Zicbom instructions cause SIGILL and also that cbo.zero causes SIGILL when Zicboz is not present. Pinning the test to a subset of cpus with taskset will also restrict the hwprobe calls to that set. Signed-off-by: Andrew Jones --- tools/testing/selftests/riscv/Makefile | 2 +- .../testing/selftests/riscv/hwprobe/Makefile | 5 +- tools/testing/selftests/riscv/hwprobe/cbo.c | 160 ++++++++++++++++++ .../testing/selftests/riscv/hwprobe/hwprobe.c | 12 +- .../testing/selftests/riscv/hwprobe/hwprobe.h | 15 ++ 5 files changed, 181 insertions(+), 13 deletions(-) create mode 100644 tools/testing/selftests/riscv/hwprobe/cbo.c create mode 100644 tools/testing/selftests/riscv/hwprobe/hwprobe.h diff --git a/tools/testing/selftests/riscv/Makefile b/tools/testing/selftests/riscv/Makefile index f4b3d5c9af5b..7bbeec48292d 100644 --- a/tools/testing/selftests/riscv/Makefile +++ b/tools/testing/selftests/riscv/Makefile @@ -16,7 +16,7 @@ CFLAGS := -Wall -O2 -g top_srcdir = $(realpath ../../../../) # Additional include paths needed by kselftest.h and local headers -CFLAGS += -I$(top_srcdir)/tools/testing/selftests/ +CFLAGS += -I$(top_srcdir)/tools/testing/selftests/ -I$(top_srcdir)/tools/include CFLAGS += $(KHDR_INCLUDES) diff --git a/tools/testing/selftests/riscv/hwprobe/Makefile b/tools/testing/selftests/riscv/hwprobe/Makefile index 5f614c3ba598..56e54d66df7e 100644 --- a/tools/testing/selftests/riscv/hwprobe/Makefile +++ b/tools/testing/selftests/riscv/hwprobe/Makefile @@ -2,9 +2,12 @@ # Copyright (C) 2021 ARM Limited # Originally tools/testing/arm64/abi/Makefile -TEST_GEN_PROGS := hwprobe +TEST_GEN_PROGS := hwprobe cbo include ../../lib.mk $(OUTPUT)/hwprobe: hwprobe.c sys_hwprobe.S $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ + +$(OUTPUT)/cbo: cbo.c sys_hwprobe.S + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ diff --git a/tools/testing/selftests/riscv/hwprobe/cbo.c b/tools/testing/selftests/riscv/hwprobe/cbo.c new file mode 100644 index 000000000000..6fa01e4cec99 --- /dev/null +++ b/tools/testing/selftests/riscv/hwprobe/cbo.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Run with 'taskset -c cbo' to only execute hwprobe on a + * subset of cpus, as well as only executing the tests on those cpus. + */ +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include + +#include "hwprobe.h" +#include "../../kselftest.h" + +static char mem[4096] __aligned(4096) = { [0 ... 4095] = 0xa5 }; + +static bool illegal_insn; + +static void sigill_handler(int sig, siginfo_t *info, void *context) +{ + unsigned long *regs = (unsigned long *)&((ucontext_t *)context)->uc_mcontext; + uint32_t insn = *(uint32_t *)regs[0]; + + assert(insn >> 20 == regs[11] && + (insn & ((1 << 20) - 1)) == (10 << 15 | 2 << 12 | 0 << 7 | 15)); + + illegal_insn = true; + regs[0] += 4; +} + +static void cbo_insn(int fn, char *base) +{ + asm volatile( + "mv a0, %0\n" + "li a1, %1\n" + ".4byte %1 << 20 | 10 << 15 | 2 << 12 | 0 << 7 | 15\n" + : : "r" (base), "i" (fn) : "a0", "a1", "memory"); +} + +static void cbo_inval(char *base) { cbo_insn(0, base); } +static void cbo_clean(char *base) { cbo_insn(1, base); } +static void cbo_flush(char *base) { cbo_insn(2, base); } +static void cbo_zero(char *base) { cbo_insn(4, base); } + +static void test_no_zicbom(void) +{ + illegal_insn = false; + cbo_clean(&mem[0]); + ksft_test_result(illegal_insn, "No cbo.clean\n"); + + illegal_insn = false; + cbo_flush(&mem[0]); + ksft_test_result(illegal_insn, "No cbo.flush\n"); + + illegal_insn = false; + cbo_inval(&mem[0]); + ksft_test_result(illegal_insn, "No cbo.inval\n"); +} + +static void test_no_zicboz(void) +{ + illegal_insn = false; + cbo_clean(&mem[0]); + ksft_test_result(illegal_insn, "No cbo.zero\n"); +} + +static bool is_power_of_2(__u64 n) +{ + return n != 0 && (n & (n - 1)) == 0; +} + +static void test_zicboz(__u64 block_size) +{ + int i, j; + + illegal_insn = false; + cbo_zero(&mem[block_size]); + ksft_test_result(!illegal_insn, "cbo.zero\n"); + + if (!is_power_of_2(block_size)) { + ksft_test_result_skip("cbo.zero check\n"); + return; + } + + assert(block_size <= 1024); + + for (i = 0; i < 4096 / block_size; ++i) { + if (i % 2) + cbo_zero(&mem[i * block_size]); + } + + for (i = 0; i < 4096 / block_size; ++i) { + char expected = i % 2 ? 0x0 : 0xa5; + + for (j = 0; j < block_size; ++j) { + if (mem[i * block_size + j] != expected) { + ksft_test_result_fail("cbo.zero check\n"); + ksft_print_msg("cbo.zero check: mem[%d] != 0x%x\n", + i * block_size + j, expected); + return; + } + } + } + + ksft_test_result_pass("cbo.zero check\n"); +} + +int main(int argc, char **argv) +{ + struct sigaction act = { + .sa_sigaction = &sigill_handler, + .sa_flags = SA_SIGINFO, + }; + bool has_zicboz = false; + struct riscv_hwprobe pair; + cpu_set_t cpus; + size_t nr_cpus; + long rc; + + rc = sigaction(SIGILL, &act, NULL); + assert(rc == 0); + + rc = sched_getaffinity(0, sizeof(cpu_set_t), &cpus); + assert(rc == 0); + nr_cpus = CPU_COUNT(&cpus); + + ksft_print_header(); + + pair.key = RISCV_HWPROBE_KEY_IMA_EXT_0; + rc = riscv_hwprobe(&pair, 1, nr_cpus, (unsigned long *)&cpus, 0); + if (rc < 0) + ksft_exit_fail_msg("hwprobe() failed with %d\n", rc); + + if (pair.key != -1 && (pair.value & RISCV_HWPROBE_EXT_ZICBOZ)) { + has_zicboz = true; + ksft_set_plan(6); + } else { + ksft_print_msg("No Zicboz, testing cbo.zero remains privileged\n"); + ksft_set_plan(4); + } + + /* Ensure zicbom instructions remain privileged */ + test_no_zicbom(); + + if (has_zicboz) { + pair.key = RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE; + rc = riscv_hwprobe(&pair, 1, nr_cpus, (unsigned long *)&cpus, 0); + ksft_test_result(rc == 0 && pair.key == RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE && + is_power_of_2(pair.value), "Zicboz block size\n"); + ksft_print_msg("Zicboz block size: %ld\n", pair.value); + test_zicboz(pair.value); + } else { + test_no_zicboz(); + } + + ksft_finished(); +} diff --git a/tools/testing/selftests/riscv/hwprobe/hwprobe.c b/tools/testing/selftests/riscv/hwprobe/hwprobe.c index 4f15f1f3b4c3..c474891df307 100644 --- a/tools/testing/selftests/riscv/hwprobe/hwprobe.c +++ b/tools/testing/selftests/riscv/hwprobe/hwprobe.c @@ -1,17 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only -#include -#include - +#include "hwprobe.h" #include "../../kselftest.h" -/* - * Rather than relying on having a new enough libc to define this, just do it - * ourselves. This way we don't need to be coupled to a new-enough libc to - * contain the call. - */ -long riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count, - size_t cpu_count, unsigned long *cpus, unsigned int flags); - int main(int argc, char **argv) { struct riscv_hwprobe pairs[8]; diff --git a/tools/testing/selftests/riscv/hwprobe/hwprobe.h b/tools/testing/selftests/riscv/hwprobe/hwprobe.h new file mode 100644 index 000000000000..721b0ce73a56 --- /dev/null +++ b/tools/testing/selftests/riscv/hwprobe/hwprobe.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef SELFTEST_RISCV_HWPROBE_H +#define SELFTEST_RISCV_HWPROBE_H +#include +#include + +/* + * Rather than relying on having a new enough libc to define this, just do it + * ourselves. This way we don't need to be coupled to a new-enough libc to + * contain the call. + */ +long riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count, + size_t cpu_count, unsigned long *cpus, unsigned int flags); + +#endif