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Thu, 10 Aug 2023 07:20:13 -0500 From: Thippeswamy Havalige To: , , , , , , CC: , , , , "Thippeswamy Havalige" Subject: [PATCH v3 1/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example Date: Thu, 10 Aug 2023 17:50:01 +0530 Message-ID: <20230810122002.133531-3-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810122002.133531-1-thippeswamy.havalige@amd.com> References: <20230810122002.133531-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529F:EE_|DM6PR12MB4138:EE_ X-MS-Office365-Filtering-Correlation-Id: f4034ef2-16b2-475d-bfc0-08db999c2ae1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /tu544tuxbWxS8Zb4UypyP17HHwBS/3NT/whngthhwvqskIs6I78UG1FMx6hLJVr6cwKyShKDLD+WFcmf1Yn8+bcxfNipo73jNjwpxRO0g24NAHNM7u+jKKcFdRfjChNX5yM3nLMiOrszZG7dVwgVoU16FZdJ8bY5wG0PL0qU6HDjk+TuT+DWLcm+svN4R2rgSTFDdh3bEndlwvSsOL8UaOLR9ih4ILwH3HCOTdV44DUt+K74JvvnM/mwc5vXNY8GRYJUN9amYed/ghh61ns63FIykxwDPh0VskmEhu/YfZ8Q2KGytH/tiHm5klWB6onDkeXcBkP6LrS7MKs+BykROjfTKWh8nSvww9q5bvqnn3uurn8es4EmQPl2EHe9Z297kcUJ8KChUdeX+gMgrF1ksb8JJJRw4NV7+osLJQv3GI4vRhyrzfAsyxQ/KRkfU5DIP1H2llRgY7+ZIHygP4CE27YjZKZmYNcBz2qxUX3wDILG/QsWaMPNtrEi+GqhCiZPFDmD6wYy0ojiP5Jn74bfMpU+xp55itgttQzouxmfxGBGEzsbuvaAljX45URzLyYRCXd1NrqeoAqE+tR4btbb9eH5XAIyu/aXGAucIis1vykupRtDa4wt/7+T9VjMg+aCR6oDUuyPzoQE9UDIZb1GZ6yHh8l38Z0T9uxRnu5VoZCMBsOh2CWr4SPgpRDXoXWqVCRrF3cQZp3MfEGZOhAcmgLneRNWrijUb5EUHjH8pchgmeZ9Gq+qjN0+6+VRD2xuCtiBzuxYx8o8s8LB399VQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(346002)(39860400002)(136003)(396003)(186006)(82310400008)(1800799006)(451199021)(46966006)(40470700004)(36840700001)(54906003)(26005)(1076003)(110136005)(81166007)(8676002)(8936002)(2616005)(426003)(356005)(36860700001)(336012)(478600001)(86362001)(4326008)(70586007)(70206006)(47076005)(41300700001)(40460700003)(316002)(82740400003)(2906002)(36756003)(83380400001)(40480700001)(5660300002)(44832011)(6666004)(36900700001);DIR:OUT;SFP:1101; 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Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada Acked-by: Rob Herring --- changes in v2: None. changes in v1: None. --- Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml index 897602559b37..426f90a47f35 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml @@ -118,7 +118,7 @@ examples: compatible = "xlnx,nwl-pcie-2.11"; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>; From patchwork Thu Aug 10 12:20:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 13349359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82377C001E0 for ; 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Thu, 10 Aug 2023 07:20:20 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 10 Aug 2023 07:20:19 -0500 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Thu, 10 Aug 2023 07:20:16 -0500 From: Thippeswamy Havalige To: , , , , , , CC: , , , , "Thippeswamy Havalige" Subject: [PATCH v3 2/2] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Date: Thu, 10 Aug 2023 17:50:02 +0530 Message-ID: <20230810122002.133531-4-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230810122002.133531-1-thippeswamy.havalige@amd.com> References: <20230810122002.133531-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT103:EE_|SN7PR12MB7369:EE_ X-MS-Office365-Filtering-Correlation-Id: 24a4a6bb-4661-4109-bf4f-08db999c2fe5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Aug 2023 12:20:30.0278 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 24a4a6bb-4661-4109-bf4f-08db999c2fe5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT103.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7369 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230810_052036_371606_E19ABAAE X-CRM114-Status: GOOD ( 12.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- changes in v3: - Remove unnecessary period at end of subject line. changes in v2: - Update this changes in a seperate patch. --- drivers/pci/controller/pcie-xilinx-nwl.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index d8a3a08be1d5..b51501921d3b 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_VALUE_DEFAULT 12 +#define NWL_ECAM_VALUE_DEFAULT 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0) @@ -165,7 +165,6 @@ struct nwl_pcie { u32 ecam_size; int irq_intx; int irq_misc; - u32 ecam_value; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -674,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) E_ECAM_CR_ENABLE, E_ECAM_CONTROL); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | - (pcie->ecam_value << E_ECAM_SIZE_SHIFT), + (NWL_ECAM_VALUE_DEFAULT << E_ECAM_SIZE_SHIFT), E_ECAM_CONTROL); nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), @@ -782,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; - pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; err = nwl_pcie_parse_dt(pcie, pdev); if (err) {