From patchwork Fri Aug 11 04:43:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13350068 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC8BEEB64DD for ; Fri, 11 Aug 2023 04:43:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3D20D10E640; Fri, 11 Aug 2023 04:43:14 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9CE6C10E640; Fri, 11 Aug 2023 04:43:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691728992; x=1723264992; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ReswyNDgQzA3g8so7QVV8af56vcYeIhA2sXH7Xg/Knw=; b=Ra0Zt9erT53rGB0si3hiz4YES3iD4WmtF7ysXJ4ioBxgDilhgYIjii1X ssKtzTkyUGyNx8t3J32OUIzeRZlfjbloGalMGZYaTB2uKHfro3ZXteA+w MpxnnxIXJG2KNLKf1+jxfQ81H3iHGB4IMB/5jIyMdnYRp1Ket0dGABANx zbFuq7XLhX16PriT7DDH/o7qOu5xzj0qoAYhWgS3dpVd1TbxfEP7Go2eT /EgLw8iqonAFhzOap0diT8uHdfWzpFQsdoh7b4SU6BkJzGquErY+XnTpr Uags+jKZPotEqQN8DincJSCFBYY8vzlcOMBa50Hzn5MxDv1zRX+Qrk2zP g==; X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="351197196" X-IronPort-AV: E=Sophos;i="6.01,164,1684825200"; d="scan'208";a="351197196" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2023 21:43:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="802533471" X-IronPort-AV: E=Sophos;i="6.01,164,1684825200"; d="scan'208";a="802533471" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga004.fm.intel.com with ESMTP; 10 Aug 2023 21:43:11 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 1/3] drm/i915/pxp/mtl: Update pxp-firmware response timeout Date: Thu, 10 Aug 2023 21:43:08 -0700 Message-Id: <20230811044310.944883-2-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230811044310.944883-1-alan.previn.teres.alexis@intel.com> References: <20230811044310.944883-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Update the max GSC-fw response time to match updated internal fw specs. Because this response time is an SLA on the firmware, not inclusive of i915->GuC->HW handoff latency, when submitting requests to the GSC fw via intel_gsc_uc_heci_cmd_submit_nonpriv, start the count after the request hits the GSC command streamer. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c | 3 +++ drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c index 89ed5ee9cded..ae45855594ac 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.c @@ -186,6 +186,9 @@ intel_gsc_uc_heci_cmd_submit_nonpriv(struct intel_gsc_uc *gsc, i915_request_add(rq); if (!err) { + if (wait_for(i915_request_started(rq), 200)) + drm_dbg(&gsc_uc_to_gt(gsc)->i915->drm, + "Delay in gsc-heci-non-priv submission to gsccs-hw"); if (i915_request_wait(rq, I915_WAIT_INTERRUPTIBLE, msecs_to_jiffies(timeout_ms)) < 0) err = -ETIME; diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h index 298ad38e6c7d..4368f010bbd3 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h @@ -10,10 +10,10 @@ struct intel_pxp; -#define GSC_REPLY_LATENCY_MS 210 +#define GSC_REPLY_LATENCY_MS 350 /* - * Max FW response time is 200ms, to which we add 10ms to account for overhead - * such as request preparation, GuC submission to hw and pipeline completion times. + * Max FW response time is 350ms, but this should be counted from the time the + * command has hit the GSC-CS hardware, not the preceding handoff to GuC CTB. */ #define GSC_PENDING_RETRY_MAXCOUNT 40 #define GSC_PENDING_RETRY_PAUSE_MS 50 From patchwork Fri Aug 11 04:43:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13350070 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0BA3FC001DE for ; Fri, 11 Aug 2023 04:43:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AF28C10E644; Fri, 11 Aug 2023 04:43:15 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id AE16F10E641; Fri, 11 Aug 2023 04:43:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691728992; x=1723264992; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wQ6SUgwc051LWxzshtFxzYkiYuHbwKJMeWigrpB7ikA=; b=RhLlC+fbMjkR0SCfD5wnvxPLfHMAlOy5IQscx1N9camphgeNP/ofg2L8 CAXTkSafO6TpSrjw1XK5xIPjhiyZQMOqNCXyVamUZ7/RpJgiALZI/wZ4e P+4nxWfld3bjRryeZR40f7OA9PHN9+U0dc6UZYDddGtcyi5DchSuG2xi/ N4aqWUYCIa5WPztD6CGQFW65jvJ7CfR6QE8g8G3pkXnjUWTlYkfdHvrMI dTk7Ki6Bt03f9ufPYMnP34f9xVM0jtzqX2kMmO1Rbo+RxM28OnzYjGP/k vz2DBuZHARDNZKxeQMsMOwNfyWCF40F+Mi1YJQFe21OleFQNRa+e5w0AR w==; X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="351197202" X-IronPort-AV: E=Sophos;i="6.01,164,1684825200"; d="scan'208";a="351197202" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2023 21:43:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="802533477" X-IronPort-AV: E=Sophos;i="6.01,164,1684825200"; d="scan'208";a="802533477" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga004.fm.intel.com with ESMTP; 10 Aug 2023 21:43:12 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 2/3] drm/i915/pxp/mtl: Update pxp-firmware packet size Date: Thu, 10 Aug 2023 21:43:09 -0700 Message-Id: <20230811044310.944883-3-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230811044310.944883-1-alan.previn.teres.alexis@intel.com> References: <20230811044310.944883-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Update the GSC-fw input/output HECI packet size to match updated internal fw specs. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h index 0165d38fbead..fa460491ce42 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h @@ -15,7 +15,7 @@ #define PXP43_CMDID_INIT_SESSION 0x00000036 /* PXP-Packet sizes for MTL's GSCCS-HECI instruction */ -#define PXP43_MAX_HECI_INOUT_SIZE (SZ_32K) +#define PXP43_MAX_HECI_INOUT_SIZE (SZ_64K) /* PXP-Packet size for MTL's NEW_HUC_AUTH instruction */ #define PXP43_HUC_AUTH_INOUT_SIZE (SZ_4K) From patchwork Fri Aug 11 04:43:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Teres Alexis, Alan Previn" X-Patchwork-Id: 13350071 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A489C04A94 for ; Fri, 11 Aug 2023 04:43:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A794C10E648; Fri, 11 Aug 2023 04:43:19 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id C396A10E63F; Fri, 11 Aug 2023 04:43:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1691728992; x=1723264992; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pgHj6dnivvbPfZkEjEXKTLHpXx6pnIn4NazSOuGBqFs=; b=AdtsaaXAnmOqz0VgODkwmd+9ZDCSB0CbWxffGzm5RdcaA2u69/wxDaBJ NQfWuvueRSMwDgvr11jeQRZiQt2yXcqMNEHPJCEGyBfsgGrMrpH9+u244 msDtnD6jbY1queGmFM3KOMID+Ezs/KKcDE7RzEomEWYe2Z7ygp0qK32CP IXCQMbmEiW8C5QiLwB0vHG2OwPWRKQdOgW+GNLxmUZn/ivqNZUsAyzdGF c03HcCxWrMWDSUe4BnQBh54Y3XOKUDsZrXlKIPaZfkNAztLrvaosDXKyC 13wV3zFWhYAB2V+V1WNJmVZiEs0uQnfEy0MDoYfJtyZ5V0XMRaU//Aupz g==; X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="351197203" X-IronPort-AV: E=Sophos;i="6.01,164,1684825200"; d="scan'208";a="351197203" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Aug 2023 21:43:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10798"; a="802533480" X-IronPort-AV: E=Sophos;i="6.01,164,1684825200"; d="scan'208";a="802533480" Received: from aalteres-desk.fm.intel.com ([10.80.57.53]) by fmsmga004.fm.intel.com with ESMTP; 10 Aug 2023 21:43:12 -0700 From: Alan Previn To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 3/3] drm/i915/gt/pxp: User PXP contexts requires runalone bit in lrc Date: Thu, 10 Aug 2023 21:43:10 -0700 Message-Id: <20230811044310.944883-4-alan.previn.teres.alexis@intel.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230811044310.944883-1-alan.previn.teres.alexis@intel.com> References: <20230811044310.944883-1-alan.previn.teres.alexis@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniele Ceraolo Spurio , dri-devel@lists.freedesktop.org, Alan Previn Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Meteorlake onwards, HW specs require that all user contexts that run on render or compute engines and require PXP must enforce run-alone bit in lrc. Add this enforcement for protected contexts. Signed-off-by: Alan Previn --- drivers/gpu/drm/i915/gt/intel_lrc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 957d0aeb0c02..2dfa49a04172 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -845,6 +845,16 @@ lrc_setup_indirect_ctx(u32 *regs, lrc_ring_indirect_offset_default(engine) << 6; } +static bool ctx_needs_runalone(const struct intel_context *ce) +{ + if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 70) && + ce->gem_context && ce->gem_context->uses_protected_content && + (ce->engine->class == COMPUTE_CLASS || ce->engine->class == RENDER_CLASS)) + return true; + + return false; +} + static void init_common_regs(u32 * const regs, const struct intel_context *ce, const struct intel_engine_cs *engine, @@ -860,6 +870,8 @@ static void init_common_regs(u32 * const regs, if (GRAPHICS_VER(engine->i915) < 11) ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT | CTX_CTRL_RS_CTX_ENABLE); + if (ctx_needs_runalone(ce)) + ctl |= _MASKED_BIT_ENABLE(BIT(7)); regs[CTX_CONTEXT_CONTROL] = ctl; regs[CTX_TIMESTAMP] = ce->stats.runtime.last;