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Wed, 16 Aug 2023 21:22:09 -0700 From: Nicolin Chen To: , , CC: , , , , Subject: [PATCH v2] iommu/arm-smmu-v3: Allow default substream bypass with a pasid support Date: Wed, 16 Aug 2023 21:21:35 -0700 Message-ID: <20230817042135.32822-1-nicolinc@nvidia.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A7:EE_|SA3PR12MB8812:EE_ X-MS-Office365-Filtering-Correlation-Id: 234a582a-c4e7-4739-ef76-08db9ed98fdb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: T7KrlOURmzVwGJTRX+fJOslic5WYLFhLJodX1SzNeC+sHpYcq6ntK16QQ+SCa+jXw9E8pts1rWm1Bqa4PzHttSMdnOS1s4KdQxqvCKW9CiD5RHUfEMahsiaHVbHsR5c2QUXukL/q34n2HJEZPWwsDGPvdvlIJac6mKTh9/aPzfZzwG+C/dSHmzrlm7XjwDX0aDgULXknB6Vwnh77qYVsrGdB4BqXlfOZ4OZdjBcWMATHDjyd6IMOgHV7iqR8jsBEmVUMFetqdSI7AowAivmbzJmmWa4KEzecabxk9YGCwvU88GeLDcMCNqnFecryQy20eDaDWAKB/OxgIALNvycg9WxL8fbzALoBnnekkTUM9a3JEcM+Nl+njtYljKDCKdsAjSK4dda5+f4svQeevk2KhYcLnSm2JwuhJXFpk1KFsWFbg9qmK+w2EYUrD0mujH0ouNBxea7hRnuc+UI3VbGpS7hyDUqnR1icxvsFrOlCVh8ydsSb93HNfcLAur2lmuFiQ270D/phNnDPlePW4oB2T6bBunU1Y58LIdGJJEH6Rcziih+THo2jAidMwD24NmXegYbqkVmZG10PiREzKJPbl0iVe6edyBEpTbMA4CcEk32vLwAwoeelQqzFhtMqfrkDGVOo7VcoxXPa6GlXZPdOV72HnBFQbbjrksLvawcxSgyHa11OQbtwwAqudG/hKEU54XTEyam2bw7Xfpe3YtPIz6VOgFcHovPvARSDGLhMJnC6Lb7Dmwsya5R8m2cDE3ZBHMnIOHbLaLXo27ABhdVgg5JGe5kFiNJrFcMPfKgsdKXWFRv3SYqCcRigey37blTAwdxNtVLVlzrQtvfFohuUewpcyO19T4JmnBa69JdoU4VkCjknplpsmHtTBurox9w6 X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(346002)(136003)(376002)(451199024)(1800799009)(186009)(82310400011)(36840700001)(46966006)(40470700004)(7636003)(316002)(110136005)(54906003)(6636002)(356005)(82740400003)(70586007)(70206006)(966005)(5660300002)(41300700001)(36860700001)(47076005)(4326008)(8936002)(8676002)(26005)(2906002)(40460700003)(83380400001)(40480700001)(426003)(336012)(478600001)(86362001)(7696005)(36756003)(6666004)(1076003)(2616005)(414714003)(473944003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Aug 2023 04:22:26.0142 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 234a582a-c4e7-4739-ef76-08db9ed98fdb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8812 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230816_212239_839529_B75F0E7F X-CRM114-Status: GOOD ( 23.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When an iommu_domain is set to IOMMU_DOMAIN_IDENTITY, the driver sets the arm_smmu_domain->stage to ARM_SMMU_DOMAIN_BYPASS and skips the allocation of a CD table, and then sets STRTAB_STE_0_CFG_BYPASS to the CONFIG field of the STE. This works well for devices that only have one substream, i.e. pasid disabled. With a pasid-capable device, however, there could be a use case where it allows an IDENTITY domain attachment without disabling its pasid feature. This requires the driver to allocate a multi-entry CD table to attach the IDENTITY domain to its default substream and to configure the S1DSS filed of the STE to STRTAB_STE_1_S1DSS_BYPASS. So, there is a missing link here between the STE setup and an IDENTITY domain attachment. Add a new stage ARM_SMMU_DOMAIN_BYPASS_S1DSS to tag this configuration by overriding the ARM_SMMU_DOMAIN_BYPASS if the device has pasid capability. This new tag will allow the driver allocating a CD table yet skipping an CD insertion from the IDENTITY domain, and setting up the STE accordingly. In a use case of ARM_SMMU_DOMAIN_BYPASS_S1DSS, the SHCFG field of the STE should be set to STRTAB_STE_1_SHCFG_INCOMING. In other cases of having a CD table, the shareability comes from a CD, not the SHCFG field: according to "13.5 Summary of attribute/permission configuration fields" in the spec the SHCFG field value is irrelevant. So, always configure the SHCFG field of the STE to STRTAB_STE_1_SHCFG_INCOMING when a CD table is present, for simplification. Signed-off-by: Nicolin Chen --- Changelog v2: * Rebased on top of Michael's series reworking CD table ownership: https://lore.kernel.org/all/20230816131925.2521220-1-mshavit@google.com/ * Added a new ARM_SMMU_DOMAIN_BYPASS_S1DSS stage to tag the use case v1: https://lore.kernel.org/all/20230627033326.5236-1-nicolinc@nvidia.com/ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 22 +++++++++++++++++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 21 insertions(+), 2 deletions(-) base-commit: aed5d77d0c3d55d1949db89f27cf7a3981261ef4 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index b27011b2bec9..860db4fbb995 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1271,6 +1271,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, * 3. Update Config, sync */ u64 val = le64_to_cpu(dst[0]); + u8 s1dss = STRTAB_STE_1_S1DSS_SSID0; bool ste_live = false; struct arm_smmu_device *smmu = NULL; struct arm_smmu_ctx_desc_cfg *cd_table = NULL; @@ -1290,6 +1291,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, if (smmu_domain) { switch (smmu_domain->stage) { + case ARM_SMMU_DOMAIN_BYPASS_S1DSS: + s1dss = STRTAB_STE_1_S1DSS_BYPASS; + fallthrough; case ARM_SMMU_DOMAIN_S1: cd_table = &master->cd_table; break; @@ -1348,7 +1352,8 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, BUG_ON(ste_live); dst[1] = cpu_to_le64( - FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) | + FIELD_PREP(STRTAB_STE_1_S1DSS, s1dss) | + FIELD_PREP(STRTAB_STE_1_SHCFG, STRTAB_STE_1_SHCFG_INCOMING) | FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) | @@ -2435,6 +2440,16 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) } else if (smmu_domain->smmu != smmu) ret = -EINVAL; + /* + * When attaching an IDENTITY domain to a master with pasid capability, + * the master can still enable SVA feature by allocating a multi-entry + * CD table and attaching the IDENTITY domain to its default substream + * that alone can be byassed using the S1DSS field of the STE. + */ + if (smmu_domain->stage == ARM_SMMU_DOMAIN_BYPASS && master->ssid_bits && + smmu->features & ARM_SMMU_FEAT_TRANS_S1) + smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS_S1DSS; + mutex_unlock(&smmu_domain->init_mutex); if (ret) return ret; @@ -2456,7 +2471,8 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) list_add(&master->domain_head, &smmu_domain->devices); spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); - if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 || + smmu_domain->stage == ARM_SMMU_DOMAIN_BYPASS_S1DSS) { if (!master->cd_table.cdtab) { ret = arm_smmu_alloc_cd_tables(master); if (ret) { @@ -2464,7 +2480,9 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) goto out_list_del; } } + } + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { /* * Prevent SVA from concurrently modifying the CD or writing to * the CD entry diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index b7a91c8e9b52..e9361f85c91c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -714,6 +714,7 @@ enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S2, ARM_SMMU_DOMAIN_NESTED, ARM_SMMU_DOMAIN_BYPASS, + ARM_SMMU_DOMAIN_BYPASS_S1DSS, /* Bypass S1 default substream only */ }; struct arm_smmu_domain {