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[111.98.113.1]) by smtp.gmail.com with ESMTPSA id c15-20020a170903234f00b001b9be3b94d3sm6131302plh.140.2023.08.20.23.20.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Aug 2023 23:20:56 -0700 (PDT) From: Tatsuyuki Ishi To: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org Subject: [PATCH v2 1/4] drm/amdgpu: Add separate mode for syncing DMA_RESV_USAGE_BOOKKEEP. Date: Mon, 21 Aug 2023 15:20:02 +0900 Message-ID: <20230821062005.109771-2-ishitatsuyuki@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230821062005.109771-1-ishitatsuyuki@gmail.com> References: <20230821062005.109771-1-ishitatsuyuki@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tatsuyuki Ishi , christian.koenig@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Bas Nieuwenhuizen To prep for allowing different sync modes in a follow-up patch. Signed-off-by: Bas Nieuwenhuizen Signed-off-by: Tatsuyuki Ishi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 11 +++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 11 ++++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 +- 8 files changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index edb35a88cb78..240556838094 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1287,7 +1287,7 @@ static int process_sync_pds_resv(struct amdkfd_process_info *process_info, struct amdgpu_bo *pd = peer_vm->root.bo; ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv, - AMDGPU_SYNC_NE_OWNER, + AMDGPU_SYNC_NE_OWNER, AMDGPU_SYNC_NE_OWNER, AMDGPU_FENCE_OWNER_KFD); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 977e1804718d..2cb814de0149 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1203,7 +1203,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) sync_mode = amdgpu_bo_explicit_sync(bo) ? AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER; r = amdgpu_sync_resv(p->adev, &p->sync, resv, sync_mode, - &fpriv->vm); + AMDGPU_SYNC_EXPLICIT, &fpriv->vm); if (r) return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index f7905bce0de1..f20c1d2757e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1450,7 +1450,8 @@ void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, * * @adev: amdgpu device pointer * @resv: reservation object to sync to - * @sync_mode: synchronization mode + * @implicit_sync_mode: synchronization mode for usage <= DMA_RESV_USAGE_READ + * @explicit_sync_mode: synchronization mode for usage DMA_RESV_USAGE_BOOKKEEP * @owner: fence owner * @intr: Whether the wait is interruptible * @@ -1460,14 +1461,15 @@ void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, * 0 on success, errno otherwise. */ int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, - enum amdgpu_sync_mode sync_mode, void *owner, + enum amdgpu_sync_mode implicit_sync_mode, + enum amdgpu_sync_mode explicit_sync_mode, void *owner, bool intr) { struct amdgpu_sync sync; int r; amdgpu_sync_create(&sync); - amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); + amdgpu_sync_resv(adev, &sync, resv, implicit_sync_mode, explicit_sync_mode, owner); r = amdgpu_sync_wait(&sync, intr); amdgpu_sync_free(&sync); return r; @@ -1488,7 +1490,8 @@ int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, - AMDGPU_SYNC_NE_OWNER, owner, intr); + AMDGPU_SYNC_NE_OWNER, AMDGPU_SYNC_EXPLICIT, + owner, intr); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 05496b97ef93..e982b5815969 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -350,7 +350,8 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo); void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, bool shared); int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, - enum amdgpu_sync_mode sync_mode, void *owner, + enum amdgpu_sync_mode implicit_sync_mode, + enum amdgpu_sync_mode explicit_sync_mode, void *owner, bool intr); int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr); u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index dcd8c066bc1f..e94f90d87902 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -226,14 +226,15 @@ static bool amdgpu_sync_test_fence(struct amdgpu_device *adev, * @adev: amdgpu device * @sync: sync object to add fences from reservation object to * @resv: reservation object with embedded fence - * @mode: how owner affects which fences we sync to + * @implicit_mode: how owner affects which fences with usage <= DMA_RESV_USAGE_READ we sync to + * @explicit_mode: how owner affects which fences with usage DMA_RESV_USAGE_BOOKKEEP we sync to * @owner: owner of the planned job submission * * Sync to the fence */ int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync, - struct dma_resv *resv, enum amdgpu_sync_mode mode, - void *owner) + struct dma_resv *resv, enum amdgpu_sync_mode implicit_mode, + enum amdgpu_sync_mode explicit_mode, void *owner) { struct dma_resv_iter cursor; struct dma_fence *f; @@ -246,6 +247,10 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync, dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, f) { dma_fence_chain_for_each(f, f) { struct dma_fence *tmp = dma_fence_chain_contained(f); + enum amdgpu_sync_mode mode = implicit_mode; + + if (dma_resv_iter_usage(&cursor) >= DMA_RESV_USAGE_BOOKKEEP) + mode = explicit_mode; if (amdgpu_sync_test_fence(adev, mode, owner, tmp)) { r = amdgpu_sync_fence(sync, f); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h index cf1e9e858efd..7758105a1d6c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h @@ -49,8 +49,8 @@ struct amdgpu_sync { void amdgpu_sync_create(struct amdgpu_sync *sync); int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f); int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync, - struct dma_resv *resv, enum amdgpu_sync_mode mode, - void *owner); + struct dma_resv *resv, enum amdgpu_sync_mode implicit_mode, + enum amdgpu_sync_mode explicit_mode, void *owner); struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, struct amdgpu_ring *ring); struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c index 31913ae86de6..f10332e1c6c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c @@ -51,7 +51,7 @@ static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p, if (!resv) return 0; - return amdgpu_bo_sync_wait_resv(p->adev, resv, sync_mode, p->vm, true); + return amdgpu_bo_sync_wait_resv(p->adev, resv, sync_mode, sync_mode, p->vm, true); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 349416e176a1..e259a51e7c56 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -98,7 +98,7 @@ static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p, return 0; amdgpu_sync_create(&sync); - r = amdgpu_sync_resv(p->adev, &sync, resv, sync_mode, p->vm); + r = amdgpu_sync_resv(p->adev, &sync, resv, sync_mode, sync_mode, p->vm); if (!r) r = amdgpu_sync_push_to_job(&sync, p->job); amdgpu_sync_free(&sync); From patchwork Mon Aug 21 06:20:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tatsuyuki Ishi X-Patchwork-Id: 13359181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18DF4EE49A5 for ; Mon, 21 Aug 2023 06:21:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1361D10E1D0; Mon, 21 Aug 2023 06:21:05 +0000 (UTC) Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4718F10E1C7; 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[111.98.113.1]) by smtp.gmail.com with ESMTPSA id d24-20020a17090ac25800b00263e1db8460sm7155225pjx.9.2023.08.20.23.20.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Aug 2023 23:20:58 -0700 (PDT) From: Tatsuyuki Ishi To: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org Subject: [PATCH v2 2/4] drm/amdgpu: Allow explicit sync for VM ops. Date: Mon, 21 Aug 2023 15:20:03 +0900 Message-ID: <20230821062005.109771-3-ishitatsuyuki@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230821062005.109771-1-ishitatsuyuki@gmail.com> References: <20230821062005.109771-1-ishitatsuyuki@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tatsuyuki Ishi , christian.koenig@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Bas Nieuwenhuizen This should be okay because moves themselves use KERNEL usage and hence still sync with BOOKKEEP usage. Then any later submits still wait on any pending VM operations. (i.e. we only made VM ops not wait on BOOKKEEP submits, not the other way around) Signed-off-by: Bas Nieuwenhuizen Signed-off-by: Tatsuyuki Ishi --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c index f10332e1c6c0..e898a549f86d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c @@ -51,7 +51,8 @@ static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p, if (!resv) return 0; - return amdgpu_bo_sync_wait_resv(p->adev, resv, sync_mode, sync_mode, p->vm, true); + return amdgpu_bo_sync_wait_resv(p->adev, resv, sync_mode, + AMDGPU_SYNC_EXPLICIT, p->vm, true); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index e259a51e7c56..8cb427710d66 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -98,7 +98,8 @@ static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p, return 0; amdgpu_sync_create(&sync); - r = amdgpu_sync_resv(p->adev, &sync, resv, sync_mode, sync_mode, p->vm); + r = amdgpu_sync_resv(p->adev, &sync, resv, sync_mode, + AMDGPU_SYNC_EXPLICIT, p->vm); if (!r) r = amdgpu_sync_push_to_job(&sync, p->job); amdgpu_sync_free(&sync); From patchwork Mon Aug 21 06:20:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tatsuyuki Ishi X-Patchwork-Id: 13359182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0493EE49AC for ; Mon, 21 Aug 2023 06:21:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5205610E1D8; Mon, 21 Aug 2023 06:21:06 +0000 (UTC) Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by gabe.freedesktop.org (Postfix) with ESMTPS id B67CC10E1D0; Mon, 21 Aug 2023 06:21:02 +0000 (UTC) Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-68a56ed12c0so77054b3a.0; Sun, 20 Aug 2023 23:21:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1692598862; x=1693203662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f7zNtx1npcyt6rHphdv4uT7irT8bAyzRl0M6M2dMjgk=; b=ajYlXTb+JOShhXkQlEyz206rkV9OlxQV9+ukfLmuZn9NlC0xy+8VrUWHRkqiqvQdJE pFJyf1B8/N/Tnv8L4vvQx3CYkC9c1uZN600RdSnymseySEo4pDdUSWikN8OdTM5oFgzR 4nXKZr9Z1AHjrB3PsA5wH7TyZ5UvT5d95A4WEE8fhwA1qQksrBV8sw6YijphF6z9H9QZ wnmvJsyONU1ufr2VK1CXNSs60mV6inaPMyn12Jq2O/F+7YUMtFBzV2lC9FNFWcPhNNqR +ONZNTnm4gAR1i0di7VV3/vSN0GAG2wo7Mc1qQMqwfYBFPN5spZ4NQbjgzMF9FeU1EVh ZIEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692598862; x=1693203662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f7zNtx1npcyt6rHphdv4uT7irT8bAyzRl0M6M2dMjgk=; b=NxxKig9L6XxfUN9hXoU19+OUGX/jT7pWlkfSib+i82SRaOCzo/oAPLBLIQFOnZqYw4 mXW63HKVXD9LC3uFnatssPYspR5MQQWV8fR011ciQFUw3XiUzGNlrrLFUmCVroWEHki8 fWmMwxzLcVDT1McGLc2DHz7/L1LutHGMNTBNzyLnQfOLbyBpj9GGKuIONeGfHnlgko/7 K3JGhmJZQVgxRiwjTpAe2yhrmhseckIp1lsiFQbT8SeYHX5AEZyeLpMSdacmQEEPi+GB ebXjAk2YGaLhb95zH2pTRFNn6HYtbZCdbB21l0IlB+klRBjCLP7k98a3Zi5QeaeVgZPg BGxQ== X-Gm-Message-State: AOJu0YybUMcd/4Ap7AC4Yc5uTwhfZN6ku2S5Wc3Q5pOTyWUztf/1EbTp q5rp9mqUyY8GHL4Gja4nJQeZ+BrPZ+Y8yelt X-Google-Smtp-Source: AGHT+IFLtBRsV54dk8YwvAEx33Iu8ETlOW/VdzwRGtD54sT+fErJpTX4AxsrGRKLLJNIEwF0cwdEFA== X-Received: by 2002:a17:902:e746:b0:1b8:35fa:cdcc with SMTP id p6-20020a170902e74600b001b835facdccmr7269102plf.5.1692598861722; Sun, 20 Aug 2023 23:21:01 -0700 (PDT) Received: from localhost (zz20184013906F627101.userreverse.dion.ne.jp. [111.98.113.1]) by smtp.gmail.com with ESMTPSA id ja1-20020a170902efc100b001b8c6662094sm6124172plb.188.2023.08.20.23.21.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Aug 2023 23:21:01 -0700 (PDT) From: Tatsuyuki Ishi To: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org Subject: [PATCH v2 3/4] drm/amdgpu: Add option to disable implicit sync for a context. Date: Mon, 21 Aug 2023 15:20:04 +0900 Message-ID: <20230821062005.109771-4-ishitatsuyuki@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230821062005.109771-1-ishitatsuyuki@gmail.com> References: <20230821062005.109771-1-ishitatsuyuki@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tatsuyuki Ishi , christian.koenig@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Bas Nieuwenhuizen This changes all BO usages in a submit to BOOKKEEP instead of READ, which effectively disables implicit sync for these submits. This is configured at a context level using the existing IOCTL. Signed-off-by: Bas Nieuwenhuizen Co-developed-by: Tatsuyuki Ishi Signed-off-by: Tatsuyuki Ishi --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 16 +++++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 30 +++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 1 + include/uapi/drm/amdgpu_drm.h | 4 ++++ 4 files changed, 47 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 2cb814de0149..008547f97fd1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1200,8 +1200,11 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) struct dma_resv *resv = bo->tbo.base.resv; enum amdgpu_sync_mode sync_mode; - sync_mode = amdgpu_bo_explicit_sync(bo) ? - AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER; + if (amdgpu_bo_explicit_sync(bo) || p->ctx->disable_implicit_sync) + sync_mode = AMDGPU_SYNC_EXPLICIT; + else + sync_mode = AMDGPU_SYNC_NE_OWNER; + r = amdgpu_sync_resv(p->adev, &p->sync, resv, sync_mode, AMDGPU_SYNC_EXPLICIT, &fpriv->vm); if (r) @@ -1322,11 +1325,16 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, dma_resv_add_fence(gobj->resv, &p->jobs[i]->base.s_fence->finished, - DMA_RESV_USAGE_READ); + p->ctx->disable_implicit_sync ? + DMA_RESV_USAGE_BOOKKEEP : + DMA_RESV_USAGE_READ); } /* The gang leader as remembered as writer */ - dma_resv_add_fence(gobj->resv, p->fence, DMA_RESV_USAGE_WRITE); + dma_resv_add_fence(gobj->resv, p->fence, + p->ctx->disable_implicit_sync ? + DMA_RESV_USAGE_BOOKKEEP : + DMA_RESV_USAGE_WRITE); } seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_leader_idx], diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index 0dc9c655c4fb..fe6f30d8fd70 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -661,6 +661,30 @@ static int amdgpu_ctx_stable_pstate(struct amdgpu_device *adev, return r; } +static int amdgpu_ctx_set_implicit_sync(struct amdgpu_device *adev, + struct amdgpu_fpriv *fpriv, uint32_t id, + bool enable) +{ + struct amdgpu_ctx *ctx; + struct amdgpu_ctx_mgr *mgr; + + if (!fpriv) + return -EINVAL; + + mgr = &fpriv->ctx_mgr; + mutex_lock(&mgr->lock); + ctx = idr_find(&mgr->ctx_handles, id); + if (!ctx) { + mutex_unlock(&mgr->lock); + return -EINVAL; + } + + ctx->disable_implicit_sync = !enable; + + mutex_unlock(&mgr->lock); + return 0; +} + int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { @@ -709,6 +733,12 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, return -EINVAL; r = amdgpu_ctx_stable_pstate(adev, fpriv, id, true, &stable_pstate); break; + case AMDGPU_CTX_OP_SET_IMPLICIT_SYNC: + if ((args->in.flags & ~AMDGPU_CTX_IMPLICIT_SYNC_ENABLED) || args->in.priority) + return -EINVAL; + r = amdgpu_ctx_set_implicit_sync(adev, fpriv, id, + args->in.flags & ~AMDGPU_CTX_IMPLICIT_SYNC_ENABLED); + break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h index 85376baaa92f..a330e5b65d30 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h @@ -58,6 +58,7 @@ struct amdgpu_ctx { unsigned long ras_counter_ue; uint32_t stable_pstate; struct amdgpu_ctx_mgr *ctx_mgr; + bool disable_implicit_sync; }; struct amdgpu_ctx_mgr { diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 79b14828d542..6a0168436c31 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -226,6 +226,7 @@ union drm_amdgpu_bo_list { #define AMDGPU_CTX_OP_QUERY_STATE2 4 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 +#define AMDGPU_CTX_OP_SET_IMPLICIT_SYNC 7 /* GPU reset status */ #define AMDGPU_CTX_NO_RESET 0 @@ -268,6 +269,9 @@ union drm_amdgpu_bo_list { #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 +/* opt-out of implicit sync */ +#define AMDGPU_CTX_IMPLICIT_SYNC_ENABLED 1 + struct drm_amdgpu_ctx_in { /** AMDGPU_CTX_OP_* */ __u32 op; From patchwork Mon Aug 21 06:20:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tatsuyuki Ishi X-Patchwork-Id: 13359183 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD08FEE49B5 for ; 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[111.98.113.1]) by smtp.gmail.com with ESMTPSA id mv22-20020a17090b199600b00263987a50fcsm7127771pjb.22.2023.08.20.23.21.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Aug 2023 23:21:04 -0700 (PDT) From: Tatsuyuki Ishi To: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org Subject: [PATCH v2 4/4] drm/amdgpu: Bump amdgpu driver version. Date: Mon, 21 Aug 2023 15:20:05 +0900 Message-ID: <20230821062005.109771-5-ishitatsuyuki@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230821062005.109771-1-ishitatsuyuki@gmail.com> References: <20230821062005.109771-1-ishitatsuyuki@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tatsuyuki Ishi , christian.koenig@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Bas Nieuwenhuizen For detection of the new explicit sync functionality without having to try the ioctl. Signed-off-by: Bas Nieuwenhuizen Signed-off-by: Tatsuyuki Ishi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index e90f730eb715..d2eef46f0fcb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -113,9 +113,10 @@ * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi * 3.53.0 - Support for GFX11 CP GFX shadowing * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support + * - 3.55.0 - Add AMDGPU_CTX_OP_SET_IMPLICIT_SYNC context operation. */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 54 +#define KMS_DRIVER_MINOR 55 #define KMS_DRIVER_PATCHLEVEL 0 unsigned int amdgpu_vram_limit = UINT_MAX;