From patchwork Mon Aug 21 08:14:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359242 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02C261FB3 for ; Mon, 21 Aug 2023 08:14:52 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69B2E93 for ; Mon, 21 Aug 2023 01:14:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692605691; x=1724141691; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=K9x8FDf/YdpQXwHLWBnorxtFd/JUNWyZ5i86X1WOEOs=; b=Wt8jSW9LugTg4cZf0Ksm9vDZmrgvVoI5E2NiwmJ8Xzcz9BWfGyVvk7UM jw2MVHGZJ/FMHE9OF+blOlKL3fZC2HK8e2a2G59AYRcCwdSLvHubGzXaG /brvbPil5OOGAs4XhxayxNT19OC6wqhaKQgC1/gPWQjasTK/H8Doa8lEq qeNOdvX6RGHQi4+YrE9dx83Tyskk/NLT7D7qZksGFbNXJvik+QxbQGEYc nROqBBZX+JSJzAu1gn6ONlQ2QF9ZBA7wNXI5aWjVNvwR+s+fIQP37bZuD wvg9uGNZ6HnPZ9jvyufhD7YBmbFzHIK3L79VQJLmxudEAkbURTJcswOGx Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="376280345" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="376280345" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2023 01:14:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="685577375" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577375" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:14:46 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 01/15] ice: add parser create and destroy skeleton Date: Mon, 21 Aug 2023 16:14:24 +0800 Message-Id: <20230821081438.2937934-2-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Add new parser module which can parse a packet in binary and generate information like ptype, protocol/offset pairs and flags which can be used to feed the FXP profile creation directly. The patch added skeleton of the create and destroy APIs: ice_parser_create ice_parser_destroy Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/ice_common.h | 4 +++ drivers/net/ethernet/intel/ice/ice_ddp.c | 10 +++---- drivers/net/ethernet/intel/ice/ice_ddp.h | 13 ++++++++ drivers/net/ethernet/intel/ice/ice_parser.c | 33 +++++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_parser.h | 13 ++++++++ 5 files changed, 68 insertions(+), 5 deletions(-) create mode 100644 drivers/net/ethernet/intel/ice/ice_parser.c create mode 100644 drivers/net/ethernet/intel/ice/ice_parser.h diff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h index 8ba5f935a092..528dde976373 100644 --- a/drivers/net/ethernet/intel/ice/ice_common.h +++ b/drivers/net/ethernet/intel/ice/ice_common.h @@ -9,10 +9,14 @@ #include "ice_type.h" #include "ice_nvm.h" #include "ice_flex_pipe.h" +#include "ice_parser.h" #include #include "ice_switch.h" #include "ice_fdir.h" +#define BITS_PER_WORD 16 +#define BITMAP_MASK(n) GENMASK(((n) - 1), 0) + #define ICE_SQ_SEND_DELAY_TIME_MS 10 #define ICE_SQ_SEND_MAX_EXECUTE 3 diff --git a/drivers/net/ethernet/intel/ice/ice_ddp.c b/drivers/net/ethernet/intel/ice/ice_ddp.c index d71ed210f9c4..3bdf03b9ee71 100644 --- a/drivers/net/ethernet/intel/ice/ice_ddp.c +++ b/drivers/net/ethernet/intel/ice/ice_ddp.c @@ -288,11 +288,11 @@ void *ice_pkg_enum_section(struct ice_seg *ice_seg, struct ice_pkg_enum *state, * indicates a base offset of 10, and the index for the entry is 2, then * section handler function should set the offset to 10 + 2 = 12. */ -static void *ice_pkg_enum_entry(struct ice_seg *ice_seg, - struct ice_pkg_enum *state, u32 sect_type, - u32 *offset, - void *(*handler)(u32 sect_type, void *section, - u32 index, u32 *offset)) +void *ice_pkg_enum_entry(struct ice_seg *ice_seg, + struct ice_pkg_enum *state, u32 sect_type, + u32 *offset, + void *(*handler)(u32 sect_type, void *section, + u32 index, u32 *offset)) { void *entry; diff --git a/drivers/net/ethernet/intel/ice/ice_ddp.h b/drivers/net/ethernet/intel/ice/ice_ddp.h index 37eadb3d27a8..da5dfeed3b1f 100644 --- a/drivers/net/ethernet/intel/ice/ice_ddp.h +++ b/drivers/net/ethernet/intel/ice/ice_ddp.h @@ -238,10 +238,18 @@ struct ice_meta_sect { #define ICE_SID_CDID_KEY_BUILDER_RSS 47 #define ICE_SID_CDID_REDIR_RSS 48 +#define ICE_SID_RXPARSER_CAM 50 +#define ICE_SID_RXPARSER_NOMATCH_CAM 51 +#define ICE_SID_RXPARSER_IMEM 52 #define ICE_SID_RXPARSER_MARKER_PTYPE 55 #define ICE_SID_RXPARSER_BOOST_TCAM 56 +#define ICE_SID_RXPARSER_PROTO_GRP 57 #define ICE_SID_RXPARSER_METADATA_INIT 58 +#define ICE_SID_TXPARSER_NOMATCH_CAM 61 #define ICE_SID_TXPARSER_BOOST_TCAM 66 +#define ICE_SID_RXPARSER_MARKER_GRP 72 +#define ICE_SID_RXPARSER_PG_SPILL 76 +#define ICE_SID_RXPARSER_NOMATCH_SPILL 78 #define ICE_SID_XLT0_PE 80 #define ICE_SID_XLT_KEY_BUILDER_PE 81 @@ -437,6 +445,11 @@ int ice_update_pkg(struct ice_hw *hw, struct ice_buf *bufs, u32 count); int ice_pkg_buf_reserve_section(struct ice_buf_build *bld, u16 count); u16 ice_pkg_buf_get_active_sections(struct ice_buf_build *bld); +void * +ice_pkg_enum_entry(struct ice_seg *ice_seg, struct ice_pkg_enum *state, + u32 sect_type, u32 *offset, + void *(*handler)(u32 sect_type, void *section, + u32 index, u32 *offset)); void *ice_pkg_enum_section(struct ice_seg *ice_seg, struct ice_pkg_enum *state, u32 sect_type); diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c new file mode 100644 index 000000000000..747dfad66db2 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_parser.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2023 Intel Corporation */ + +#include "ice_common.h" + +/** + * ice_parser_create - create a parser instance + * @hw: pointer to the hardware structure + * @psr: output parameter for a new parser instance be created + */ +int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr) +{ + struct ice_parser *p; + + p = devm_kzalloc(ice_hw_to_dev(hw), sizeof(struct ice_parser), + GFP_KERNEL); + if (!p) + return -ENOMEM; + + p->hw = hw; + + *psr = p; + return 0; +} + +/** + * ice_parser_destroy - destroy a parser instance + * @psr: pointer to a parser instance + */ +void ice_parser_destroy(struct ice_parser *psr) +{ + devm_kfree(ice_hw_to_dev(psr->hw), psr); +} diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h new file mode 100644 index 000000000000..85c470235e67 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_parser.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2023 Intel Corporation */ + +#ifndef _ICE_PARSER_H_ +#define _ICE_PARSER_H_ + +struct ice_parser { + struct ice_hw *hw; /* pointer to the hardware structure */ +}; + +int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr); +void ice_parser_destroy(struct ice_parser *psr); +#endif /* _ICE_PARSER_H_ */ From patchwork Mon Aug 21 08:14:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359243 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 500772105 for ; Mon, 21 Aug 2023 08:14:56 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBF51BB for ; Mon, 21 Aug 2023 01:14:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692605693; x=1724141693; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zF5E0sbGQJ6dovqEFRSnNHAoKnbVLxIyioTreUZySh8=; b=OoFTWEWUaOsuK97dmF8wSkMzIWQoUK65K2YOZEoQGjybjaAzNIJ9sANO 6ftK4vdKVlDHy9wBRDdszJWNp9VvmLoN/CvGYa7QQBVNzBQXPONViK8nt 2bjO+Tsbwm00H9SuVm6wsYpU3IWb97hvnC6870Z455Z2H2r5bsEIE/mep DnE8U2vL5Pm6N2fYCpOSzQVartqx7WMVheLHhW6JIWMXb/D24BdLYT4Wi CQlgiCPuglvBu3q6Wy0XoWuaIuwlfe616s50BSRd+hsNap/yLgnixphMD z2swqP9GEDZ5pMX0E0bU5Tvnpzmv3Mkva6bT36t4SPLoCZ42Me0asFuQ0 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="376280376" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="376280376" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2023 01:14:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="685577412" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577412" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:14:49 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 02/15] ice: init imem table for parser Date: Mon, 21 Aug 2023 16:14:25 +0800 Message-Id: <20230821081438.2937934-3-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Parse DDP section ICE_SID_RXPARSER_IMEM into an array of struct ice_imem_item. Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/ice_imem.c | 279 ++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_imem.h | 217 ++++++++++++++ drivers/net/ethernet/intel/ice/ice_parser.c | 97 ++++++ drivers/net/ethernet/intel/ice/ice_parser.h | 8 + .../net/ethernet/intel/ice/ice_parser_util.h | 24 ++ drivers/net/ethernet/intel/ice/ice_type.h | 1 + 6 files changed, 626 insertions(+) create mode 100644 drivers/net/ethernet/intel/ice/ice_imem.c create mode 100644 drivers/net/ethernet/intel/ice/ice_imem.h create mode 100644 drivers/net/ethernet/intel/ice/ice_parser_util.h diff --git a/drivers/net/ethernet/intel/ice/ice_imem.c b/drivers/net/ethernet/intel/ice/ice_imem.c new file mode 100644 index 000000000000..5e6ded40fa6e --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_imem.c @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2023 Intel Corporation */ + +#include "ice_common.h" +#include "ice_parser_util.h" + +static void _ice_imem_bst_bm_dump(struct ice_hw *hw, struct ice_bst_main *bm) +{ + dev_info(ice_hw_to_dev(hw), "boost main:\n"); + dev_info(ice_hw_to_dev(hw), "\talu0 = %d\n", bm->alu0); + dev_info(ice_hw_to_dev(hw), "\talu1 = %d\n", bm->alu1); + dev_info(ice_hw_to_dev(hw), "\talu2 = %d\n", bm->alu2); + dev_info(ice_hw_to_dev(hw), "\tpg = %d\n", bm->pg); +} + +static void _ice_imem_bst_kb_dump(struct ice_hw *hw, + struct ice_bst_keybuilder *kb) +{ + dev_info(ice_hw_to_dev(hw), "boost key builder:\n"); + dev_info(ice_hw_to_dev(hw), "\tpriority = %d\n", kb->prio); + dev_info(ice_hw_to_dev(hw), "\ttsr_ctrl = %d\n", kb->tsr_ctrl); +} + +static void _ice_imem_np_kb_dump(struct ice_hw *hw, + struct ice_np_keybuilder *kb) +{ + dev_info(ice_hw_to_dev(hw), "next proto key builder:\n"); + dev_info(ice_hw_to_dev(hw), "\tops = %d\n", kb->opc); + dev_info(ice_hw_to_dev(hw), "\tstart_or_reg0 = %d\n", + kb->start_reg0); + dev_info(ice_hw_to_dev(hw), "\tlen_or_reg1 = %d\n", kb->len_reg1); +} + +static void _ice_imem_pg_kb_dump(struct ice_hw *hw, + struct ice_pg_keybuilder *kb) +{ + dev_info(ice_hw_to_dev(hw), "parse graph key builder:\n"); + dev_info(ice_hw_to_dev(hw), "\tflag0_ena = %d\n", kb->flag0_ena); + dev_info(ice_hw_to_dev(hw), "\tflag1_ena = %d\n", kb->flag1_ena); + dev_info(ice_hw_to_dev(hw), "\tflag2_ena = %d\n", kb->flag2_ena); + dev_info(ice_hw_to_dev(hw), "\tflag3_ena = %d\n", kb->flag3_ena); + dev_info(ice_hw_to_dev(hw), "\tflag0_idx = %d\n", kb->flag0_idx); + dev_info(ice_hw_to_dev(hw), "\tflag1_idx = %d\n", kb->flag1_idx); + dev_info(ice_hw_to_dev(hw), "\tflag2_idx = %d\n", kb->flag2_idx); + dev_info(ice_hw_to_dev(hw), "\tflag3_idx = %d\n", kb->flag3_idx); + dev_info(ice_hw_to_dev(hw), "\talu_reg_idx = %d\n", kb->alu_reg_idx); +} + +static void _ice_imem_alu_dump(struct ice_hw *hw, + struct ice_alu *alu, int index) +{ + dev_info(ice_hw_to_dev(hw), "alu%d:\n", index); + dev_info(ice_hw_to_dev(hw), "\topc = %d\n", alu->opc); + dev_info(ice_hw_to_dev(hw), "\tsrc_start = %d\n", alu->src_start); + dev_info(ice_hw_to_dev(hw), "\tsrc_len = %d\n", alu->src_len); + dev_info(ice_hw_to_dev(hw), "\tshift_xlate_sel = %d\n", + alu->shift_xlate_sel); + dev_info(ice_hw_to_dev(hw), "\tshift_xlate_key = %d\n", + alu->shift_xlate_key); + dev_info(ice_hw_to_dev(hw), "\tsrc_reg_id = %d\n", alu->src_reg_id); + dev_info(ice_hw_to_dev(hw), "\tdst_reg_id = %d\n", alu->dst_reg_id); + dev_info(ice_hw_to_dev(hw), "\tinc0 = %d\n", alu->inc0); + dev_info(ice_hw_to_dev(hw), "\tinc1 = %d\n", alu->inc1); + dev_info(ice_hw_to_dev(hw), "\tproto_offset_opc = %d\n", + alu->proto_offset_opc); + dev_info(ice_hw_to_dev(hw), "\tproto_offset = %d\n", + alu->proto_offset); + dev_info(ice_hw_to_dev(hw), "\tbranch_addr = %d\n", alu->branch_addr); + dev_info(ice_hw_to_dev(hw), "\timm = %d\n", alu->imm); + dev_info(ice_hw_to_dev(hw), "\tdst_start = %d\n", alu->dst_start); + dev_info(ice_hw_to_dev(hw), "\tdst_len = %d\n", alu->dst_len); + dev_info(ice_hw_to_dev(hw), "\tflags_extr_imm = %d\n", + alu->flags_extr_imm); + dev_info(ice_hw_to_dev(hw), "\tflags_start_imm= %d\n", + alu->flags_start_imm); +} + +/** + * ice_imem_dump - dump an imem item info + * @hw: pointer to the hardware structure + * @item: imem item to dump + */ +void ice_imem_dump(struct ice_hw *hw, struct ice_imem_item *item) +{ + dev_info(ice_hw_to_dev(hw), "index = %d\n", item->idx); + _ice_imem_bst_bm_dump(hw, &item->b_m); + _ice_imem_bst_kb_dump(hw, &item->b_kb); + dev_info(ice_hw_to_dev(hw), "pg priority = %d\n", item->pg_pri); + _ice_imem_np_kb_dump(hw, &item->np_kb); + _ice_imem_pg_kb_dump(hw, &item->pg_kb); + _ice_imem_alu_dump(hw, &item->alu0, 0); + _ice_imem_alu_dump(hw, &item->alu1, 1); + _ice_imem_alu_dump(hw, &item->alu2, 2); +} + +/** The function parses a 4 bits Boost Main with below format: + * BIT 0: ALU 0 (bm->alu0) + * BIT 1: ALU 1 (bm->alu1) + * BIT 2: ALU 2 (bm->alu2) + * BIT 3: Parge Graph (bm->pg) + */ +static void _ice_imem_bm_init(struct ice_bst_main *bm, u8 data) +{ + bm->alu0 = !!(data & ICE_BM_ALU0); + bm->alu1 = !!(data & ICE_BM_ALU1); + bm->alu2 = !!(data & ICE_BM_ALU2); + bm->pg = !!(data & ICE_BM_PG); +} + +/** The function parses a 10 bits Boost Main Build with below format: + * BIT 0-7: Priority (bkb->prio) + * BIT 8: TSR Control (bkb->tsr_ctrl) + * BIT 9: Reserved + */ +static void _ice_imem_bkb_init(struct ice_bst_keybuilder *bkb, u16 data) +{ + bkb->prio = (u8)(data & ICE_BKB_PRIO_M); + bkb->tsr_ctrl = !!(data >> ICE_BKB_TSRC_S & ICE_BKB_TSRC_M); +} + +/** The function parses a 18 bits Next Protocol Key Build with below format: + * BIT 0-1: Opcode (kb->ops) + * BIT 2-9: Start / Reg 0 (kb->start_or_reg0) + * BIT 10-17: Length / Reg 1 (kb->len_or_reg1) + */ +static void _ice_imem_npkb_init(struct ice_np_keybuilder *kb, u32 data) +{ + kb->opc = (u8)(data & ICE_NPKB_OPC_M); + kb->start_reg0 = (u8)((data >> ICE_NPKB_SR0_S) & ICE_NPKB_SR0_M); + kb->len_reg1 = (u8)((data >> ICE_NPKB_LR1_S) & ICE_NPKB_LR1_M); +} + +/** The function parses a 35 bits Parse Graph Key Build with below format: + * BIT 0: Flag 0 Enable (kb->flag0_ena) + * BIT 1-6: Flag 0 Index (kb->flag0_idx) + * BIT 7: Flag 1 Enable (kb->flag1_ena) + * BIT 8-13: Flag 1 Index (kb->flag1_idx) + * BIT 14: Flag 2 Enable (kb->flag2_ena) + * BIT 15-20: Flag 2 Index (kb->flag2_idx) + * BIT 21: Flag 3 Enable (kb->flag3_ena) + * BIT 22-27: Flag 3 Index (kb->flag3_idx) + * BIT 28-34: ALU Register Index (kb->alu_reg_idx) + */ +static void _ice_imem_pgkb_init(struct ice_pg_keybuilder *kb, u64 data) +{ + kb->flag0_ena = !!(data & ICE_PGKB_F0E_M); + kb->flag0_idx = (u8)((data >> ICE_PGKB_F0I_S) & ICE_PGKB_F0I_M); + kb->flag1_ena = !!((data >> ICE_PGKB_F1E_S) & ICE_PGKB_F1E_M); + kb->flag1_idx = (u8)((data >> ICE_PGKB_F1I_S) & ICE_PGKB_F1I_M); + kb->flag2_ena = !!((data >> ICE_PGKB_F2E_S) & ICE_PGKB_F2E_M); + kb->flag2_idx = (u8)((data >> ICE_PGKB_F2I_S) & ICE_PGKB_F2I_M); + kb->flag3_ena = !!((data >> ICE_PGKB_F3E_S) & ICE_PGKB_F3E_M); + kb->flag3_idx = (u8)((data >> ICE_PGKB_F3I_S) & ICE_PGKB_F3I_M); + kb->alu_reg_idx = (u8)((data >> ICE_PGKB_ARI_S) & ICE_PGKB_ARI_M); +} + +/** The function parses a 96 bits ALU entry with below format: + * BIT 0-5: Opcode (alu->opc) + * BIT 6-13: Source Start (alu->src_start) + * BIT 14-18: Source Length (alu->src_len) + * BIT 19: Shift/Xlate Select (alu->shift_xlate_select) + * BIT 20-23: Shift/Xlate Key (alu->shift_xlate_key) + * BIT 24-30: Source Register ID (alu->src_reg_id) + * BIT 31-37: Dest. Register ID (alu->dst_reg_id) + * BIT 38: Inc0 (alu->inc0) + * BIT 39: Inc1 (alu->inc1) + * BIT 40:41 Protocol Offset Opcode (alu->proto_offset_opc) + * BIT 42:49 Protocol Offset (alu->proto_offset) + * BIT 50:57 Branch Address (alu->branch_addr) + * BIT 58:73 Immediate (alu->imm) + * BIT 74 Dedicated Flags Enable (alu->dedicate_flags_ena) + * BIT 75:80 Dest. Start (alu->dst_start) + * BIT 81:86 Dest. Length (alu->dst_len) + * BIT 87 Flags Extract Imm. (alu->flags_extr_imm) + * BIT 88:95 Flags Start/Immediate (alu->flags_start_imm) + */ +static void _ice_imem_alu_init(struct ice_alu *alu, u8 *data, u8 off) +{ + u64 d64; + u8 idd; + + d64 = *((u64 *)data) >> off; + + alu->opc = (enum ice_alu_opcode)(d64 & ICE_ALU_OPC_M); + alu->src_start = (u8)((d64 >> ICE_ALU_SS_S) & ICE_ALU_SS_M); + alu->src_len = (u8)((d64 >> ICE_ALU_SL_S) & ICE_ALU_SL_M); + alu->shift_xlate_sel = !!((d64 >> ICE_ALU_SXS_S) & ICE_ALU_SXS_M); + alu->shift_xlate_key = (u8)((d64 >> ICE_ALU_SXK_S) & ICE_ALU_SXK_M); + alu->src_reg_id = (u8)((d64 >> ICE_ALU_SRI_S) & ICE_ALU_SRI_M); + alu->dst_reg_id = (u8)((d64 >> ICE_ALU_DRI_S) & ICE_ALU_DRI_M); + alu->inc0 = !!((d64 >> ICE_ALU_INC0_S) & ICE_ALU_INC0_M); + alu->inc1 = !!((d64 >> ICE_ALU_INC1_S) & ICE_ALU_INC1_M); + alu->proto_offset_opc = (u8)((d64 >> ICE_ALU_POO_S) & ICE_ALU_POO_M); + alu->proto_offset = (u8)((d64 >> ICE_ALU_PO_S) & ICE_ALU_PO_M); + + idd = (ICE_ALU_BA_S + off) / BITS_PER_BYTE; + off = (ICE_ALU_BA_S + off) % BITS_PER_BYTE; + d64 = *((u64 *)(&data[idd])) >> off; + + alu->branch_addr = (u8)(d64 & ICE_ALU_BA_M); + off = ICE_ALU_IMM_S - ICE_ALU_BA_S; + alu->imm = (u16)((d64 >> off) & ICE_ALU_IMM_M); + off = ICE_ALU_DFE_S - ICE_ALU_BA_S; + alu->dedicate_flags_ena = !!((d64 >> off) & ICE_ALU_DFE_M); + off = ICE_ALU_DS_S - ICE_ALU_BA_S; + alu->dst_start = (u8)((d64 >> off) & ICE_ALU_DS_M); + off = ICE_ALU_DL_S - ICE_ALU_BA_S; + alu->dst_len = (u8)((d64 >> off) & ICE_ALU_DL_M); + off = ICE_ALU_FEI_S - ICE_ALU_BA_S; + alu->flags_extr_imm = !!((d64 >> off) & ICE_ALU_FEI_M); + off = ICE_ALU_FSI_S - ICE_ALU_BA_S; + alu->flags_start_imm = (u8)((d64 >> off) & ICE_ALU_FSI_M); +} + +/** The function parses a 384 bits IMEM entry with below format: + * BIT 0-3: Boost Main (ii->b_m) + * BIT 4-13: Boost Key Build (ii->b_kb) + * BIT 14-15: PG Priority (ii->pg) + * BIT 16-33: Next Proto Key Build (ii->np_kb) + * BIT 34-68: PG Key Build (ii->pg_kb) + * BIT 69-164: ALU0 (ii->alu0) + * BIT 165-260:ALU1 (ii->alu1) + * BIT 261-356:ALU2 (ii->alu2) + * BIT 357-383:Reserved + */ +static void _ice_imem_parse_item(struct ice_hw *hw, u16 idx, void *item, + void *data, int size) +{ + struct ice_imem_item *ii = item; + u8 *buf = (u8 *)data; + u8 idd, off; + + ii->idx = idx; + + _ice_imem_bm_init(&ii->b_m, *(u8 *)buf); + + idd = ICE_IMEM_BKB_S / BITS_PER_BYTE; + off = ICE_IMEM_BKB_S % BITS_PER_BYTE; + _ice_imem_bkb_init(&ii->b_kb, *((u16 *)(&buf[idd])) >> off); + + ii->pg_pri = (u8)((*(u16 *)buf >> ICE_IMEM_PGP_S) & ICE_IMEM_PGP_M); + + idd = ICE_IMEM_NPKB_S / BITS_PER_BYTE; + off = ICE_IMEM_NPKB_S % BITS_PER_BYTE; + _ice_imem_npkb_init(&ii->np_kb, *((u32 *)(&buf[idd])) >> off); + + idd = ICE_IMEM_PGKB_S / BITS_PER_BYTE; + off = ICE_IMEM_PGKB_S % BITS_PER_BYTE; + _ice_imem_pgkb_init(&ii->pg_kb, *((u64 *)(&buf[idd])) >> off); + + idd = ICE_IMEM_ALU0_S / BITS_PER_BYTE; + off = ICE_IMEM_ALU0_S % BITS_PER_BYTE; + _ice_imem_alu_init(&ii->alu0, &buf[idd], off); + + idd = ICE_IMEM_ALU1_S / BITS_PER_BYTE; + off = ICE_IMEM_ALU1_S % BITS_PER_BYTE; + _ice_imem_alu_init(&ii->alu1, &buf[idd], off); + + idd = ICE_IMEM_ALU2_S / BITS_PER_BYTE; + off = ICE_IMEM_ALU2_S % BITS_PER_BYTE; + _ice_imem_alu_init(&ii->alu2, &buf[idd], off); + + if (hw->debug_mask & ICE_DBG_PARSER) + ice_imem_dump(hw, ii); +} + +/** + * ice_imem_table_get - create an imem table + * @hw: pointer to the hardware structure + */ +struct ice_imem_item *ice_imem_table_get(struct ice_hw *hw) +{ + return (struct ice_imem_item *) + ice_parser_create_table(hw, ICE_SID_RXPARSER_IMEM, + sizeof(struct ice_imem_item), + ICE_IMEM_TABLE_SIZE, + ice_parser_sect_item_get, + _ice_imem_parse_item); +} diff --git a/drivers/net/ethernet/intel/ice/ice_imem.h b/drivers/net/ethernet/intel/ice/ice_imem.h new file mode 100644 index 000000000000..70b0555013a8 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_imem.h @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2023 Intel Corporation */ + +#ifndef _ICE_IMEM_H_ +#define _ICE_IMEM_H_ + +#define ICE_IMEM_TABLE_SIZE 192 + +#define ICE_BM_ALU0 BIT(0) +#define ICE_BM_ALU1 BIT(1) +#define ICE_BM_ALU2 BIT(2) +#define ICE_BM_PG BIT(3) + +struct ice_bst_main { + bool alu0; + bool alu1; + bool alu2; + bool pg; +}; + +#define ICE_BKB_PRIO_S 0 +#define ICE_BKB_PRIO_M BITMAP_MASK(8) +#define ICE_BKB_TSRC_S 8 +#define ICE_BKB_TSRC_M BITMAP_MASK(1) + +struct ice_bst_keybuilder { + u8 prio; + bool tsr_ctrl; +}; + +#define ICE_NPKB_HV_SIZE 8 + +#define ICE_NPKB_OPC_S 0 +#define ICE_NPKB_OPC_M BITMAP_MASK(2) +#define ICE_NPKB_SR0_S 2 +#define ICE_NPKB_SR0_M BITMAP_MASK(8) +#define ICE_NPKB_LR1_S 10 +#define ICE_NPKB_LR1_M BITMAP_MASK(8) + +struct ice_np_keybuilder { + u8 opc; + u8 start_reg0; + u8 len_reg1; +}; + +enum ice_np_keybuilder_opcode { + ICE_NPKB_OPC_EXTRACT = 0, + ICE_NPKB_OPC_BUILD = 1, + ICE_NPKB_OPC_BYPASS = 2, +}; + +#define ICE_PGKB_F0E_S 0 +#define ICE_PGKB_F0E_M BITMAP_MASK(1) +#define ICE_PGKB_F0I_S 1 +#define ICE_PGKB_F0I_M BITMAP_MASK(6) +#define ICE_PGKB_F1E_S 7 +#define ICE_PGKB_F1E_M BITMAP_MASK(1) +#define ICE_PGKB_F1I_S 8 +#define ICE_PGKB_F1I_M BITMAP_MASK(6) +#define ICE_PGKB_F2E_S 14 +#define ICE_PGKB_F2E_M BITMAP_MASK(1) +#define ICE_PGKB_F2I_S 15 +#define ICE_PGKB_F2I_M BITMAP_MASK(6) +#define ICE_PGKB_F3E_S 21 +#define ICE_PGKB_F3E_M BITMAP_MASK(1) +#define ICE_PGKB_F3I_S 22 +#define ICE_PGKB_F3I_M BITMAP_MASK(6) +#define ICE_PGKB_ARI_S 28 +#define ICE_PGKB_ARI_M BITMAP_MASK(7) + +struct ice_pg_keybuilder { + bool flag0_ena; + bool flag1_ena; + bool flag2_ena; + bool flag3_ena; + u8 flag0_idx; + u8 flag1_idx; + u8 flag2_idx; + u8 flag3_idx; + u8 alu_reg_idx; +}; + +enum ice_alu_idx { + ICE_ALU0_IDX = 0, + ICE_ALU1_IDX = 1, + ICE_ALU2_IDX = 2, +}; + +enum ice_alu_opcode { + ICE_ALU_PARK = 0, + ICE_ALU_MOV_ADD = 1, + ICE_ALU_ADD = 2, + ICE_ALU_MOV_AND = 4, + ICE_ALU_AND = 5, + ICE_ALU_AND_IMM = 6, + ICE_ALU_MOV_OR = 7, + ICE_ALU_OR = 8, + ICE_ALU_MOV_XOR = 9, + ICE_ALU_XOR = 10, + ICE_ALU_NOP = 11, + ICE_ALU_BR = 12, + ICE_ALU_BREQ = 13, + ICE_ALU_BRNEQ = 14, + ICE_ALU_BRGT = 15, + ICE_ALU_BRLT = 16, + ICE_ALU_BRGEQ = 17, + ICE_ALU_BRLEG = 18, + ICE_ALU_SETEQ = 19, + ICE_ALU_ANDEQ = 20, + ICE_ALU_OREQ = 21, + ICE_ALU_SETNEQ = 22, + ICE_ALU_ANDNEQ = 23, + ICE_ALU_ORNEQ = 24, + ICE_ALU_SETGT = 25, + ICE_ALU_ANDGT = 26, + ICE_ALU_ORGT = 27, + ICE_ALU_SETLT = 28, + ICE_ALU_ANDLT = 29, + ICE_ALU_ORLT = 30, + ICE_ALU_MOV_SUB = 31, + ICE_ALU_SUB = 32, + ICE_ALU_INVALID = 64, +}; + +enum ice_proto_off_opcode { + ICE_PO_OFF_REMAIN = 0, + ICE_PO_OFF_HDR_ADD = 1, + ICE_PO_OFF_HDR_SUB = 2, +}; + +#define ICE_ALU_REG_SIZE 4 + +#define ICE_ALU_OPC_S 0 +#define ICE_ALU_OPC_M BITMAP_MASK(6) +#define ICE_ALU_SS_S 6 +#define ICE_ALU_SS_M BITMAP_MASK(8) +#define ICE_ALU_SL_S 14 +#define ICE_ALU_SL_M BITMAP_MASK(5) +#define ICE_ALU_SXS_S 19 +#define ICE_ALU_SXS_M BITMAP_MASK(1) +#define ICE_ALU_SXK_S 20 +#define ICE_ALU_SXK_M BITMAP_MASK(4) +#define ICE_ALU_SRI_S 24 +#define ICE_ALU_SRI_M BITMAP_MASK(7) +#define ICE_ALU_DRI_S 31 +#define ICE_ALU_DRI_M BITMAP_MASK(7) +#define ICE_ALU_INC0_S 38 +#define ICE_ALU_INC0_M BITMAP_MASK(1) +#define ICE_ALU_INC1_S 39 +#define ICE_ALU_INC1_M BITMAP_MASK(1) +#define ICE_ALU_POO_S 40 +#define ICE_ALU_POO_M BITMAP_MASK(2) +#define ICE_ALU_PO_S 42 +#define ICE_ALU_PO_M BITMAP_MASK(8) +#define ICE_ALU_BA_S 50 +#define ICE_ALU_BA_M BITMAP_MASK(8) +#define ICE_ALU_IMM_S 58 +#define ICE_ALU_IMM_M BITMAP_MASK(16) +#define ICE_ALU_DFE_S 74 +#define ICE_ALU_DFE_M BITMAP_MASK(1) +#define ICE_ALU_DS_S 75 +#define ICE_ALU_DS_M BITMAP_MASK(6) +#define ICE_ALU_DL_S 81 +#define ICE_ALU_DL_M BITMAP_MASK(6) +#define ICE_ALU_FEI_S 87 +#define ICE_ALU_FEI_M BITMAP_MASK(1) +#define ICE_ALU_FSI_S 88 +#define ICE_ALU_FSI_M BITMAP_MASK(8) + +struct ice_alu { + enum ice_alu_opcode opc; + u8 src_start; + u8 src_len; + bool shift_xlate_sel; + u8 shift_xlate_key; + u8 src_reg_id; + u8 dst_reg_id; + bool inc0; + bool inc1; + u8 proto_offset_opc; + u8 proto_offset; + u8 branch_addr; + u16 imm; + bool dedicate_flags_ena; + u8 dst_start; + u8 dst_len; + bool flags_extr_imm; + u8 flags_start_imm; +}; + +#define ICE_IMEM_BM_S 0 +#define ICE_IMEM_BM_M BITMAP_MASK(4) +#define ICE_IMEM_BKB_S 4 +#define ICE_IMEM_BKB_M BITMAP_MASK(10) +#define ICE_IMEM_PGP_S 14 +#define ICE_IMEM_PGP_M BITMAP_MASK(2) +#define ICE_IMEM_NPKB_S 16 +#define ICE_IMEM_PGKB_S 34 +#define ICE_IMEM_ALU0_S 69 +#define ICE_IMEM_ALU1_S 165 +#define ICE_IMEM_ALU2_S 357 + +struct ice_imem_item { + u16 idx; + struct ice_bst_main b_m; + struct ice_bst_keybuilder b_kb; + u8 pg_pri; + struct ice_np_keybuilder np_kb; + struct ice_pg_keybuilder pg_kb; + struct ice_alu alu0; + struct ice_alu alu1; + struct ice_alu alu2; +}; + +void ice_imem_dump(struct ice_hw *hw, struct ice_imem_item *item); +struct ice_imem_item *ice_imem_table_get(struct ice_hw *hw); +#endif /* _ICE_IMEM_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c index 747dfad66db2..dd089c859616 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.c +++ b/drivers/net/ethernet/intel/ice/ice_parser.c @@ -2,6 +2,91 @@ /* Copyright (C) 2023 Intel Corporation */ #include "ice_common.h" +#include "ice_parser_util.h" + +/** + * ice_parser_sect_item_get - parse a item from a section + * @sect_type: section type + * @section: section object + * @index: index of the item to get + * @offset: dummy as prototype of ice_pkg_enum_entry's last parameter + */ +void *ice_parser_sect_item_get(u32 sect_type, void *section, + u32 index, u32 *offset) +{ + size_t data_off = ICE_SEC_DATA_OFFSET; + struct ice_pkg_sect_hdr *hdr; + size_t size; + + if (!section) + return NULL; + + switch (sect_type) { + case ICE_SID_RXPARSER_IMEM: + size = ICE_SID_RXPARSER_IMEM_ENTRY_SIZE; + break; + default: + return NULL; + } + + hdr = section; + if (index >= le16_to_cpu(hdr->count)) + return NULL; + + return (u8 *)section + data_off + index * size; +} + +/** + * ice_parser_create_table - create a item table from a section + * @hw: pointer to the hardware structure + * @sect_type: section type + * @item_size: item size in byte + * @length: number of items in the table to create + * @item_get: the function will be parsed to ice_pkg_enum_entry + * @parse_item: the function to parse the item + */ +void *ice_parser_create_table(struct ice_hw *hw, u32 sect_type, + u32 item_size, u32 length, + void *(*item_get)(u32 sect_type, void *section, + u32 index, u32 *offset), + void (*parse_item)(struct ice_hw *hw, u16 idx, + void *item, void *data, + int size)) +{ + struct ice_seg *seg = hw->seg; + struct ice_pkg_enum state; + u16 idx = U16_MAX; + void *table; + void *data; + + if (!seg) + return NULL; + + table = devm_kzalloc(ice_hw_to_dev(hw), item_size * length, + GFP_KERNEL); + if (!table) + return NULL; + + memset(&state, 0, sizeof(state)); + do { + data = ice_pkg_enum_entry(seg, &state, sect_type, NULL, + item_get); + seg = NULL; + if (data) { + struct ice_pkg_sect_hdr *hdr = + (struct ice_pkg_sect_hdr *)state.sect; + + idx = le16_to_cpu(hdr->offset) + state.entry_idx; + parse_item(hw, idx, + (void *)((uintptr_t)table + + ((uintptr_t)idx * + (uintptr_t)item_size)), + data, item_size); + } + } while (data); + + return table; +} /** * ice_parser_create - create a parser instance @@ -11,6 +96,7 @@ int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr) { struct ice_parser *p; + int status; p = devm_kzalloc(ice_hw_to_dev(hw), sizeof(struct ice_parser), GFP_KERNEL); @@ -19,8 +105,17 @@ int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr) p->hw = hw; + p->imem_table = ice_imem_table_get(hw); + if (!p->imem_table) { + status = -EINVAL; + goto err; + } + *psr = p; return 0; +err: + ice_parser_destroy(p); + return status; } /** @@ -29,5 +124,7 @@ int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr) */ void ice_parser_destroy(struct ice_parser *psr) { + devm_kfree(ice_hw_to_dev(psr->hw), psr->imem_table); + devm_kfree(ice_hw_to_dev(psr->hw), psr); } diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h index 85c470235e67..b63c27ec481d 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.h +++ b/drivers/net/ethernet/intel/ice/ice_parser.h @@ -4,8 +4,16 @@ #ifndef _ICE_PARSER_H_ #define _ICE_PARSER_H_ +#include "ice_imem.h" + +#define ICE_SEC_DATA_OFFSET 4 +#define ICE_SID_RXPARSER_IMEM_ENTRY_SIZE 48 + struct ice_parser { struct ice_hw *hw; /* pointer to the hardware structure */ + + /* load data from section ICE_SID_RX_PARSER_IMEM */ + struct ice_imem_item *imem_table; }; int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr); diff --git a/drivers/net/ethernet/intel/ice/ice_parser_util.h b/drivers/net/ethernet/intel/ice/ice_parser_util.h new file mode 100644 index 000000000000..32371458b581 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_parser_util.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2023 Intel Corporation */ + +#ifndef _ICE_PARSER_UTIL_H_ +#define _ICE_PARSER_UTIL_H_ + +#include "ice_imem.h" + +struct ice_pkg_sect_hdr { + __le16 count; + __le16 offset; +}; + +void *ice_parser_sect_item_get(u32 sect_type, void *section, + u32 index, u32 *offset); + +void *ice_parser_create_table(struct ice_hw *hw, u32 sect_type, + u32 item_size, u32 length, + void *(*handler)(u32 sect_type, void *section, + u32 index, u32 *offset), + void (*parse_item)(struct ice_hw *hw, u16 idx, + void *item, void *data, + int size)); +#endif /* _ICE_PARSER_UTIL_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h index a09556e57803..fa4336dd55f7 100644 --- a/drivers/net/ethernet/intel/ice/ice_type.h +++ b/drivers/net/ethernet/intel/ice/ice_type.h @@ -60,6 +60,7 @@ static inline u32 ice_round_to_num(u32 N, u32 R) ICE_DBG_AQ_DESC | \ ICE_DBG_AQ_DESC_BUF | \ ICE_DBG_AQ_CMD) +#define ICE_DBG_PARSER BIT_ULL(28) #define ICE_DBG_USER BIT_ULL(31) From patchwork Mon Aug 21 08:14:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359244 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA3981FBA for ; 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21 Aug 2023 01:14:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="685577431" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577431" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:14:53 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 03/15] ice: init metainit table for parser Date: Mon, 21 Aug 2023 16:14:26 +0800 Message-Id: <20230821081438.2937934-4-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Parse DDP section ICE_SID_RXPARSER_METADATA_INIT into an array of struct ice_metainit_item. Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/ice_metainit.c | 181 ++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_metainit.h | 104 ++++++++++ drivers/net/ethernet/intel/ice/ice_parser.c | 10 + drivers/net/ethernet/intel/ice/ice_parser.h | 4 + .../net/ethernet/intel/ice/ice_parser_util.h | 1 + 5 files changed, 300 insertions(+) create mode 100644 drivers/net/ethernet/intel/ice/ice_metainit.c create mode 100644 drivers/net/ethernet/intel/ice/ice_metainit.h diff --git a/drivers/net/ethernet/intel/ice/ice_metainit.c b/drivers/net/ethernet/intel/ice/ice_metainit.c new file mode 100644 index 000000000000..de7b6da548f6 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_metainit.c @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2023 Intel Corporation */ + +#include "ice_common.h" +#include "ice_parser_util.h" + +/** + * ice_metainit_dump - dump an metainit item info + * @hw: pointer to the hardware structure + * @item: metainit item to dump + */ +void ice_metainit_dump(struct ice_hw *hw, struct ice_metainit_item *item) +{ + dev_info(ice_hw_to_dev(hw), "index = %d\n", item->idx); + + dev_info(ice_hw_to_dev(hw), "tsr = %d\n", item->tsr); + dev_info(ice_hw_to_dev(hw), "ho = %d\n", item->ho); + dev_info(ice_hw_to_dev(hw), "pc = %d\n", item->pc); + dev_info(ice_hw_to_dev(hw), "pg_rn = %d\n", item->pg_rn); + dev_info(ice_hw_to_dev(hw), "cd = %d\n", item->cd); + + dev_info(ice_hw_to_dev(hw), "gpr_a_ctrl = %d\n", item->gpr_a_ctrl); + dev_info(ice_hw_to_dev(hw), "gpr_a_data_mdid = %d\n", + item->gpr_a_data_mdid); + dev_info(ice_hw_to_dev(hw), "gpr_a_data_start = %d\n", + item->gpr_a_data_start); + dev_info(ice_hw_to_dev(hw), "gpr_a_data_len = %d\n", + item->gpr_a_data_len); + dev_info(ice_hw_to_dev(hw), "gpr_a_id = %d\n", item->gpr_a_id); + + dev_info(ice_hw_to_dev(hw), "gpr_b_ctrl = %d\n", item->gpr_b_ctrl); + dev_info(ice_hw_to_dev(hw), "gpr_b_data_mdid = %d\n", + item->gpr_b_data_mdid); + dev_info(ice_hw_to_dev(hw), "gpr_b_data_start = %d\n", + item->gpr_b_data_start); + dev_info(ice_hw_to_dev(hw), "gpr_b_data_len = %d\n", + item->gpr_b_data_len); + dev_info(ice_hw_to_dev(hw), "gpr_b_id = %d\n", item->gpr_b_id); + + dev_info(ice_hw_to_dev(hw), "gpr_c_ctrl = %d\n", item->gpr_c_ctrl); + dev_info(ice_hw_to_dev(hw), "gpr_c_data_mdid = %d\n", + item->gpr_c_data_mdid); + dev_info(ice_hw_to_dev(hw), "gpr_c_data_start = %d\n", + item->gpr_c_data_start); + dev_info(ice_hw_to_dev(hw), "gpr_c_data_len = %d\n", + item->gpr_c_data_len); + dev_info(ice_hw_to_dev(hw), "gpr_c_id = %d\n", item->gpr_c_id); + + dev_info(ice_hw_to_dev(hw), "gpr_d_ctrl = %d\n", item->gpr_d_ctrl); + dev_info(ice_hw_to_dev(hw), "gpr_d_data_mdid = %d\n", + item->gpr_d_data_mdid); + dev_info(ice_hw_to_dev(hw), "gpr_d_data_start = %d\n", + item->gpr_d_data_start); + dev_info(ice_hw_to_dev(hw), "gpr_d_data_len = %d\n", + item->gpr_d_data_len); + dev_info(ice_hw_to_dev(hw), "gpr_d_id = %d\n", item->gpr_d_id); + + dev_info(ice_hw_to_dev(hw), "flags = 0x%llx\n", + (unsigned long long)(item->flags)); +} + +/** The function parses a 192 bits Metadata Init entry with below format: + * BIT 0-7: TCAM Search Key Register (mi->tsr) + * BIT 8-16: Header Offset (mi->ho) + * BIT 17-24: Program Counter (mi->pc) + * BIT 25-35: Parse Graph Root Node (mi->pg_rn) + * BIT 36-38: Control Domain (mi->cd) + * BIT 39: GPR_A Data Control (mi->gpr_a_ctrl) + * BIT 40-44: GPR_A MDID.ID (mi->gpr_a_data_mdid) + * BIT 45-48: GPR_A MDID.START (mi->gpr_a_data_start) + * BIT 49-53: GPR_A MDID.LEN (mi->gpr_a_data_len) + * BIT 54-55: reserved + * BIT 56-59: GPR_A ID (mi->gpr_a_id) + * BIT 60: GPR_B Data Control (mi->gpr_b_ctrl) + * BIT 61-65: GPR_B MDID.ID (mi->gpr_b_data_mdid) + * BIT 66-69: GPR_B MDID.START (mi->gpr_b_data_start) + * BIT 70-74: GPR_B MDID.LEN (mi->gpr_b_data_len) + * BIT 75-76: reserved + * BIT 77-80: GPR_B ID (mi->gpr_a_id) + * BIT 81: GPR_C Data Control (mi->gpr_c_ctrl) + * BIT 82-86: GPR_C MDID.ID (mi->gpr_c_data_mdid) + * BIT 87-90: GPR_C MDID.START (mi->gpr_c_data_start) + * BIT 91-95: GPR_C MDID.LEN (mi->gpr_c_data_len) + * BIT 96-97: reserved + * BIT 98-101: GPR_C ID (mi->gpr_c_id) + * BIT 102: GPR_D Data Control (mi->gpr_d_ctrl) + * BIT 103-107:GPR_D MDID.ID (mi->gpr_d_data_mdid) + * BIT 108-111:GPR_D MDID.START (mi->gpr_d_data_start) + * BIT 112-116:GPR_D MDID.LEN (mi->gpr_d_data_len) + * BIT 117-118:reserved + * BIT 119-122:GPR_D ID (mi->gpr_d_id) + * BIT 123-186:Flags (mi->flags) + * BIT 187-191:rserved + */ +static void _ice_metainit_parse_item(struct ice_hw *hw, u16 idx, void *item, + void *data, int size) +{ + struct ice_metainit_item *mi = item; + u8 *buf = (u8 *)data; + u8 idd, off; + u64 d64; + + mi->idx = idx; + + d64 = *(u64 *)buf; + + mi->tsr = (u8)(d64 & ICE_MI_TSR_M); + mi->ho = (u16)((d64 >> ICE_MI_HO_S) & ICE_MI_HO_M); + mi->pc = (u16)((d64 >> ICE_MI_PC_S) & ICE_MI_PC_M); + mi->pg_rn = (u16)((d64 >> ICE_MI_PGRN_S) & ICE_MI_PGRN_M); + mi->cd = (u16)((d64 >> ICE_MI_CD_S) & ICE_MI_CD_M); + + mi->gpr_a_ctrl = !!((d64 >> ICE_MI_GAC_S) & ICE_MI_GAC_M); + mi->gpr_a_data_mdid = (u8)((d64 >> ICE_MI_GADM_S) & ICE_MI_GADM_M); + mi->gpr_a_data_start = (u8)((d64 >> ICE_MI_GADS_S) & ICE_MI_GADS_M); + mi->gpr_a_data_len = (u8)((d64 >> ICE_MI_GADL_S) & ICE_MI_GADL_M); + mi->gpr_a_id = (u8)((d64 >> ICE_MI_GAI_S) & ICE_MI_GAI_M); + + idd = ICE_MI_GBC_S / BITS_PER_BYTE; + off = ICE_MI_GBC_S % BITS_PER_BYTE; + d64 = *((u64 *)&buf[idd]) >> off; + + mi->gpr_b_ctrl = !!(d64 & ICE_MI_GBC_M); + off = ICE_MI_GBDM_S - ICE_MI_GBC_S; + mi->gpr_b_data_mdid = (u8)((d64 >> off) & ICE_MI_GBDM_M); + off = ICE_MI_GBDS_S - ICE_MI_GBC_S; + mi->gpr_b_data_start = (u8)((d64 >> off) & ICE_MI_GBDS_M); + off = ICE_MI_GBDL_S - ICE_MI_GBC_S; + mi->gpr_b_data_len = (u8)((d64 >> off) & ICE_MI_GBDL_M); + off = ICE_MI_GBI_S - ICE_MI_GBC_S; + mi->gpr_b_id = (u8)((d64 >> off) & ICE_MI_GBI_M); + + off = ICE_MI_GCC_S - ICE_MI_GBC_S; + mi->gpr_c_ctrl = !!((d64 >> off) & ICE_MI_GCC_M); + off = ICE_MI_GCDM_S - ICE_MI_GBC_S; + mi->gpr_c_data_mdid = (u8)((d64 >> off) & ICE_MI_GCDM_M); + off = ICE_MI_GCDS_S - ICE_MI_GBC_S; + mi->gpr_c_data_start = (u8)((d64 >> off) & ICE_MI_GCDS_M); + off = ICE_MI_GCDL_S - ICE_MI_GBC_S; + mi->gpr_c_data_len = (u8)((d64 >> off) & ICE_MI_GCDL_M); + off = ICE_MI_GCI_S - ICE_MI_GBC_S; + mi->gpr_c_id = (u8)((d64 >> off) & ICE_MI_GCI_M); + + off = ICE_MI_GDC_S - ICE_MI_GBC_S; + mi->gpr_d_ctrl = !!((d64 >> off) & ICE_MI_GDC_M); + off = ICE_MI_GDDM_S - ICE_MI_GBC_S; + mi->gpr_d_data_mdid = (u8)((d64 >> off) & ICE_MI_GDDM_M); + off = ICE_MI_GDDS_S - ICE_MI_GBC_S; + mi->gpr_d_data_start = (u8)((d64 >> off) & ICE_MI_GDDS_M); + off = ICE_MI_GDDL_S - ICE_MI_GBC_S; + mi->gpr_d_data_len = (u8)((d64 >> off) & ICE_MI_GDDL_M); + + idd = ICE_MI_GDI_S / BITS_PER_BYTE; + off = ICE_MI_GDI_S % BITS_PER_BYTE; + d64 = *((u64 *)&buf[idd]) >> off; + + mi->gpr_d_id = (u8)(d64 & ICE_MI_GDI_M); + + idd = ICE_MI_FLAG_S / BITS_PER_BYTE; + off = ICE_MI_FLAG_S % BITS_PER_BYTE; + d64 = *((u64 *)&buf[idd]) >> off; + + mi->flags = d64; + + if (hw->debug_mask & ICE_DBG_PARSER) + ice_metainit_dump(hw, mi); +} + +/** + * ice_metainit_table_get - create a metainit table + * @hw: pointer to the hardware structure + */ +struct ice_metainit_item *ice_metainit_table_get(struct ice_hw *hw) +{ + return (struct ice_metainit_item *) + ice_parser_create_table(hw, ICE_SID_RXPARSER_METADATA_INIT, + sizeof(struct ice_metainit_item), + ICE_METAINIT_TABLE_SIZE, + ice_parser_sect_item_get, + _ice_metainit_parse_item); +} diff --git a/drivers/net/ethernet/intel/ice/ice_metainit.h b/drivers/net/ethernet/intel/ice/ice_metainit.h new file mode 100644 index 000000000000..9decf87bb631 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_metainit.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2023 Intel Corporation */ + +#ifndef _ICE_METAINIT_H_ +#define _ICE_METAINIT_H_ + +#define ICE_METAINIT_TABLE_SIZE 16 + +#define ICE_MI_TSR_S 0 +#define ICE_MI_TSR_M BITMAP_MASK(8) +#define ICE_MI_HO_S 8 +#define ICE_MI_HO_M BITMAP_MASK(9) +#define ICE_MI_PC_S 17 +#define ICE_MI_PC_M BITMAP_MASK(8) +#define ICE_MI_PGRN_S 25 +#define ICE_MI_PGRN_M BITMAP_MASK(11) +#define ICE_MI_CD_S 36 +#define ICE_MI_CD_M BITMAP_MASK(3) + +#define ICE_MI_GAC_S 39 +#define ICE_MI_GAC_M BITMAP_MASK(1) +#define ICE_MI_GADM_S 40 +#define ICE_MI_GADM_M BITMAP_MASK(5) +#define ICE_MI_GADS_S 45 +#define ICE_MI_GADS_M BITMAP_MASK(4) +#define ICE_MI_GADL_S 49 +#define ICE_MI_GADL_M BITMAP_MASK(5) +#define ICE_MI_GAI_S 56 +#define ICE_MI_GAI_M BITMAP_MASK(4) + +#define ICE_MI_GBC_S 60 +#define ICE_MI_GBC_M BITMAP_MASK(1) +#define ICE_MI_GBDM_S 61 +#define ICE_MI_GBDM_M BITMAP_MASK(5) +#define ICE_MI_GBDS_S 66 +#define ICE_MI_GBDS_M BITMAP_MASK(4) +#define ICE_MI_GBDL_S 70 +#define ICE_MI_GBDL_M BITMAP_MASK(5) +#define ICE_MI_GBI_S 77 +#define ICE_MI_GBI_M BITMAP_MASK(4) + +#define ICE_MI_GCC_S 81 +#define ICE_MI_GCC_M BITMAP_MASK(1) +#define ICE_MI_GCDM_S 82 +#define ICE_MI_GCDM_M BITMAP_MASK(5) +#define ICE_MI_GCDS_S 87 +#define ICE_MI_GCDS_M BITMAP_MASK(4) +#define ICE_MI_GCDL_S 91 +#define ICE_MI_GCDL_M BITMAP_MASK(5) +#define ICE_MI_GCI_S 98 +#define ICE_MI_GCI_M BITMAP_MASK(4) + +#define ICE_MI_GDC_S 102 +#define ICE_MI_GDC_M BITMAP_MASK(1) +#define ICE_MI_GDDM_S 103 +#define ICE_MI_GDDM_M BITMAP_MASK(5) +#define ICE_MI_GDDS_S 108 +#define ICE_MI_GDDS_M BITMAP_MASK(4) +#define ICE_MI_GDDL_S 112 +#define ICE_MI_GDDL_M BITMAP_MASK(5) +#define ICE_MI_GDI_S 119 +#define ICE_MI_GDI_M BITMAP_MASK(4) + +#define ICE_MI_FLAG_S 123 + +struct ice_metainit_item { + u16 idx; + + u8 tsr; + u16 ho; + u16 pc; + u16 pg_rn; + u8 cd; + + bool gpr_a_ctrl; + u8 gpr_a_data_mdid; + u8 gpr_a_data_start; + u8 gpr_a_data_len; + u8 gpr_a_id; + + bool gpr_b_ctrl; + u8 gpr_b_data_mdid; + u8 gpr_b_data_start; + u8 gpr_b_data_len; + u8 gpr_b_id; + + bool gpr_c_ctrl; + u8 gpr_c_data_mdid; + u8 gpr_c_data_start; + u8 gpr_c_data_len; + u8 gpr_c_id; + + bool gpr_d_ctrl; + u8 gpr_d_data_mdid; + u8 gpr_d_data_start; + u8 gpr_d_data_len; + u8 gpr_d_id; + + u64 flags; +}; + +void ice_metainit_dump(struct ice_hw *hw, struct ice_metainit_item *item); +struct ice_metainit_item *ice_metainit_table_get(struct ice_hw *hw); +#endif /*_ICE_METAINIT_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c index dd089c859616..e2e49fcf69c1 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.c +++ b/drivers/net/ethernet/intel/ice/ice_parser.c @@ -25,6 +25,9 @@ void *ice_parser_sect_item_get(u32 sect_type, void *section, case ICE_SID_RXPARSER_IMEM: size = ICE_SID_RXPARSER_IMEM_ENTRY_SIZE; break; + case ICE_SID_RXPARSER_METADATA_INIT: + size = ICE_SID_RXPARSER_METADATA_INIT_ENTRY_SIZE; + break; default: return NULL; } @@ -111,6 +114,12 @@ int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr) goto err; } + p->mi_table = ice_metainit_table_get(hw); + if (!p->mi_table) { + status = -EINVAL; + goto err; + } + *psr = p; return 0; err: @@ -125,6 +134,7 @@ int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr) void ice_parser_destroy(struct ice_parser *psr) { devm_kfree(ice_hw_to_dev(psr->hw), psr->imem_table); + devm_kfree(ice_hw_to_dev(psr->hw), psr->mi_table); devm_kfree(ice_hw_to_dev(psr->hw), psr); } diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h index b63c27ec481d..b52abad747b2 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.h +++ b/drivers/net/ethernet/intel/ice/ice_parser.h @@ -4,16 +4,20 @@ #ifndef _ICE_PARSER_H_ #define _ICE_PARSER_H_ +#include "ice_metainit.h" #include "ice_imem.h" #define ICE_SEC_DATA_OFFSET 4 #define ICE_SID_RXPARSER_IMEM_ENTRY_SIZE 48 +#define ICE_SID_RXPARSER_METADATA_INIT_ENTRY_SIZE 24 struct ice_parser { struct ice_hw *hw; /* pointer to the hardware structure */ /* load data from section ICE_SID_RX_PARSER_IMEM */ struct ice_imem_item *imem_table; + /* load data from section ICE_SID_RXPARSER_METADATA_INIT */ + struct ice_metainit_item *mi_table; }; int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr); diff --git a/drivers/net/ethernet/intel/ice/ice_parser_util.h b/drivers/net/ethernet/intel/ice/ice_parser_util.h index 32371458b581..42a91bd51a51 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser_util.h +++ b/drivers/net/ethernet/intel/ice/ice_parser_util.h @@ -5,6 +5,7 @@ #define _ICE_PARSER_UTIL_H_ #include "ice_imem.h" +#include "ice_metainit.h" struct ice_pkg_sect_hdr { __le16 count; From patchwork Mon Aug 21 08:14:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359245 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7750A46A7 for ; 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21 Aug 2023 01:15:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="685577448" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577448" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:14:56 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 04/15] ice: init parse graph cam tables for parser Date: Mon, 21 Aug 2023 16:14:27 +0800 Message-Id: <20230821081438.2937934-5-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Parse DDP section ICE_SID_RXPARSER_CAM or ICE_SID_RXPARSER_PG_SPILL into an array of struct ice_pg_cam_item. Parse DDP section ICE_SID_RXPARSER_NOMATCH_CAM or ICE_SID_RXPARSER_NOMATCH_SPILL into an array of struct ice_pg_nm_cam_item. Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/ice_parser.c | 40 +++ drivers/net/ethernet/intel/ice/ice_parser.h | 13 + drivers/net/ethernet/intel/ice/ice_pg_cam.c | 321 ++++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_pg_cam.h | 136 +++++++++ 4 files changed, 510 insertions(+) create mode 100644 drivers/net/ethernet/intel/ice/ice_pg_cam.c create mode 100644 drivers/net/ethernet/intel/ice/ice_pg_cam.h diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c index e2e49fcf69c1..b654135419fb 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.c +++ b/drivers/net/ethernet/intel/ice/ice_parser.c @@ -28,6 +28,18 @@ void *ice_parser_sect_item_get(u32 sect_type, void *section, case ICE_SID_RXPARSER_METADATA_INIT: size = ICE_SID_RXPARSER_METADATA_INIT_ENTRY_SIZE; break; + case ICE_SID_RXPARSER_CAM: + size = ICE_SID_RXPARSER_CAM_ENTRY_SIZE; + break; + case ICE_SID_RXPARSER_PG_SPILL: + size = ICE_SID_RXPARSER_PG_SPILL_ENTRY_SIZE; + break; + case ICE_SID_RXPARSER_NOMATCH_CAM: + size = ICE_SID_RXPARSER_NOMATCH_CAM_ENTRY_SIZE; + break; + case ICE_SID_RXPARSER_NOMATCH_SPILL: + size = ICE_SID_RXPARSER_NOMATCH_SPILL_ENTRY_SIZE; + break; default: return NULL; } @@ -120,6 +132,30 @@ int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr) goto err; } + p->pg_cam_table = ice_pg_cam_table_get(hw); + if (!p->pg_cam_table) { + status = -EINVAL; + goto err; + } + + p->pg_sp_cam_table = ice_pg_sp_cam_table_get(hw); + if (!p->pg_sp_cam_table) { + status = -EINVAL; + goto err; + } + + p->pg_nm_cam_table = ice_pg_nm_cam_table_get(hw); + if (!p->pg_nm_cam_table) { + status = -EINVAL; + goto err; + } + + p->pg_nm_sp_cam_table = ice_pg_nm_sp_cam_table_get(hw); + if (!p->pg_nm_sp_cam_table) { + status = -EINVAL; + goto err; + } + *psr = p; return 0; err: @@ -135,6 +171,10 @@ void ice_parser_destroy(struct ice_parser *psr) { devm_kfree(ice_hw_to_dev(psr->hw), psr->imem_table); devm_kfree(ice_hw_to_dev(psr->hw), psr->mi_table); + devm_kfree(ice_hw_to_dev(psr->hw), psr->pg_cam_table); + devm_kfree(ice_hw_to_dev(psr->hw), psr->pg_sp_cam_table); + devm_kfree(ice_hw_to_dev(psr->hw), psr->pg_nm_cam_table); + devm_kfree(ice_hw_to_dev(psr->hw), psr->pg_nm_sp_cam_table); devm_kfree(ice_hw_to_dev(psr->hw), psr); } diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h index b52abad747b2..c709c56bf2e6 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.h +++ b/drivers/net/ethernet/intel/ice/ice_parser.h @@ -6,10 +6,15 @@ #include "ice_metainit.h" #include "ice_imem.h" +#include "ice_pg_cam.h" #define ICE_SEC_DATA_OFFSET 4 #define ICE_SID_RXPARSER_IMEM_ENTRY_SIZE 48 #define ICE_SID_RXPARSER_METADATA_INIT_ENTRY_SIZE 24 +#define ICE_SID_RXPARSER_CAM_ENTRY_SIZE 16 +#define ICE_SID_RXPARSER_PG_SPILL_ENTRY_SIZE 17 +#define ICE_SID_RXPARSER_NOMATCH_CAM_ENTRY_SIZE 12 +#define ICE_SID_RXPARSER_NOMATCH_SPILL_ENTRY_SIZE 13 struct ice_parser { struct ice_hw *hw; /* pointer to the hardware structure */ @@ -18,6 +23,14 @@ struct ice_parser { struct ice_imem_item *imem_table; /* load data from section ICE_SID_RXPARSER_METADATA_INIT */ struct ice_metainit_item *mi_table; + /* load data from section ICE_SID_RXPARSER_CAM */ + struct ice_pg_cam_item *pg_cam_table; + /* load data from section ICE_SID_RXPARSER_PG_SPILL */ + struct ice_pg_cam_item *pg_sp_cam_table; + /* load data from section ICE_SID_RXPARSER_NOMATCH_CAM */ + struct ice_pg_nm_cam_item *pg_nm_cam_table; + /* load data from section ICE_SID_RXPARSER_NOMATCH_SPILL */ + struct ice_pg_nm_cam_item *pg_nm_sp_cam_table; }; int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr); diff --git a/drivers/net/ethernet/intel/ice/ice_pg_cam.c b/drivers/net/ethernet/intel/ice/ice_pg_cam.c new file mode 100644 index 000000000000..82a8c916d5ce --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_pg_cam.c @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2023 Intel Corporation */ + +#include "ice_common.h" +#include "ice_parser_util.h" + +static void _ice_pg_cam_key_dump(struct ice_hw *hw, struct ice_pg_cam_key *key) +{ + dev_info(ice_hw_to_dev(hw), "key:\n"); + dev_info(ice_hw_to_dev(hw), "\tvalid = %d\n", key->valid); + dev_info(ice_hw_to_dev(hw), "\tnode_id = %d\n", key->node_id); + dev_info(ice_hw_to_dev(hw), "\tflag0 = %d\n", key->flag0); + dev_info(ice_hw_to_dev(hw), "\tflag1 = %d\n", key->flag1); + dev_info(ice_hw_to_dev(hw), "\tflag2 = %d\n", key->flag2); + dev_info(ice_hw_to_dev(hw), "\tflag3 = %d\n", key->flag3); + dev_info(ice_hw_to_dev(hw), "\tboost_idx = %d\n", key->boost_idx); + dev_info(ice_hw_to_dev(hw), "\talu_reg = 0x%04x\n", key->alu_reg); + dev_info(ice_hw_to_dev(hw), "\tnext_proto = 0x%08x\n", + key->next_proto); +} + +static void _ice_pg_nm_cam_key_dump(struct ice_hw *hw, + struct ice_pg_nm_cam_key *key) +{ + dev_info(ice_hw_to_dev(hw), "key:\n"); + dev_info(ice_hw_to_dev(hw), "\tvalid = %d\n", key->valid); + dev_info(ice_hw_to_dev(hw), "\tnode_id = %d\n", key->node_id); + dev_info(ice_hw_to_dev(hw), "\tflag0 = %d\n", key->flag0); + dev_info(ice_hw_to_dev(hw), "\tflag1 = %d\n", key->flag1); + dev_info(ice_hw_to_dev(hw), "\tflag2 = %d\n", key->flag2); + dev_info(ice_hw_to_dev(hw), "\tflag3 = %d\n", key->flag3); + dev_info(ice_hw_to_dev(hw), "\tboost_idx = %d\n", key->boost_idx); + dev_info(ice_hw_to_dev(hw), "\talu_reg = 0x%04x\n", key->alu_reg); +} + +static void _ice_pg_cam_action_dump(struct ice_hw *hw, + struct ice_pg_cam_action *action) +{ + dev_info(ice_hw_to_dev(hw), "action:\n"); + dev_info(ice_hw_to_dev(hw), "\tnext_node = %d\n", action->next_node); + dev_info(ice_hw_to_dev(hw), "\tnext_pc = %d\n", action->next_pc); + dev_info(ice_hw_to_dev(hw), "\tis_pg = %d\n", action->is_pg); + dev_info(ice_hw_to_dev(hw), "\tproto_id = %d\n", action->proto_id); + dev_info(ice_hw_to_dev(hw), "\tis_mg = %d\n", action->is_mg); + dev_info(ice_hw_to_dev(hw), "\tmarker_id = %d\n", action->marker_id); + dev_info(ice_hw_to_dev(hw), "\tis_last_round = %d\n", + action->is_last_round); + dev_info(ice_hw_to_dev(hw), "\tho_polarity = %d\n", + action->ho_polarity); + dev_info(ice_hw_to_dev(hw), "\tho_inc = %d\n", action->ho_inc); +} + +/** + * ice_pg_cam_dump - dump an parse graph cam info + * @hw: pointer to the hardware structure + * @item: parse graph cam to dump + */ +void ice_pg_cam_dump(struct ice_hw *hw, struct ice_pg_cam_item *item) +{ + dev_info(ice_hw_to_dev(hw), "index = %d\n", item->idx); + _ice_pg_cam_key_dump(hw, &item->key); + _ice_pg_cam_action_dump(hw, &item->action); +} + +/** + * ice_pg_nm_cam_dump - dump an parse graph no match cam info + * @hw: pointer to the hardware structure + * @item: parse graph no match cam to dump + */ +void ice_pg_nm_cam_dump(struct ice_hw *hw, struct ice_pg_nm_cam_item *item) +{ + dev_info(ice_hw_to_dev(hw), "index = %d\n", item->idx); + _ice_pg_nm_cam_key_dump(hw, &item->key); + _ice_pg_cam_action_dump(hw, &item->action); +} + +/** The function parses a 55 bits Parse Graph CAM Action with below format: + * BIT 0-10: Next Node ID (action->next_node) + * BIT 11-18: Next PC (action->next_pc) + * BIT 19: Is Protocol Group (action->is_pg) + * BIT 20-22: reserved + * BIT 23-30: Protocol ID (action->proto_id) + * BIT 31: Is Marker Group (action->is_mg) + * BIT 32-39: Marker ID (action->marker_id) + * BIT 40: Is Last Round (action->is_last_round) + * BIT 41: Header Offset Polarity (action->ho_poloarity) + * BIT 42-50: Header Offset Inc (action->ho_inc) + * BIT 51-54: reserved + */ +static void _ice_pg_cam_action_init(struct ice_pg_cam_action *action, u64 data) +{ + action->next_node = (u16)(data & ICE_PGCA_NN_M); + action->next_pc = (u8)((data >> ICE_PGCA_NP_S) & ICE_PGCA_NP_M); + action->is_pg = !!((data >> ICE_PGCA_IPG_S) & ICE_PGCA_IPG_M); + action->proto_id = ((data >> ICE_PGCA_PID_S) & ICE_PGCA_PID_M); + action->is_mg = !!((data >> ICE_PGCA_IMG_S) & ICE_PGCA_IMG_M); + action->marker_id = ((data >> ICE_PGCA_MID_S) & ICE_PGCA_MID_M); + action->is_last_round = !!((data >> ICE_PGCA_ILR_S) & ICE_PGCA_ILR_M); + action->ho_polarity = !!((data >> ICE_PGCA_HOP_S) & ICE_PGCA_HOP_M); + action->ho_inc = ((data >> ICE_PGCA_HOI_S) & ICE_PGCA_HOI_M); +} + +/** The function parses a 41 bits Parse Graph NoMatch CAM Key with below format: + * BIT 0: Valid (key->valid) + * BIT 1-11: Node ID (key->node_id) + * BIT 12: Flag 0 (key->flag0) + * BIT 13: Flag 1 (key->flag1) + * BIT 14: Flag 2 (key->flag2) + * BIT 15: Flag 3 (key->flag3) + * BIT 16: Boost Hit (key->boost_idx to 0 if it is 0) + * BIT 17-24: Boost Index (key->boost_idx only if Boost Hit is not 0) + * BIT 25-40: ALU Reg (key->alu_reg) + */ +static void _ice_pg_nm_cam_key_init(struct ice_pg_nm_cam_key *key, u64 data) +{ + key->valid = !!(data & ICE_PGNCK_VLD_M); + key->node_id = (u16)((data >> ICE_PGNCK_NID_S) & ICE_PGNCK_NID_M); + key->flag0 = !!((data >> ICE_PGNCK_F0_S) & ICE_PGNCK_F0_M); + key->flag1 = !!((data >> ICE_PGNCK_F1_S) & ICE_PGNCK_F1_M); + key->flag2 = !!((data >> ICE_PGNCK_F2_S) & ICE_PGNCK_F2_M); + key->flag3 = !!((data >> ICE_PGNCK_F3_S) & ICE_PGNCK_F3_M); + if ((data >> ICE_PGNCK_BH_S) & ICE_PGNCK_BH_M) + key->boost_idx = + (u8)((data >> ICE_PGNCK_BI_S) & ICE_PGNCK_BI_M); + else + key->boost_idx = 0; + key->alu_reg = (u16)((data >> ICE_PGNCK_AR_S) & ICE_PGNCK_AR_M); +} + +/** The function parses a 73 bits Parse Graph CAM Key with below format: + * BIT 0: Valid (key->valid) + * BIT 1-11: Node ID (key->node_id) + * BIT 12: Flag 0 (key->flag0) + * BIT 13: Flag 1 (key->flag1) + * BIT 14: Flag 2 (key->flag2) + * BIT 15: Flag 3 (key->flag3) + * BIT 16: Boost Hit (key->boost_idx to 0 if it is 0) + * BIT 17-24: Boost Index (key->boost_idx only if Boost Hit is not 0) + * BIT 25-40: ALU Reg (key->alu_reg) + * BIT 41-72: Next Proto Key (key->next_proto) + */ +static void _ice_pg_cam_key_init(struct ice_pg_cam_key *key, u8 *data) +{ + u64 d64 = *(u64 *)data; + u8 idd, off; + + key->valid = !!(d64 & ICE_PGCK_VLD_M); + key->node_id = (u16)((d64 >> ICE_PGCK_NID_S) & ICE_PGCK_NID_M); + key->flag0 = !!((d64 >> ICE_PGCK_F0_S) & ICE_PGCK_F0_M); + key->flag1 = !!((d64 >> ICE_PGCK_F1_S) & ICE_PGCK_F1_M); + key->flag2 = !!((d64 >> ICE_PGCK_F2_S) & ICE_PGCK_F2_M); + key->flag3 = !!((d64 >> ICE_PGCK_F3_S) & ICE_PGCK_F3_M); + if ((d64 >> ICE_PGCK_BH_S) & ICE_PGCK_BH_M) + key->boost_idx = (u8)((d64 >> ICE_PGCK_BI_S) & ICE_PGCK_BI_M); + else + key->boost_idx = 0; + key->alu_reg = (u16)((d64 >> ICE_PGCK_AR_S) & ICE_PGCK_AR_M); + + idd = ICE_PGCK_NPK_S / BITS_PER_BYTE; + off = ICE_PGCK_NPK_S % BITS_PER_BYTE; + d64 = *((u64 *)&data[idd]) >> off; + + key->next_proto = (u32)(d64 & ICE_PGCK_NPK_M); +} + +/** The function parses a 128 bits Parse Graph CAM Entry with below format: + * BIT 0-72: Key (ci->key) + * BIT 73-127: Action (ci->action) + */ +static void _ice_pg_cam_parse_item(struct ice_hw *hw, u16 idx, void *item, + void *data, int size) +{ + struct ice_pg_cam_item *ci = item; + u8 *buf = data; + u64 d64; + u8 off; + + ci->idx = idx; + + _ice_pg_cam_key_init(&ci->key, buf); + + off = ICE_PG_CAM_ACT_OFF % BITS_PER_BYTE; + d64 = *((u64 *)&buf[ICE_PG_CAM_ACT_OFF / BITS_PER_BYTE]) >> off; + _ice_pg_cam_action_init(&ci->action, d64); + + if (hw->debug_mask & ICE_DBG_PARSER) + ice_pg_cam_dump(hw, ci); +} + +/** The function parses a 136 bits Parse Graph Spill CAM Entry with below + * format: + * BIT 0-55: Action (ci->key) + * BIT 56-135: Key (ci->action) + */ +static void _ice_pg_sp_cam_parse_item(struct ice_hw *hw, u16 idx, void *item, + void *data, int size) +{ + struct ice_pg_cam_item *ci = item; + u8 *buf = data; + u64 d64; + u8 idd; + + ci->idx = idx; + + d64 = *(u64 *)buf; + _ice_pg_cam_action_init(&ci->action, d64); + + idd = ICE_PG_SP_CAM_KEY_OFF / BITS_PER_BYTE; + _ice_pg_cam_key_init(&ci->key, &buf[idd]); + + if (hw->debug_mask & ICE_DBG_PARSER) + ice_pg_cam_dump(hw, ci); +} + +/** The function parses a 96 bits Parse Graph NoMatch CAM Entry with below + * format: + * BIT 0-40: Key (ci->key) + * BIT 41-95: Action (ci->action) + */ +static void _ice_pg_nm_cam_parse_item(struct ice_hw *hw, u16 idx, void *item, + void *data, int size) +{ + struct ice_pg_nm_cam_item *ci = item; + u8 *buf = data; + u64 d64; + u8 off; + + ci->idx = idx; + + d64 = *(u64 *)buf; + _ice_pg_nm_cam_key_init(&ci->key, d64); + + off = ICE_PG_NM_CAM_ACT_OFF % BITS_PER_BYTE; + d64 = *((u64 *)&buf[ICE_PG_NM_CAM_ACT_OFF / BITS_PER_BYTE]) >> off; + _ice_pg_cam_action_init(&ci->action, d64); + + if (hw->debug_mask & ICE_DBG_PARSER) + ice_pg_nm_cam_dump(hw, ci); +} + +/** The function parses a 104 bits Parse Graph NoMatch Spill CAM Entry with + * below format: + * BIT 0-55: Key (ci->key) + * BIT 56-103: Action (ci->action) + */ +static void _ice_pg_nm_sp_cam_parse_item(struct ice_hw *hw, u16 idx, + void *item, void *data, int size) +{ + struct ice_pg_nm_cam_item *ci = item; + u8 *buf = data; + u64 d64; + u8 off; + + ci->idx = idx; + + d64 = *(u64 *)buf; + _ice_pg_cam_action_init(&ci->action, d64); + + off = ICE_PG_NM_SP_CAM_ACT_OFF % BITS_PER_BYTE; + d64 = *((u64 *)&buf[ICE_PG_NM_SP_CAM_ACT_OFF / BITS_PER_BYTE]) >> off; + _ice_pg_nm_cam_key_init(&ci->key, d64); + + if (hw->debug_mask & ICE_DBG_PARSER) + ice_pg_nm_cam_dump(hw, ci); +} + +/** + * ice_pg_cam_table_get - create a parse graph cam table + * @hw: pointer to the hardware structure + */ +struct ice_pg_cam_item *ice_pg_cam_table_get(struct ice_hw *hw) +{ + return (struct ice_pg_cam_item *) + ice_parser_create_table(hw, ICE_SID_RXPARSER_CAM, + sizeof(struct ice_pg_cam_item), + ICE_PG_CAM_TABLE_SIZE, + ice_parser_sect_item_get, + _ice_pg_cam_parse_item); +} + +/** + * ice_pg_sp_cam_table_get - create a parse graph spill cam table + * @hw: pointer to the hardware structure + */ +struct ice_pg_cam_item *ice_pg_sp_cam_table_get(struct ice_hw *hw) +{ + return (struct ice_pg_cam_item *) + ice_parser_create_table(hw, ICE_SID_RXPARSER_PG_SPILL, + sizeof(struct ice_pg_cam_item), + ICE_PG_SP_CAM_TABLE_SIZE, + ice_parser_sect_item_get, + _ice_pg_sp_cam_parse_item); +} + +/** + * ice_pg_nm_cam_table_get - create a parse graph no match cam table + * @hw: pointer to the hardware structure + */ +struct ice_pg_nm_cam_item *ice_pg_nm_cam_table_get(struct ice_hw *hw) +{ + return (struct ice_pg_nm_cam_item *) + ice_parser_create_table(hw, ICE_SID_RXPARSER_NOMATCH_CAM, + sizeof(struct ice_pg_nm_cam_item), + ICE_PG_NM_CAM_TABLE_SIZE, + ice_parser_sect_item_get, + _ice_pg_nm_cam_parse_item); +} + +/** + * ice_pg_nm_sp_cam_table_get - create a parse graph no match spill cam table + * @hw: pointer to the hardware structure + */ +struct ice_pg_nm_cam_item *ice_pg_nm_sp_cam_table_get(struct ice_hw *hw) +{ + return (struct ice_pg_nm_cam_item *) + ice_parser_create_table(hw, ICE_SID_RXPARSER_NOMATCH_SPILL, + sizeof(struct ice_pg_nm_cam_item), + ICE_PG_NM_SP_CAM_TABLE_SIZE, + ice_parser_sect_item_get, + _ice_pg_nm_sp_cam_parse_item); +} diff --git a/drivers/net/ethernet/intel/ice/ice_pg_cam.h b/drivers/net/ethernet/intel/ice/ice_pg_cam.h new file mode 100644 index 000000000000..0d5c84d380d3 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_pg_cam.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2023 Intel Corporation */ + +#ifndef _ICE_PG_CAM_H_ +#define _ICE_PG_CAM_H_ + +#define ICE_PG_CAM_TABLE_SIZE 2048 +#define ICE_PG_SP_CAM_TABLE_SIZE 128 +#define ICE_PG_NM_CAM_TABLE_SIZE 1024 +#define ICE_PG_NM_SP_CAM_TABLE_SIZE 64 + +#define ICE_PGCK_VLD_S 0 +#define ICE_PGCK_VLD_M BITMAP_MASK(1) +#define ICE_PGCK_NID_S 1 +#define ICE_PGCK_NID_M BITMAP_MASK(11) +#define ICE_PGCK_F0_S 12 +#define ICE_PGCK_F0_M BITMAP_MASK(1) +#define ICE_PGCK_F1_S 13 +#define ICE_PGCK_F1_M BITMAP_MASK(1) +#define ICE_PGCK_F2_S 14 +#define ICE_PGCK_F2_M BITMAP_MASK(1) +#define ICE_PGCK_F3_S 15 +#define ICE_PGCK_F3_M BITMAP_MASK(1) +#define ICE_PGCK_BH_S 16 +#define ICE_PGCK_BH_M BITMAP_MASK(1) +#define ICE_PGCK_BI_S 17 +#define ICE_PGCK_BI_M BITMAP_MASK(8) +#define ICE_PGCK_AR_S 25 +#define ICE_PGCK_AR_M BITMAP_MASK(16) +#define ICE_PGCK_NPK_S 41 +#define ICE_PGCK_NPK_M BITMAP_MASK(32) + +struct ice_pg_cam_key { + bool valid; + u16 node_id; + bool flag0; + bool flag1; + bool flag2; + bool flag3; + u8 boost_idx; + u16 alu_reg; + u32 next_proto; +}; + +#define ICE_PGNCK_VLD_S 0 +#define ICE_PGNCK_VLD_M BITMAP_MASK(1) +#define ICE_PGNCK_NID_S 1 +#define ICE_PGNCK_NID_M BITMAP_MASK(11) +#define ICE_PGNCK_F0_S 12 +#define ICE_PGNCK_F0_M BITMAP_MASK(1) +#define ICE_PGNCK_F1_S 13 +#define ICE_PGNCK_F1_M BITMAP_MASK(1) +#define ICE_PGNCK_F2_S 14 +#define ICE_PGNCK_F2_M BITMAP_MASK(1) +#define ICE_PGNCK_F3_S 15 +#define ICE_PGNCK_F3_M BITMAP_MASK(1) +#define ICE_PGNCK_BH_S 16 +#define ICE_PGNCK_BH_M BITMAP_MASK(1) +#define ICE_PGNCK_BI_S 17 +#define ICE_PGNCK_BI_M BITMAP_MASK(8) +#define ICE_PGNCK_AR_S 25 +#define ICE_PGNCK_AR_M BITMAP_MASK(16) + +struct ice_pg_nm_cam_key { + bool valid; + u16 node_id; + bool flag0; + bool flag1; + bool flag2; + bool flag3; + u8 boost_idx; + u16 alu_reg; +}; + +#define ICE_PGCA_NN_S 0 +#define ICE_PGCA_NN_M BITMAP_MASK(11) +#define ICE_PGCA_NP_S 11 +#define ICE_PGCA_NP_M BITMAP_MASK(8) +#define ICE_PGCA_IPG_S 19 +#define ICE_PGCA_IPG_M BITMAP_MASK(1) +#define ICE_PGCA_PID_S 23 +#define ICE_PGCA_PID_M BITMAP_MASK(8) +#define ICE_PGCA_IMG_S 31 +#define ICE_PGCA_IMG_M BITMAP_MASK(1) +#define ICE_PGCA_MID_S 32 +#define ICE_PGCA_MID_M BITMAP_MASK(8) +#define ICE_PGCA_ILR_S 40 +#define ICE_PGCA_ILR_M BITMAP_MASK(1) +#define ICE_PGCA_HOP_S 41 +#define ICE_PGCA_HOP_M BITMAP_MASK(1) +#define ICE_PGCA_HOI_S 42 +#define ICE_PGCA_HOI_M BITMAP_MASK(9) + +struct ice_pg_cam_action { + u16 next_node; + u8 next_pc; + bool is_pg; + u8 proto_id; + bool is_mg; + u8 marker_id; + bool is_last_round; + bool ho_polarity; + u16 ho_inc; +}; + +#define ICE_PG_CAM_KEY_OFF 0 +#define ICE_PG_CAM_ACT_OFF 73 +#define ICE_PG_SP_CAM_ACT_OFF 0 +#define ICE_PG_SP_CAM_KEY_OFF 56 + +struct ice_pg_cam_item { + u16 idx; + struct ice_pg_cam_key key; + struct ice_pg_cam_action action; +}; + +#define ICE_PG_NM_CAM_KEY_OFF 0 +#define ICE_PG_NM_CAM_ACT_OFF 41 +#define ICE_PG_NM_SP_CAM_KEY_OFF 0 +#define ICE_PG_NM_SP_CAM_ACT_OFF 56 + +struct ice_pg_nm_cam_item { + u16 idx; + struct ice_pg_nm_cam_key key; + struct ice_pg_cam_action action; +}; + +void ice_pg_cam_dump(struct ice_hw *hw, struct ice_pg_cam_item *item); +void ice_pg_nm_cam_dump(struct ice_hw *hw, struct ice_pg_nm_cam_item *item); + +struct ice_pg_cam_item *ice_pg_cam_table_get(struct ice_hw *hw); +struct ice_pg_cam_item *ice_pg_sp_cam_table_get(struct ice_hw *hw); + +struct ice_pg_nm_cam_item *ice_pg_nm_cam_table_get(struct ice_hw *hw); +struct ice_pg_nm_cam_item *ice_pg_nm_sp_cam_table_get(struct ice_hw *hw); +#endif /* _ICE_PG_CAM_H_ */ From patchwork Mon Aug 21 08:14:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359246 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 798E34A0E for ; Mon, 21 Aug 2023 08:15:08 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68279BD for ; Mon, 21 Aug 2023 01:15:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692605704; x=1724141704; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0ELWPeHpBpBSyd1b5u0YKbYfDQzJwk9gmM/VnlaN5HA=; b=Cy9PB8EVrmCfK6UGlkeRZ318QSwI/gHVeo98cQlvcif4oT4DD01o68Ck MehPWTNeKHmIr+gWE5RGiX+KrkiPH+Hq+5WpM3z4JrzJdd7js9w6QNb6T 9LesXi0SwVUDkhFZJMbRf9Ek+5tKkyqgMOIXhQ5NXFdPSBN24dgoGoI9N kb3tbTOc58uenSqoa7CZNxbFs+oNUccPNz0uQD7lSf2rVrhypuNz73z4p 9Bc9BI04wOSYGhNU6zbY+0tl4thDYLFFDlncGOTx304ADQfhhjkzikJ1l DDlw9CvcrWnByZOAev5qbZmOAe5xtKVZJlb0WDj/pv3z19IA8e/cTTCzC A==; X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="376280414" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="376280414" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2023 01:15:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="685577493" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577493" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:15:00 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 05/15] ice: init boost tcam and label tables for parser Date: Mon, 21 Aug 2023 16:14:28 +0800 Message-Id: <20230821081438.2937934-6-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Parse DDP section ICE_SID_RXPARSER_CAM into an array of ice_bst_tcam_item. Parse DDP section ICE_SID_LBL_RXPARSER_TMEM into an array of ice_lbl_item. Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/ice_bst_tcam.c | 273 ++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_bst_tcam.h | 45 +++ drivers/net/ethernet/intel/ice/ice_imem.c | 2 +- drivers/net/ethernet/intel/ice/ice_metainit.c | 2 +- drivers/net/ethernet/intel/ice/ice_parser.c | 43 ++- drivers/net/ethernet/intel/ice/ice_parser.h | 9 + .../net/ethernet/intel/ice/ice_parser_util.h | 14 +- drivers/net/ethernet/intel/ice/ice_pg_cam.c | 8 +- 8 files changed, 387 insertions(+), 9 deletions(-) create mode 100644 drivers/net/ethernet/intel/ice/ice_bst_tcam.c create mode 100644 drivers/net/ethernet/intel/ice/ice_bst_tcam.h diff --git a/drivers/net/ethernet/intel/ice/ice_bst_tcam.c b/drivers/net/ethernet/intel/ice/ice_bst_tcam.c new file mode 100644 index 000000000000..9f232db164d9 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_bst_tcam.c @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2023 Intel Corporation */ + +#include "ice_common.h" +#include "ice_parser_util.h" + +static void _ice_bst_np_kb_dump(struct ice_hw *hw, + struct ice_np_keybuilder *kb) +{ + dev_info(ice_hw_to_dev(hw), "next proto key builder:\n"); + dev_info(ice_hw_to_dev(hw), "\topc = %d\n", kb->opc); + dev_info(ice_hw_to_dev(hw), "\tstart_reg0 = %d\n", kb->start_reg0); + dev_info(ice_hw_to_dev(hw), "\tlen_reg1 = %d\n", kb->len_reg1); +} + +static void _ice_bst_pg_kb_dump(struct ice_hw *hw, + struct ice_pg_keybuilder *kb) +{ + dev_info(ice_hw_to_dev(hw), "parse graph key builder:\n"); + dev_info(ice_hw_to_dev(hw), "\tflag0_ena = %d\n", kb->flag0_ena); + dev_info(ice_hw_to_dev(hw), "\tflag1_ena = %d\n", kb->flag1_ena); + dev_info(ice_hw_to_dev(hw), "\tflag2_ena = %d\n", kb->flag2_ena); + dev_info(ice_hw_to_dev(hw), "\tflag3_ena = %d\n", kb->flag3_ena); + dev_info(ice_hw_to_dev(hw), "\tflag0_idx = %d\n", kb->flag0_idx); + dev_info(ice_hw_to_dev(hw), "\tflag1_idx = %d\n", kb->flag1_idx); + dev_info(ice_hw_to_dev(hw), "\tflag2_idx = %d\n", kb->flag2_idx); + dev_info(ice_hw_to_dev(hw), "\tflag3_idx = %d\n", kb->flag3_idx); + dev_info(ice_hw_to_dev(hw), "\talu_reg_idx = %d\n", kb->alu_reg_idx); +} + +static void _ice_bst_alu_dump(struct ice_hw *hw, struct ice_alu *alu, int idx) +{ + dev_info(ice_hw_to_dev(hw), "alu%d:\n", idx); + dev_info(ice_hw_to_dev(hw), "\topc = %d\n", alu->opc); + dev_info(ice_hw_to_dev(hw), "\tsrc_start = %d\n", alu->src_start); + dev_info(ice_hw_to_dev(hw), "\tsrc_len = %d\n", alu->src_len); + dev_info(ice_hw_to_dev(hw), "\tshift_xlate_sel = %d\n", + alu->shift_xlate_sel); + dev_info(ice_hw_to_dev(hw), "\tshift_xlate_key = %d\n", + alu->shift_xlate_key); + dev_info(ice_hw_to_dev(hw), "\tsrc_reg_id = %d\n", alu->src_reg_id); + dev_info(ice_hw_to_dev(hw), "\tdst_reg_id = %d\n", alu->dst_reg_id); + dev_info(ice_hw_to_dev(hw), "\tinc0 = %d\n", alu->inc0); + dev_info(ice_hw_to_dev(hw), "\tinc1 = %d\n", alu->inc1); + dev_info(ice_hw_to_dev(hw), "\tproto_offset_opc = %d\n", + alu->proto_offset_opc); + dev_info(ice_hw_to_dev(hw), "\tproto_offset = %d\n", + alu->proto_offset); + dev_info(ice_hw_to_dev(hw), "\tbranch_addr = %d\n", alu->branch_addr); + dev_info(ice_hw_to_dev(hw), "\timm = %d\n", alu->imm); + dev_info(ice_hw_to_dev(hw), "\tdst_start = %d\n", alu->dst_start); + dev_info(ice_hw_to_dev(hw), "\tdst_len = %d\n", alu->dst_len); + dev_info(ice_hw_to_dev(hw), "\tflags_extr_imm = %d\n", + alu->flags_extr_imm); + dev_info(ice_hw_to_dev(hw), "\tflags_start_imm= %d\n", + alu->flags_start_imm); +} + +/** + * ice_bst_tcam_dump - dump a boost tcam info + * @hw: pointer to the hardware structure + * @item: boost tcam to dump + */ +void ice_bst_tcam_dump(struct ice_hw *hw, struct ice_bst_tcam_item *item) +{ + int i; + + dev_info(ice_hw_to_dev(hw), "addr = %d\n", item->addr); + dev_info(ice_hw_to_dev(hw), "key : "); + for (i = 0; i < ICE_BST_TCAM_KEY_SIZE; i++) + dev_info(ice_hw_to_dev(hw), "%02x ", item->key[i]); + dev_info(ice_hw_to_dev(hw), "\n"); + dev_info(ice_hw_to_dev(hw), "key_inv: "); + for (i = 0; i < ICE_BST_TCAM_KEY_SIZE; i++) + dev_info(ice_hw_to_dev(hw), "%02x ", item->key_inv[i]); + dev_info(ice_hw_to_dev(hw), "\n"); + dev_info(ice_hw_to_dev(hw), "hit_idx_grp = %d\n", item->hit_idx_grp); + dev_info(ice_hw_to_dev(hw), "pg_pri = %d\n", item->pg_pri); + + _ice_bst_np_kb_dump(hw, &item->np_kb); + _ice_bst_pg_kb_dump(hw, &item->pg_kb); + + _ice_bst_alu_dump(hw, &item->alu0, ICE_ALU0_IDX); + _ice_bst_alu_dump(hw, &item->alu1, ICE_ALU1_IDX); + _ice_bst_alu_dump(hw, &item->alu2, ICE_ALU2_IDX); +} + +/** The function parses a 96 bits ALU entry with below format: + * BIT 0-5: Opcode (alu->opc) + * BIT 6-13: Source Start (alu->src_start) + * BIT 14-18: Source Length (alu->src_len) + * BIT 19: Shift/Xlate Select (alu->shift_xlate_select) + * BIT 20-23: Shift/Xlate Key (alu->shift_xlate_key) + * BIT 24-30: Source Register ID (alu->src_reg_id) + * BIT 31-37: Dest. Register ID (alu->dst_reg_id) + * BIT 38: Inc0 (alu->inc0) + * BIT 39: Inc1 (alu->inc1) + * BIT 40:41 Protocol Offset Opcode (alu->proto_offset_opc) + * BIT 42:49 Protocol Offset (alu->proto_offset) + * BIT 50:57 Branch Address (alu->branch_addr) + * BIT 58:73 Immediate (alu->imm) + * BIT 74 Dedicated Flags Enable (alu->dedicate_flags_ena) + * BIT 75:80 Dest. Start (alu->dst_start) + * BIT 81:86 Dest. Length (alu->dst_len) + * BIT 87 Flags Extract Imm. (alu->flags_extr_imm) + * BIT 88:95 Flags Start/Immediate (alu->flags_start_imm) + * + */ +static void _ice_bst_alu_init(struct ice_alu *alu, u8 *data, u8 off) +{ + u64 d64; + u8 idd; + + d64 = *((u64 *)data) >> off; + + alu->opc = (enum ice_alu_opcode)(d64 & ICE_ALU_OPC_M); + alu->src_start = (u8)((d64 >> ICE_ALU_SS_S) & ICE_ALU_SS_M); + alu->src_len = (u8)((d64 >> ICE_ALU_SL_S) & ICE_ALU_SL_M); + alu->shift_xlate_sel = !!((d64 >> ICE_ALU_SXS_S) & ICE_ALU_SXS_M); + alu->shift_xlate_key = (u8)((d64 >> ICE_ALU_SXK_S) & ICE_ALU_SXK_M); + alu->src_reg_id = (u8)((d64 >> ICE_ALU_SRI_S) & ICE_ALU_SRI_M); + alu->dst_reg_id = (u8)((d64 >> ICE_ALU_DRI_S) & ICE_ALU_DRI_M); + alu->inc0 = !!((d64 >> ICE_ALU_INC0_S) & ICE_ALU_INC0_M); + alu->inc1 = !!((d64 >> ICE_ALU_INC1_S) & ICE_ALU_INC1_M); + alu->proto_offset_opc = (u8)((d64 >> ICE_ALU_POO_S) & ICE_ALU_POO_M); + alu->proto_offset = (u8)((d64 >> ICE_ALU_PO_S) & ICE_ALU_PO_M); + + idd = (ICE_ALU_BA_S + off) / BITS_PER_BYTE; + off = (ICE_ALU_BA_S + off) % BITS_PER_BYTE; + d64 = *((u64 *)(&data[idd])) >> off; + + alu->branch_addr = (u8)(d64 & ICE_ALU_BA_M); + off = ICE_ALU_IMM_S - ICE_ALU_BA_S; + alu->imm = (u16)((d64 >> off) & ICE_ALU_IMM_M); + off = ICE_ALU_DFE_S - ICE_ALU_BA_S; + alu->dedicate_flags_ena = !!((d64 >> off) & ICE_ALU_DFE_M); + off = ICE_ALU_DS_S - ICE_ALU_BA_S; + alu->dst_start = (u8)((d64 >> off) & ICE_ALU_DS_M); + off = ICE_ALU_DL_S - ICE_ALU_BA_S; + alu->dst_len = (u8)((d64 >> off) & ICE_ALU_DL_M); + off = ICE_ALU_FEI_S - ICE_ALU_BA_S; + alu->flags_extr_imm = !!((d64 >> off) & ICE_ALU_FEI_M); + off = ICE_ALU_FSI_S - ICE_ALU_BA_S; + alu->flags_start_imm = (u8)((d64 >> off) & ICE_ALU_FSI_M); +} + +/** The function parses a 35 bits Parse Graph Key Build with below format: + * BIT 0: Flag 0 Enable (kb->flag0_ena) + * BIT 1-6: Flag 0 Index (kb->flag0_idx) + * BIT 7: Flag 1 Enable (kb->flag1_ena) + * BIT 8-13: Flag 1 Index (kb->flag1_idx) + * BIT 14: Flag 2 Enable (kb->flag2_ena) + * BIT 15-20: Flag 2 Index (kb->flag2_idx) + * BIT 21: Flag 3 Enable (kb->flag3_ena) + * BIT 22-27: Flag 3 Index (kb->flag3_idx) + * BIT 28-34: ALU Register Index (kb->alu_reg_idx) + */ +static void _ice_bst_pgkb_init(struct ice_pg_keybuilder *kb, u64 data) +{ + kb->flag0_ena = !!(data & ICE_PGKB_F0E_M); + kb->flag0_idx = (u8)((data >> ICE_PGKB_F0I_S) & ICE_PGKB_F0I_M); + kb->flag1_ena = !!((data >> ICE_PGKB_F1E_S) & ICE_PGKB_F1E_M); + kb->flag1_idx = (u8)((data >> ICE_PGKB_F1I_S) & ICE_PGKB_F1I_M); + kb->flag2_ena = !!((data >> ICE_PGKB_F2E_S) & ICE_PGKB_F2E_M); + kb->flag2_idx = (u8)((data >> ICE_PGKB_F2I_S) & ICE_PGKB_F2I_M); + kb->flag3_ena = !!((data >> ICE_PGKB_F3E_S) & ICE_PGKB_F3E_M); + kb->flag3_idx = (u8)((data >> ICE_PGKB_F3I_S) & ICE_PGKB_F3I_M); + kb->alu_reg_idx = (u8)((data >> ICE_PGKB_ARI_S) & ICE_PGKB_ARI_M); +} + +/** The function parses a 18 bits Next Protocol Key Build with below format: + * BIT 0-1: Opcode (kb->ops) + * BIT 2-9: Start / Reg 0 (kb->start_or_reg0) + * BIT 10-17: Length / Reg 1 (kb->len_or_reg1) + */ +static void _ice_bst_npkb_init(struct ice_np_keybuilder *kb, u32 data) +{ + kb->opc = (u8)(data & ICE_NPKB_OPC_M); + kb->start_reg0 = (u8)((data >> ICE_NPKB_SR0_S) & ICE_NPKB_SR0_M); + kb->len_reg1 = (u8)((data >> ICE_NPKB_LR1_S) & ICE_NPKB_LR1_M); +} + +/** The function parses a 704 bits Boost TCAM entry with below format: + * BIT 0-15: Address (ti->address) + * BIT 16-31: reserved + * BIT 32-191: Key (ti->key) + * BIT 192-351:Key Invert (ti->key_inv) + * BIT 352-359:Boost Hit Index Group (ti->hit_idx_grp) + * BIT 360-361:PG Priority (ti->pg_pri) + * BIT 362-379:Next Proto Key Build (ti->np_kb) + * BIT 380-414:PG Key Build (ti->pg_kb) + * BIT 415-510:ALU 0 (ti->alu0) + * BIT 511-606:ALU 1 (ti->alu1) + * BIT 607-702:ALU 2 (ti->alu2) + * BIT 703: reserved + */ +static void _ice_bst_parse_item(struct ice_hw *hw, u16 idx, void *item, + void *data, int size) +{ + struct ice_bst_tcam_item *ti = item; + u8 *buf = (u8 *)data; + u8 idd, off; + int i; + + ti->addr = *(u16 *)buf; + + for (i = 0; i < ICE_BST_TCAM_KEY_SIZE; i++) { + ti->key[i] = buf[(ICE_BT_KEY_S / BITS_PER_BYTE) + i]; + ti->key_inv[i] = buf[(ICE_BT_KIV_S / BITS_PER_BYTE) + i]; + } + ti->hit_idx_grp = buf[ICE_BT_HIG_S / BITS_PER_BYTE]; + ti->pg_pri = buf[ICE_BT_PGP_S / BITS_PER_BYTE] & ICE_BT_PGP_M; + + idd = ICE_BT_NPKB_S / BITS_PER_BYTE; + off = ICE_BT_NPKB_S % BITS_PER_BYTE; + _ice_bst_npkb_init(&ti->np_kb, *((u32 *)(&buf[idd])) >> off); + + idd = ICE_BT_PGKB_S / BITS_PER_BYTE; + off = ICE_BT_PGKB_S % BITS_PER_BYTE; + _ice_bst_pgkb_init(&ti->pg_kb, *((u64 *)(&buf[idd])) >> off); + + idd = ICE_BT_ALU0_S / BITS_PER_BYTE; + off = ICE_BT_ALU0_S % BITS_PER_BYTE; + _ice_bst_alu_init(&ti->alu0, &buf[idd], off); + + idd = ICE_BT_ALU1_S / BITS_PER_BYTE; + off = ICE_BT_ALU1_S % BITS_PER_BYTE; + _ice_bst_alu_init(&ti->alu1, &buf[idd], off); + + idd = ICE_BT_ALU2_S / BITS_PER_BYTE; + off = ICE_BT_ALU2_S % BITS_PER_BYTE; + _ice_bst_alu_init(&ti->alu2, &buf[idd], off); + + if (hw->debug_mask & ICE_DBG_PARSER) + ice_bst_tcam_dump(hw, ti); +} + +/** + * ice_bst_tcam_table_get - create a boost tcam table + * @hw: pointer to the hardware structure + */ +struct ice_bst_tcam_item *ice_bst_tcam_table_get(struct ice_hw *hw) +{ + return (struct ice_bst_tcam_item *) + ice_parser_create_table(hw, ICE_SID_RXPARSER_BOOST_TCAM, + sizeof(struct ice_bst_tcam_item), + ICE_BST_TCAM_TABLE_SIZE, + ice_parser_sect_item_get, + _ice_bst_parse_item, true); +} + +static void _ice_parse_lbl_item(struct ice_hw *hw, u16 idx, void *item, + void *data, int size) +{ + ice_parse_item_dflt(hw, idx, item, data, size); + + if (hw->debug_mask & ICE_DBG_PARSER) + ice_lbl_dump(hw, (struct ice_lbl_item *)item); +} + +/** + * ice_bst_lbl_table_get - create a boost label table + * @hw: pointer to the hardware structure + */ +struct ice_lbl_item *ice_bst_lbl_table_get(struct ice_hw *hw) +{ + return (struct ice_lbl_item *) + ice_parser_create_table(hw, ICE_SID_LBL_RXPARSER_TMEM, + sizeof(struct ice_lbl_item), + ICE_BST_TCAM_TABLE_SIZE, + ice_parser_sect_item_get, + _ice_parse_lbl_item, true); +} diff --git a/drivers/net/ethernet/intel/ice/ice_bst_tcam.h b/drivers/net/ethernet/intel/ice/ice_bst_tcam.h new file mode 100644 index 000000000000..b1b1dc224d70 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_bst_tcam.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2023 Intel Corporation */ + +#ifndef _ICE_BST_TCAM_H_ +#define _ICE_BST_TCAM_H_ + +#include "ice_imem.h" + +#define ICE_BST_TCAM_TABLE_SIZE 256 +#define ICE_BST_TCAM_KEY_SIZE 20 + +#define ICE_BST_KEY_TSR_SIZE 1 +#define ICE_BST_KEY_TCAM_SIZE 19 + +#define ICE_BT_ADDR_S 0 +#define ICE_BT_KEY_S 32 +#define ICE_BT_KIV_S 192 +#define ICE_BT_HIG_S 352 +#define ICE_BT_PGP_S 360 +#define ICE_BT_PGP_M BITMAP_MASK(2) +#define ICE_BT_NPKB_S 362 +#define ICE_BT_PGKB_S 380 +#define ICE_BT_ALU0_S 415 +#define ICE_BT_ALU1_S 511 +#define ICE_BT_ALU2_S 607 + +struct ice_bst_tcam_item { + u16 addr; + u8 key[ICE_BST_TCAM_KEY_SIZE]; + u8 key_inv[ICE_BST_TCAM_KEY_SIZE]; + u8 hit_idx_grp; + u8 pg_pri; + struct ice_np_keybuilder np_kb; + struct ice_pg_keybuilder pg_kb; + struct ice_alu alu0; + struct ice_alu alu1; + struct ice_alu alu2; +}; + +void ice_bst_tcam_dump(struct ice_hw *hw, struct ice_bst_tcam_item *item); + +struct ice_bst_tcam_item *ice_bst_tcam_table_get(struct ice_hw *hw); + +struct ice_lbl_item *ice_bst_lbl_table_get(struct ice_hw *hw); +#endif /*_ICE_BST_TCAM_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_imem.c b/drivers/net/ethernet/intel/ice/ice_imem.c index 5e6ded40fa6e..f97e545f0f98 100644 --- a/drivers/net/ethernet/intel/ice/ice_imem.c +++ b/drivers/net/ethernet/intel/ice/ice_imem.c @@ -275,5 +275,5 @@ struct ice_imem_item *ice_imem_table_get(struct ice_hw *hw) sizeof(struct ice_imem_item), ICE_IMEM_TABLE_SIZE, ice_parser_sect_item_get, - _ice_imem_parse_item); + _ice_imem_parse_item, false); } diff --git a/drivers/net/ethernet/intel/ice/ice_metainit.c b/drivers/net/ethernet/intel/ice/ice_metainit.c index de7b6da548f6..1ce90060690a 100644 --- a/drivers/net/ethernet/intel/ice/ice_metainit.c +++ b/drivers/net/ethernet/intel/ice/ice_metainit.c @@ -177,5 +177,5 @@ struct ice_metainit_item *ice_metainit_table_get(struct ice_hw *hw) sizeof(struct ice_metainit_item), ICE_METAINIT_TABLE_SIZE, ice_parser_sect_item_get, - _ice_metainit_parse_item); + _ice_metainit_parse_item, false); } diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c index b654135419fb..e5f0ae7be612 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.c +++ b/drivers/net/ethernet/intel/ice/ice_parser.c @@ -4,6 +4,18 @@ #include "ice_common.h" #include "ice_parser_util.h" +void ice_lbl_dump(struct ice_hw *hw, struct ice_lbl_item *item) +{ + dev_info(ice_hw_to_dev(hw), "index = %d\n", item->idx); + dev_info(ice_hw_to_dev(hw), "label = %s\n", item->label); +} + +void ice_parse_item_dflt(struct ice_hw *hw, u16 idx, void *item, + void *data, int size) +{ + memcpy(item, data, size); +} + /** * ice_parser_sect_item_get - parse a item from a section * @sect_type: section type @@ -40,6 +52,13 @@ void *ice_parser_sect_item_get(u32 sect_type, void *section, case ICE_SID_RXPARSER_NOMATCH_SPILL: size = ICE_SID_RXPARSER_NOMATCH_SPILL_ENTRY_SIZE; break; + case ICE_SID_RXPARSER_BOOST_TCAM: + size = ICE_SID_RXPARSER_BOOST_TCAM_ENTRY_SIZE; + break; + case ICE_SID_LBL_RXPARSER_TMEM: + data_off = ICE_SEC_LBL_DATA_OFFSET; + size = ICE_SID_LBL_ENTRY_SIZE; + break; default: return NULL; } @@ -59,6 +78,7 @@ void *ice_parser_sect_item_get(u32 sect_type, void *section, * @length: number of items in the table to create * @item_get: the function will be parsed to ice_pkg_enum_entry * @parse_item: the function to parse the item + * @no_offset: ignore header offset, calculate index from 0 */ void *ice_parser_create_table(struct ice_hw *hw, u32 sect_type, u32 item_size, u32 length, @@ -66,7 +86,8 @@ void *ice_parser_create_table(struct ice_hw *hw, u32 sect_type, u32 index, u32 *offset), void (*parse_item)(struct ice_hw *hw, u16 idx, void *item, void *data, - int size)) + int size), + bool no_offset) { struct ice_seg *seg = hw->seg; struct ice_pkg_enum state; @@ -91,7 +112,11 @@ void *ice_parser_create_table(struct ice_hw *hw, u32 sect_type, struct ice_pkg_sect_hdr *hdr = (struct ice_pkg_sect_hdr *)state.sect; - idx = le16_to_cpu(hdr->offset) + state.entry_idx; + if (no_offset) + idx++; + else + idx = le16_to_cpu(hdr->offset) + + state.entry_idx; parse_item(hw, idx, (void *)((uintptr_t)table + ((uintptr_t)idx * @@ -156,6 +181,18 @@ int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr) goto err; } + p->bst_tcam_table = ice_bst_tcam_table_get(hw); + if (!p->bst_tcam_table) { + status = -EINVAL; + goto err; + } + + p->bst_lbl_table = ice_bst_lbl_table_get(hw); + if (!p->bst_lbl_table) { + status = -EINVAL; + goto err; + } + *psr = p; return 0; err: @@ -175,6 +212,8 @@ void ice_parser_destroy(struct ice_parser *psr) devm_kfree(ice_hw_to_dev(psr->hw), psr->pg_sp_cam_table); devm_kfree(ice_hw_to_dev(psr->hw), psr->pg_nm_cam_table); devm_kfree(ice_hw_to_dev(psr->hw), psr->pg_nm_sp_cam_table); + devm_kfree(ice_hw_to_dev(psr->hw), psr->bst_tcam_table); + devm_kfree(ice_hw_to_dev(psr->hw), psr->bst_lbl_table); devm_kfree(ice_hw_to_dev(psr->hw), psr); } diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h index c709c56bf2e6..14d17c7c8479 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.h +++ b/drivers/net/ethernet/intel/ice/ice_parser.h @@ -7,6 +7,7 @@ #include "ice_metainit.h" #include "ice_imem.h" #include "ice_pg_cam.h" +#include "ice_bst_tcam.h" #define ICE_SEC_DATA_OFFSET 4 #define ICE_SID_RXPARSER_IMEM_ENTRY_SIZE 48 @@ -15,6 +16,10 @@ #define ICE_SID_RXPARSER_PG_SPILL_ENTRY_SIZE 17 #define ICE_SID_RXPARSER_NOMATCH_CAM_ENTRY_SIZE 12 #define ICE_SID_RXPARSER_NOMATCH_SPILL_ENTRY_SIZE 13 +#define ICE_SID_RXPARSER_BOOST_TCAM_ENTRY_SIZE 88 + +#define ICE_SEC_LBL_DATA_OFFSET 2 +#define ICE_SID_LBL_ENTRY_SIZE 66 struct ice_parser { struct ice_hw *hw; /* pointer to the hardware structure */ @@ -31,6 +36,10 @@ struct ice_parser { struct ice_pg_nm_cam_item *pg_nm_cam_table; /* load data from section ICE_SID_RXPARSER_NOMATCH_SPILL */ struct ice_pg_nm_cam_item *pg_nm_sp_cam_table; + /* load data from section ICE_SID_RXPARSER_BOOST_TCAM */ + struct ice_bst_tcam_item *bst_tcam_table; + /* load data from section ICE_SID_LBL_RXPARSER_TMEM */ + struct ice_lbl_item *bst_lbl_table; }; int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr); diff --git a/drivers/net/ethernet/intel/ice/ice_parser_util.h b/drivers/net/ethernet/intel/ice/ice_parser_util.h index 42a91bd51a51..defa7ac1f5d9 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser_util.h +++ b/drivers/net/ethernet/intel/ice/ice_parser_util.h @@ -7,11 +7,22 @@ #include "ice_imem.h" #include "ice_metainit.h" +#define ICE_LBL_LEN 64 + +struct ice_lbl_item { + u16 idx; + char label[ICE_LBL_LEN]; +}; + struct ice_pkg_sect_hdr { __le16 count; __le16 offset; }; +void ice_lbl_dump(struct ice_hw *hw, struct ice_lbl_item *item); +void ice_parse_item_dflt(struct ice_hw *hw, u16 idx, void *item, + void *data, int size); + void *ice_parser_sect_item_get(u32 sect_type, void *section, u32 index, u32 *offset); @@ -21,5 +32,6 @@ void *ice_parser_create_table(struct ice_hw *hw, u32 sect_type, u32 index, u32 *offset), void (*parse_item)(struct ice_hw *hw, u16 idx, void *item, void *data, - int size)); + int size), + bool no_offset); #endif /* _ICE_PARSER_UTIL_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_pg_cam.c b/drivers/net/ethernet/intel/ice/ice_pg_cam.c index 82a8c916d5ce..70b0b0b93a8d 100644 --- a/drivers/net/ethernet/intel/ice/ice_pg_cam.c +++ b/drivers/net/ethernet/intel/ice/ice_pg_cam.c @@ -275,7 +275,7 @@ struct ice_pg_cam_item *ice_pg_cam_table_get(struct ice_hw *hw) sizeof(struct ice_pg_cam_item), ICE_PG_CAM_TABLE_SIZE, ice_parser_sect_item_get, - _ice_pg_cam_parse_item); + _ice_pg_cam_parse_item, false); } /** @@ -289,7 +289,7 @@ struct ice_pg_cam_item *ice_pg_sp_cam_table_get(struct ice_hw *hw) sizeof(struct ice_pg_cam_item), ICE_PG_SP_CAM_TABLE_SIZE, ice_parser_sect_item_get, - _ice_pg_sp_cam_parse_item); + _ice_pg_sp_cam_parse_item, false); } /** @@ -303,7 +303,7 @@ struct ice_pg_nm_cam_item *ice_pg_nm_cam_table_get(struct ice_hw *hw) sizeof(struct ice_pg_nm_cam_item), ICE_PG_NM_CAM_TABLE_SIZE, ice_parser_sect_item_get, - _ice_pg_nm_cam_parse_item); + _ice_pg_nm_cam_parse_item, false); } /** @@ -317,5 +317,5 @@ struct ice_pg_nm_cam_item *ice_pg_nm_sp_cam_table_get(struct ice_hw *hw) sizeof(struct ice_pg_nm_cam_item), ICE_PG_NM_SP_CAM_TABLE_SIZE, ice_parser_sect_item_get, - _ice_pg_nm_sp_cam_parse_item); + _ice_pg_nm_sp_cam_parse_item, false); } From patchwork Mon Aug 21 08:14:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359247 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D8414A0E for ; Mon, 21 Aug 2023 08:15:10 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16119C4 for ; Mon, 21 Aug 2023 01:15:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692605708; x=1724141708; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZtZPTtuh6KRLFmuu9JOc1XxTJm/BImqlewiABGBI4Cg=; b=OMyym721gDURYmKN+RSS6h0n9VhUvksFt207iT9h9A71gMTnqxVdii1r pFV2SzHkDQTAq99LisG0VjrUJVtXD2lpWrUYquuqBz1bhviRdE9TCBK9Q BRlIdBqqN1VUX97SWTLblgLTkJpwozAPJdgmrYEV9Vg5MPCQ9O9LyOtPf YlSft137vcwUjeDiUODIntIZMcDrQ40Fb4euU6bkcOJm7Vfq7aHd1WUup ikRCk4RpCzTBTPcceyTeq7fi7mQwaVbcvsRKVAJDikF44QEqiZVFEXuKj uDyvRzek/ZIQH/owphe921yz4Sh69cyHeapwH/P5OFa3JihEeQTyg5hae g==; X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="376280421" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="376280421" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2023 01:15:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="685577527" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577527" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:15:03 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 06/15] ice: init ptype marker tcam table for parser Date: Mon, 21 Aug 2023 16:14:29 +0800 Message-Id: <20230821081438.2937934-7-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Parse DDP section ICE_SID_RXPARSER_MARKER_PTYPE into an array of ice_ptype_mk_tcam_item. Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/ice_parser.c | 10 ++++ drivers/net/ethernet/intel/ice/ice_parser.h | 4 ++ drivers/net/ethernet/intel/ice/ice_ptype_mk.c | 51 +++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_ptype_mk.h | 20 ++++++++ 4 files changed, 85 insertions(+) create mode 100644 drivers/net/ethernet/intel/ice/ice_ptype_mk.c create mode 100644 drivers/net/ethernet/intel/ice/ice_ptype_mk.h diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c index e5f0ae7be612..01684a7c5c75 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.c +++ b/drivers/net/ethernet/intel/ice/ice_parser.c @@ -59,6 +59,9 @@ void *ice_parser_sect_item_get(u32 sect_type, void *section, data_off = ICE_SEC_LBL_DATA_OFFSET; size = ICE_SID_LBL_ENTRY_SIZE; break; + case ICE_SID_RXPARSER_MARKER_PTYPE: + size = ICE_SID_RXPARSER_MARKER_TYPE_ENTRY_SIZE; + break; default: return NULL; } @@ -193,6 +196,12 @@ int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr) goto err; } + p->ptype_mk_tcam_table = ice_ptype_mk_tcam_table_get(hw); + if (!p->ptype_mk_tcam_table) { + status = -EINVAL; + goto err; + } + *psr = p; return 0; err: @@ -214,6 +223,7 @@ void ice_parser_destroy(struct ice_parser *psr) devm_kfree(ice_hw_to_dev(psr->hw), psr->pg_nm_sp_cam_table); devm_kfree(ice_hw_to_dev(psr->hw), psr->bst_tcam_table); devm_kfree(ice_hw_to_dev(psr->hw), psr->bst_lbl_table); + devm_kfree(ice_hw_to_dev(psr->hw), psr->ptype_mk_tcam_table); devm_kfree(ice_hw_to_dev(psr->hw), psr); } diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h index 14d17c7c8479..c0ac4b2a9a6e 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.h +++ b/drivers/net/ethernet/intel/ice/ice_parser.h @@ -8,6 +8,7 @@ #include "ice_imem.h" #include "ice_pg_cam.h" #include "ice_bst_tcam.h" +#include "ice_ptype_mk.h" #define ICE_SEC_DATA_OFFSET 4 #define ICE_SID_RXPARSER_IMEM_ENTRY_SIZE 48 @@ -17,6 +18,7 @@ #define ICE_SID_RXPARSER_NOMATCH_CAM_ENTRY_SIZE 12 #define ICE_SID_RXPARSER_NOMATCH_SPILL_ENTRY_SIZE 13 #define ICE_SID_RXPARSER_BOOST_TCAM_ENTRY_SIZE 88 +#define ICE_SID_RXPARSER_MARKER_TYPE_ENTRY_SIZE 24 #define ICE_SEC_LBL_DATA_OFFSET 2 #define ICE_SID_LBL_ENTRY_SIZE 66 @@ -40,6 +42,8 @@ struct ice_parser { struct ice_bst_tcam_item *bst_tcam_table; /* load data from section ICE_SID_LBL_RXPARSER_TMEM */ struct ice_lbl_item *bst_lbl_table; + /* load data from section ICE_SID_RXPARSER_MARKER_PTYPE */ + struct ice_ptype_mk_tcam_item *ptype_mk_tcam_table; }; int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr); diff --git a/drivers/net/ethernet/intel/ice/ice_ptype_mk.c b/drivers/net/ethernet/intel/ice/ice_ptype_mk.c new file mode 100644 index 000000000000..ee7b09618d54 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_ptype_mk.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2023 Intel Corporation */ + +#include "ice_common.h" +#include "ice_parser_util.h" + +/** + * ice_ptype_mk_tcam_dump - dump an ptype marker tcam info_ + * @hw: pointer to the hardware structure + * @item: ptype marker tcam to dump + */ +void ice_ptype_mk_tcam_dump(struct ice_hw *hw, + struct ice_ptype_mk_tcam_item *item) +{ + int i; + + dev_info(ice_hw_to_dev(hw), "address = %d\n", item->address); + dev_info(ice_hw_to_dev(hw), "ptype = %d\n", item->ptype); + dev_info(ice_hw_to_dev(hw), "key :"); + for (i = 0; i < ICE_PTYPE_MK_TCAM_KEY_SIZE; i++) + dev_info(ice_hw_to_dev(hw), "%02x ", item->key[i]); + dev_info(ice_hw_to_dev(hw), "\n"); + dev_info(ice_hw_to_dev(hw), "key_inv:"); + for (i = 0; i < ICE_PTYPE_MK_TCAM_KEY_SIZE; i++) + dev_info(ice_hw_to_dev(hw), "%02x ", item->key_inv[i]); + dev_info(ice_hw_to_dev(hw), "\n"); +} + +static void _ice_parse_ptype_mk_tcam_item(struct ice_hw *hw, u16 idx, + void *item, void *data, int size) +{ + ice_parse_item_dflt(hw, idx, item, data, size); + + if (hw->debug_mask & ICE_DBG_PARSER) + ice_ptype_mk_tcam_dump(hw, + (struct ice_ptype_mk_tcam_item *)item); +} + +/** + * ice_ptype_mk_tcam_table_get - create a ptype marker tcam table + * @hw: pointer to the hardware structure + */ +struct ice_ptype_mk_tcam_item *ice_ptype_mk_tcam_table_get(struct ice_hw *hw) +{ + return (struct ice_ptype_mk_tcam_item *) + ice_parser_create_table(hw, ICE_SID_RXPARSER_MARKER_PTYPE, + sizeof(struct ice_ptype_mk_tcam_item), + ICE_PTYPE_MK_TCAM_TABLE_SIZE, + ice_parser_sect_item_get, + _ice_parse_ptype_mk_tcam_item, true); +} diff --git a/drivers/net/ethernet/intel/ice/ice_ptype_mk.h b/drivers/net/ethernet/intel/ice/ice_ptype_mk.h new file mode 100644 index 000000000000..4a071d823bea --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_ptype_mk.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2023 Intel Corporation */ + +#ifndef _ICE_PTYPE_MK_H_ +#define _ICE_PTYPE_MK_H_ + +#define ICE_PTYPE_MK_TCAM_TABLE_SIZE 1024 +#define ICE_PTYPE_MK_TCAM_KEY_SIZE 10 + +struct ice_ptype_mk_tcam_item { + u16 address; + u16 ptype; + u8 key[ICE_PTYPE_MK_TCAM_KEY_SIZE]; + u8 key_inv[ICE_PTYPE_MK_TCAM_KEY_SIZE]; +}; + +void ice_ptype_mk_tcam_dump(struct ice_hw *hw, + struct ice_ptype_mk_tcam_item *item); +struct ice_ptype_mk_tcam_item *ice_ptype_mk_tcam_table_get(struct ice_hw *hw); +#endif /* _ICE_PTYPE_MK_H_ */ From patchwork Mon Aug 21 08:14:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359248 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B00184A0E for ; Mon, 21 Aug 2023 08:15:14 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B11193 for ; Mon, 21 Aug 2023 01:15:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692605713; x=1724141713; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vCYWVvxkMdL4IFxwc3MUYglzDpuG2NQY5N5/RVHYwa8=; b=OTMHq43IZQ6eoU+Uy+UwZ/UcsTQ3zuhKjtP6vIhyhtFFePJE4eHJEUuf bn6Z4hv2nLaV7ruLkYOV8uFZE0UZL8njn81OnS5vowDh2KAyb9F4N4jmo frkeY3CIuVkv1LiLfNKMN1IuroWA1530dMCET2yPt+UU7Bhg/7l6Pj39h 4mjoJfd9SP/oG1Ycyt55f5sAO4gA9RGoYyGJBxNu7yF1OH4pVs98WXep/ XjyLLdKESpLN/zGSM8P/6MCN4idFjMVnqy5aRQEZV5+GIatbMqb6dcmr8 KSJ2x61XfbDrXGSdEM1SwX/nlT1d1xDZXMSfgthUSX7nEc6BEoBc85FSD g==; X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="376280435" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="376280435" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2023 01:15:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="685577551" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577551" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:15:07 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 07/15] ice: init marker and protocol group tables for parser Date: Mon, 21 Aug 2023 16:14:30 +0800 Message-Id: <20230821081438.2937934-8-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Parse DDP section ICE_SID_RXPARSER_MARKER_GRP into an array of ice_mk_grp_item. Parse DDP section ICE_SID_RXPARSER_PROTO_GRP into an array of ice_proto_grp_item. Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/ice_mk_grp.c | 51 +++++++++++ drivers/net/ethernet/intel/ice/ice_mk_grp.h | 17 ++++ drivers/net/ethernet/intel/ice/ice_parser.c | 20 +++++ drivers/net/ethernet/intel/ice/ice_parser.h | 8 ++ .../net/ethernet/intel/ice/ice_proto_grp.c | 90 +++++++++++++++++++ .../net/ethernet/intel/ice/ice_proto_grp.h | 31 +++++++ 6 files changed, 217 insertions(+) create mode 100644 drivers/net/ethernet/intel/ice/ice_mk_grp.c create mode 100644 drivers/net/ethernet/intel/ice/ice_mk_grp.h create mode 100644 drivers/net/ethernet/intel/ice/ice_proto_grp.c create mode 100644 drivers/net/ethernet/intel/ice/ice_proto_grp.h diff --git a/drivers/net/ethernet/intel/ice/ice_mk_grp.c b/drivers/net/ethernet/intel/ice/ice_mk_grp.c new file mode 100644 index 000000000000..395e43343165 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_mk_grp.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2023 Intel Corporation */ + +#include "ice_common.h" +#include "ice_parser_util.h" + +/** + * ice_mk_grp_dump - dump an marker group item info + * @hw: pointer to the hardware structure + * @item: marker group item to dump + */ +void ice_mk_grp_dump(struct ice_hw *hw, struct ice_mk_grp_item *item) +{ + int i; + + dev_info(ice_hw_to_dev(hw), "index = %d\n", item->idx); + dev_info(ice_hw_to_dev(hw), "markers: "); + for (i = 0; i < ICE_MK_COUNT_PER_GRP; i++) + dev_info(ice_hw_to_dev(hw), "%d ", item->markers[i]); + dev_info(ice_hw_to_dev(hw), "\n"); +} + +static void _ice_mk_grp_parse_item(struct ice_hw *hw, u16 idx, void *item, + void *data, int size) +{ + struct ice_mk_grp_item *grp = item; + u8 *buf = data; + int i; + + grp->idx = idx; + + for (i = 0; i < ICE_MK_COUNT_PER_GRP; i++) + grp->markers[i] = buf[i]; + + if (hw->debug_mask & ICE_DBG_PARSER) + ice_mk_grp_dump(hw, grp); +} + +/** + * ice_mk_grp_table_get - create a marker group table + * @hw: pointer to the hardware structure + */ +struct ice_mk_grp_item *ice_mk_grp_table_get(struct ice_hw *hw) +{ + return (struct ice_mk_grp_item *) + ice_parser_create_table(hw, ICE_SID_RXPARSER_MARKER_GRP, + sizeof(struct ice_mk_grp_item), + ICE_MK_GRP_TABLE_SIZE, + ice_parser_sect_item_get, + _ice_mk_grp_parse_item, false); +} diff --git a/drivers/net/ethernet/intel/ice/ice_mk_grp.h b/drivers/net/ethernet/intel/ice/ice_mk_grp.h new file mode 100644 index 000000000000..c5c8734b9d3e --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_mk_grp.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2023 Intel Corporation */ + +#ifndef _ICE_MK_GRP_H_ +#define _ICE_MK_GRP_H_ + +#define ICE_MK_GRP_TABLE_SIZE 128 +#define ICE_MK_COUNT_PER_GRP 8 + +struct ice_mk_grp_item { + int idx; + u8 markers[ICE_MK_COUNT_PER_GRP]; +}; + +void ice_mk_grp_dump(struct ice_hw *hw, struct ice_mk_grp_item *item); +struct ice_mk_grp_item *ice_mk_grp_table_get(struct ice_hw *hw); +#endif /* _ICE_MK_GRP_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c index 01684a7c5c75..4da2d4c21bab 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.c +++ b/drivers/net/ethernet/intel/ice/ice_parser.c @@ -62,6 +62,12 @@ void *ice_parser_sect_item_get(u32 sect_type, void *section, case ICE_SID_RXPARSER_MARKER_PTYPE: size = ICE_SID_RXPARSER_MARKER_TYPE_ENTRY_SIZE; break; + case ICE_SID_RXPARSER_MARKER_GRP: + size = ICE_SID_RXPARSER_MARKER_GRP_ENTRY_SIZE; + break; + case ICE_SID_RXPARSER_PROTO_GRP: + size = ICE_SID_RXPARSER_PROTO_GRP_ENTRY_SIZE; + break; default: return NULL; } @@ -202,6 +208,18 @@ int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr) goto err; } + p->mk_grp_table = ice_mk_grp_table_get(hw); + if (!p->mk_grp_table) { + status = -EINVAL; + goto err; + } + + p->proto_grp_table = ice_proto_grp_table_get(hw); + if (!p->proto_grp_table) { + status = -EINVAL; + goto err; + } + *psr = p; return 0; err: @@ -224,6 +242,8 @@ void ice_parser_destroy(struct ice_parser *psr) devm_kfree(ice_hw_to_dev(psr->hw), psr->bst_tcam_table); devm_kfree(ice_hw_to_dev(psr->hw), psr->bst_lbl_table); devm_kfree(ice_hw_to_dev(psr->hw), psr->ptype_mk_tcam_table); + devm_kfree(ice_hw_to_dev(psr->hw), psr->mk_grp_table); + devm_kfree(ice_hw_to_dev(psr->hw), psr->proto_grp_table); devm_kfree(ice_hw_to_dev(psr->hw), psr); } diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h index c0ac4b2a9a6e..4038833450f2 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.h +++ b/drivers/net/ethernet/intel/ice/ice_parser.h @@ -9,6 +9,8 @@ #include "ice_pg_cam.h" #include "ice_bst_tcam.h" #include "ice_ptype_mk.h" +#include "ice_mk_grp.h" +#include "ice_proto_grp.h" #define ICE_SEC_DATA_OFFSET 4 #define ICE_SID_RXPARSER_IMEM_ENTRY_SIZE 48 @@ -19,6 +21,8 @@ #define ICE_SID_RXPARSER_NOMATCH_SPILL_ENTRY_SIZE 13 #define ICE_SID_RXPARSER_BOOST_TCAM_ENTRY_SIZE 88 #define ICE_SID_RXPARSER_MARKER_TYPE_ENTRY_SIZE 24 +#define ICE_SID_RXPARSER_MARKER_GRP_ENTRY_SIZE 8 +#define ICE_SID_RXPARSER_PROTO_GRP_ENTRY_SIZE 24 #define ICE_SEC_LBL_DATA_OFFSET 2 #define ICE_SID_LBL_ENTRY_SIZE 66 @@ -44,6 +48,10 @@ struct ice_parser { struct ice_lbl_item *bst_lbl_table; /* load data from section ICE_SID_RXPARSER_MARKER_PTYPE */ struct ice_ptype_mk_tcam_item *ptype_mk_tcam_table; + /* load data from section ICE_SID_RXPARSER_MARKER_GRP */ + struct ice_mk_grp_item *mk_grp_table; + /* load data from section ICE_SID_RXPARSER_PROTO_GRP */ + struct ice_proto_grp_item *proto_grp_table; }; int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr); diff --git a/drivers/net/ethernet/intel/ice/ice_proto_grp.c b/drivers/net/ethernet/intel/ice/ice_proto_grp.c new file mode 100644 index 000000000000..c53970b47029 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_proto_grp.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2023 Intel Corporation */ + +#include "ice_common.h" +#include "ice_parser_util.h" + +static void _ice_proto_off_dump(struct ice_hw *hw, struct ice_proto_off *po, + int idx) +{ + dev_info(ice_hw_to_dev(hw), "proto %d\n", idx); + dev_info(ice_hw_to_dev(hw), "\tpolarity = %d\n", po->polarity); + dev_info(ice_hw_to_dev(hw), "\tproto_id = %d\n", po->proto_id); + dev_info(ice_hw_to_dev(hw), "\toffset = %d\n", po->offset); +} + +/** + * ice_proto_grp_dump - dump a proto group item info + * @hw: pointer to the hardware structure + * @item: proto group item to dump + */ +void ice_proto_grp_dump(struct ice_hw *hw, struct ice_proto_grp_item *item) +{ + int i; + + dev_info(ice_hw_to_dev(hw), "index = %d\n", item->idx); + + for (i = 0; i < ICE_PROTO_COUNT_PER_GRP; i++) + _ice_proto_off_dump(hw, &item->po[i], i); +} + +/** The function parses a 22 bits Protocol entry with below format: + * BIT 0: Polarity of Protocol Offset (po->polarity) + * BIT 1-8: Protocol ID (po->proto_id) + * BIT 9-11: reserved + * BIT 12-21: Protocol Offset (po->offset) + */ +static void _ice_proto_off_parse(struct ice_proto_off *po, u32 data) +{ + po->polarity = !!(data & ICE_PO_POL_M); + po->proto_id = (u8)((data >> ICE_PO_PID_S) & ICE_PO_PID_M); + po->offset = (u16)((data >> ICE_PO_OFF_S) & ICE_PO_OFF_M); +} + +/** The function parses a 192 bits Protocol Group Table entry with below + * format: + * BIT 0-21: Protocol 0 (grp->po[0]) + * BIT 22-43: Protocol 1 (grp->po[1]) + * BIT 44-65: Protocol 2 (grp->po[2]) + * BIT 66-87: Protocol 3 (grp->po[3]) + * BIT 88-109: Protocol 4 (grp->po[4]) + * BIT 110-131:Protocol 5 (grp->po[5]) + * BIT 132-153:Protocol 6 (grp->po[6]) + * BIT 154-175:Protocol 7 (grp->po[7]) + * BIT 176-191:reserved + */ +static void _ice_proto_grp_parse_item(struct ice_hw *hw, u16 idx, void *item, + void *data, int size) +{ + struct ice_proto_grp_item *grp = item; + u8 *buf = (u8 *)data; + u8 idd, off; + u32 d32; + int i; + + grp->idx = idx; + + for (i = 0; i < ICE_PROTO_COUNT_PER_GRP; i++) { + idd = (ICE_PROTO_GRP_ITEM_SIZE * i) / BITS_PER_BYTE; + off = (ICE_PROTO_GRP_ITEM_SIZE * i) % BITS_PER_BYTE; + d32 = *((u32 *)&buf[idd]) >> off; + _ice_proto_off_parse(&grp->po[i], d32); + } + + if (hw->debug_mask & ICE_DBG_PARSER) + ice_proto_grp_dump(hw, grp); +} + +/** + * ice_proto_grp_table_get - create a proto group table + * @hw: pointer to the hardware structure + */ +struct ice_proto_grp_item *ice_proto_grp_table_get(struct ice_hw *hw) +{ + return (struct ice_proto_grp_item *) + ice_parser_create_table(hw, ICE_SID_RXPARSER_PROTO_GRP, + sizeof(struct ice_proto_grp_item), + ICE_PROTO_GRP_TABLE_SIZE, + ice_parser_sect_item_get, + _ice_proto_grp_parse_item, false); +} diff --git a/drivers/net/ethernet/intel/ice/ice_proto_grp.h b/drivers/net/ethernet/intel/ice/ice_proto_grp.h new file mode 100644 index 000000000000..6e2b39151a92 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_proto_grp.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2023 Intel Corporation */ + +#ifndef _ICE_PROTO_GRP_H_ +#define _ICE_PROTO_GRP_H_ + +#define ICE_PROTO_COUNT_PER_GRP 8 +#define ICE_PROTO_GRP_TABLE_SIZE 192 +#define ICE_PROTO_GRP_ITEM_SIZE 22 + +#define ICE_PO_POL_S 0 +#define ICE_PO_POL_M BITMAP_MASK(1) +#define ICE_PO_PID_S 1 +#define ICE_PO_PID_M BITMAP_MASK(8) +#define ICE_PO_OFF_S 12 +#define ICE_PO_OFF_M BITMAP_MASK(10) + +struct ice_proto_off { + bool polarity; /* true: positive, false: nagtive */ + u8 proto_id; + u16 offset; +}; + +struct ice_proto_grp_item { + u16 idx; + struct ice_proto_off po[ICE_PROTO_COUNT_PER_GRP]; +}; + +void ice_proto_grp_dump(struct ice_hw *hw, struct ice_proto_grp_item *item); +struct ice_proto_grp_item *ice_proto_grp_table_get(struct ice_hw *hw); +#endif /* _ICE_PROTO_GRP_H_ */ From patchwork Mon Aug 21 08:14:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359249 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3FC94C6A for ; Mon, 21 Aug 2023 08:15:16 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 658E393 for ; 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a="685577567" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577567" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:15:11 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 08/15] ice: init flag redirect table for parser Date: Mon, 21 Aug 2023 16:14:31 +0800 Message-Id: <20230821081438.2937934-9-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Parse DDP section ICE_SID_RXPARSER_FLAG_REDIR into an array of ice_flag_rd_item. Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/ice_ddp.h | 1 + drivers/net/ethernet/intel/ice/ice_flg_rd.c | 50 +++++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_flg_rd.h | 23 ++++++++++ drivers/net/ethernet/intel/ice/ice_parser.c | 10 +++++ drivers/net/ethernet/intel/ice/ice_parser.h | 4 ++ 5 files changed, 88 insertions(+) create mode 100644 drivers/net/ethernet/intel/ice/ice_flg_rd.c create mode 100644 drivers/net/ethernet/intel/ice/ice_flg_rd.h diff --git a/drivers/net/ethernet/intel/ice/ice_ddp.h b/drivers/net/ethernet/intel/ice/ice_ddp.h index da5dfeed3b1f..45beed8b4415 100644 --- a/drivers/net/ethernet/intel/ice/ice_ddp.h +++ b/drivers/net/ethernet/intel/ice/ice_ddp.h @@ -261,6 +261,7 @@ struct ice_meta_sect { #define ICE_SID_CDID_KEY_BUILDER_PE 87 #define ICE_SID_CDID_REDIR_PE 88 +#define ICE_SID_RXPARSER_FLAG_REDIR 97 /* Label Metadata section IDs */ #define ICE_SID_LBL_FIRST 0x80000010 #define ICE_SID_LBL_RXPARSER_TMEM 0x80000018 diff --git a/drivers/net/ethernet/intel/ice/ice_flg_rd.c b/drivers/net/ethernet/intel/ice/ice_flg_rd.c new file mode 100644 index 000000000000..9d5d66d0c773 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_flg_rd.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2023 Intel Corporation */ + +#include "ice_common.h" +#include "ice_parser_util.h" + +/** + * ice_flg_rd_dump - dump a flag redirect item info + * @hw: pointer to the hardware structure + * @item: flag redirect item to dump + */ +void ice_flg_rd_dump(struct ice_hw *hw, struct ice_flg_rd_item *item) +{ + dev_info(ice_hw_to_dev(hw), "index = %d\n", item->idx); + dev_info(ice_hw_to_dev(hw), "expose = %d\n", item->expose); + dev_info(ice_hw_to_dev(hw), "intr_flg_id = %d\n", item->intr_flg_id); +} + +/** The function parses a 8 bits Flag Redirect Table entry with below format: + * BIT 0: Expose (rdi->expose) + * BIT 1-6: Internal Flag ID (rdi->intr_flg_id) + * BIT 7: reserved + */ +static void _ice_flg_rd_parse_item(struct ice_hw *hw, u16 idx, void *item, + void *data, int size) +{ + struct ice_flg_rd_item *rdi = item; + u8 d8 = *(u8 *)data; + + rdi->idx = idx; + rdi->expose = !!(d8 & ICE_RDI_EXP_M); + rdi->intr_flg_id = (u8)((d8 >> ICE_RDI_IFD_S) & ICE_RDI_IFD_M); + + if (hw->debug_mask & ICE_DBG_PARSER) + ice_flg_rd_dump(hw, rdi); +} + +/** + * ice_flg_rd_table_get - create a flag redirect table + * @hw: pointer to the hardware structure + */ +struct ice_flg_rd_item *ice_flg_rd_table_get(struct ice_hw *hw) +{ + return (struct ice_flg_rd_item *) + ice_parser_create_table(hw, ICE_SID_RXPARSER_FLAG_REDIR, + sizeof(struct ice_flg_rd_item), + ICE_FLG_RD_TABLE_SIZE, + ice_parser_sect_item_get, + _ice_flg_rd_parse_item, false); +} diff --git a/drivers/net/ethernet/intel/ice/ice_flg_rd.h b/drivers/net/ethernet/intel/ice/ice_flg_rd.h new file mode 100644 index 000000000000..b3b4fd7a9002 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_flg_rd.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2023 Intel Corporation */ + +#ifndef _ICE_FLG_RD_H_ +#define _ICE_FLG_RD_H_ + +#define ICE_FLG_RD_TABLE_SIZE 64 +#define ICE_FLG_RDT_SIZE 64 + +#define ICE_RDI_EXP_S 0 +#define ICE_RDI_EXP_M BITMAP_MASK(1) +#define ICE_RDI_IFD_S 1 +#define ICE_RDI_IFD_M BITMAP_MASK(6) + +struct ice_flg_rd_item { + u16 idx; + bool expose; + u8 intr_flg_id; +}; + +void ice_flg_rd_dump(struct ice_hw *hw, struct ice_flg_rd_item *item); +struct ice_flg_rd_item *ice_flg_rd_table_get(struct ice_hw *hw); +#endif /* _ICE_FLG_RD_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c index 4da2d4c21bab..3c3f7d6bea52 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.c +++ b/drivers/net/ethernet/intel/ice/ice_parser.c @@ -68,6 +68,9 @@ void *ice_parser_sect_item_get(u32 sect_type, void *section, case ICE_SID_RXPARSER_PROTO_GRP: size = ICE_SID_RXPARSER_PROTO_GRP_ENTRY_SIZE; break; + case ICE_SID_RXPARSER_FLAG_REDIR: + size = ICE_SID_RXPARSER_FLAG_REDIR_ENTRY_SIZE; + break; default: return NULL; } @@ -220,6 +223,12 @@ int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr) goto err; } + p->flg_rd_table = ice_flg_rd_table_get(hw); + if (!p->flg_rd_table) { + status = -EINVAL; + goto err; + } + *psr = p; return 0; err: @@ -244,6 +253,7 @@ void ice_parser_destroy(struct ice_parser *psr) devm_kfree(ice_hw_to_dev(psr->hw), psr->ptype_mk_tcam_table); devm_kfree(ice_hw_to_dev(psr->hw), psr->mk_grp_table); devm_kfree(ice_hw_to_dev(psr->hw), psr->proto_grp_table); + devm_kfree(ice_hw_to_dev(psr->hw), psr->flg_rd_table); devm_kfree(ice_hw_to_dev(psr->hw), psr); } diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h index 4038833450f2..62123788e0a2 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.h +++ b/drivers/net/ethernet/intel/ice/ice_parser.h @@ -11,6 +11,7 @@ #include "ice_ptype_mk.h" #include "ice_mk_grp.h" #include "ice_proto_grp.h" +#include "ice_flg_rd.h" #define ICE_SEC_DATA_OFFSET 4 #define ICE_SID_RXPARSER_IMEM_ENTRY_SIZE 48 @@ -23,6 +24,7 @@ #define ICE_SID_RXPARSER_MARKER_TYPE_ENTRY_SIZE 24 #define ICE_SID_RXPARSER_MARKER_GRP_ENTRY_SIZE 8 #define ICE_SID_RXPARSER_PROTO_GRP_ENTRY_SIZE 24 +#define ICE_SID_RXPARSER_FLAG_REDIR_ENTRY_SIZE 1 #define ICE_SEC_LBL_DATA_OFFSET 2 #define ICE_SID_LBL_ENTRY_SIZE 66 @@ -52,6 +54,8 @@ struct ice_parser { struct ice_mk_grp_item *mk_grp_table; /* load data from section ICE_SID_RXPARSER_PROTO_GRP */ struct ice_proto_grp_item *proto_grp_table; + /* load data from section ICE_SID_RXPARSER_FLAG_REDIR */ + struct ice_flg_rd_item *flg_rd_table; }; int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr); From patchwork Mon Aug 21 08:14:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359250 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2DB54C6A for ; Mon, 21 Aug 2023 08:15:20 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A2D8BD for ; Mon, 21 Aug 2023 01:15:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692605718; x=1724141718; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JBW2knGd5Q4Qx4PH2OazV1jmLljLNCUirQBECMiZzs8=; b=hdO8Bjq1E0V8iCt6TOOARK2n4RmPTc0+ah9glFP9IybWPRcKtqy0wH5h 6onHyJpw1rUtaa0AGfwvrEAAT/zOLm3mxPPxTlJW7F/myxE//J+thZatq cYcIIROo8kxK/SVtJXpN78LPqh3FlFCY2fTSZ1fiYQI+/Ukgo0fnVDoPf HjJ2Nkc0MwSnsYvK4sZiQPZc6qjmX7n+dHZoN8oShQ0bBDq0eU9beWCOi oQ4NfC6ZDDhX+UIgPzpLhNErKJJvmm9fWETkq52dYyNOIeeBbEbjBr0Pz ct8HcmlPgKPoX4zGfHGrWPsh2qkzsXLBGd8ZGdYrWW+PKszcHlgb3qB4X Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="376280477" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="376280477" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2023 01:15:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="685577575" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577575" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:15:14 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 09/15] ice: init XLT key builder for parser Date: Mon, 21 Aug 2023 16:14:32 +0800 Message-Id: <20230821081438.2937934-10-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Parse below DDP section into struct ice_xlt_kb: ICE_SID_XLT_KEY_BUILDER_SW ICE_SID_XLT_KEY_BUILDER_ACL ICE_SID_XLT_KEY_BUILDER_FD ICE_SID_XLT_KEY_BUILDER_RSS Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/ice_parser.c | 28 +++ drivers/net/ethernet/intel/ice/ice_parser.h | 9 + drivers/net/ethernet/intel/ice/ice_xlt_kb.c | 235 ++++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_xlt_kb.h | 79 +++++++ 4 files changed, 351 insertions(+) create mode 100644 drivers/net/ethernet/intel/ice/ice_xlt_kb.c create mode 100644 drivers/net/ethernet/intel/ice/ice_xlt_kb.h diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c index 3c3f7d6bea52..6499bb774667 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.c +++ b/drivers/net/ethernet/intel/ice/ice_parser.c @@ -229,6 +229,30 @@ int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr) goto err; } + p->xlt_kb_sw = ice_xlt_kb_get_sw(hw); + if (!p->xlt_kb_sw) { + status = -EINVAL; + goto err; + } + + p->xlt_kb_acl = ice_xlt_kb_get_acl(hw); + if (!p->xlt_kb_acl) { + status = -EINVAL; + goto err; + } + + p->xlt_kb_fd = ice_xlt_kb_get_fd(hw); + if (!p->xlt_kb_fd) { + status = -EINVAL; + goto err; + } + + p->xlt_kb_rss = ice_xlt_kb_get_rss(hw); + if (!p->xlt_kb_rss) { + status = -EINVAL; + goto err; + } + *psr = p; return 0; err: @@ -254,6 +278,10 @@ void ice_parser_destroy(struct ice_parser *psr) devm_kfree(ice_hw_to_dev(psr->hw), psr->mk_grp_table); devm_kfree(ice_hw_to_dev(psr->hw), psr->proto_grp_table); devm_kfree(ice_hw_to_dev(psr->hw), psr->flg_rd_table); + devm_kfree(ice_hw_to_dev(psr->hw), psr->xlt_kb_sw); + devm_kfree(ice_hw_to_dev(psr->hw), psr->xlt_kb_acl); + devm_kfree(ice_hw_to_dev(psr->hw), psr->xlt_kb_fd); + devm_kfree(ice_hw_to_dev(psr->hw), psr->xlt_kb_rss); devm_kfree(ice_hw_to_dev(psr->hw), psr); } diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h index 62123788e0a2..ca71ef4f50f5 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.h +++ b/drivers/net/ethernet/intel/ice/ice_parser.h @@ -12,6 +12,7 @@ #include "ice_mk_grp.h" #include "ice_proto_grp.h" #include "ice_flg_rd.h" +#include "ice_xlt_kb.h" #define ICE_SEC_DATA_OFFSET 4 #define ICE_SID_RXPARSER_IMEM_ENTRY_SIZE 48 @@ -56,6 +57,14 @@ struct ice_parser { struct ice_proto_grp_item *proto_grp_table; /* load data from section ICE_SID_RXPARSER_FLAG_REDIR */ struct ice_flg_rd_item *flg_rd_table; + /* load data from section ICE_SID_XLT_KEY_BUILDER_SW */ + struct ice_xlt_kb *xlt_kb_sw; + /* load data from section ICE_SID_XLT_KEY_BUILDER_ACL */ + struct ice_xlt_kb *xlt_kb_acl; + /* load data from section ICE_SID_XLT_KEY_BUILDER_FD */ + struct ice_xlt_kb *xlt_kb_fd; + /* load data from section ICE_SID_XLT_KEY_BUILDER_RSS */ + struct ice_xlt_kb *xlt_kb_rss; }; int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr); diff --git a/drivers/net/ethernet/intel/ice/ice_xlt_kb.c b/drivers/net/ethernet/intel/ice/ice_xlt_kb.c new file mode 100644 index 000000000000..4fca88fb7d77 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_xlt_kb.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2023 Intel Corporation */ + +#include "ice_common.h" + +static void _ice_xlt_kb_entry_dump(struct ice_hw *hw, + struct ice_xlt_kb_entry *entry, int idx) +{ + int i; + + dev_info(ice_hw_to_dev(hw), "key builder entry %d\n", idx); + dev_info(ice_hw_to_dev(hw), "\txlt1_ad_sel = %d\n", + entry->xlt1_ad_sel); + dev_info(ice_hw_to_dev(hw), "\txlt2_ad_sel = %d\n", + entry->xlt2_ad_sel); + + for (i = 0; i < ICE_XLT_KB_FLAG0_14_CNT; i++) + dev_info(ice_hw_to_dev(hw), "\tflg%d_sel = %d\n", i, + entry->flg0_14_sel[i]); + + dev_info(ice_hw_to_dev(hw), "\txlt1_md_sel = %d\n", + entry->xlt1_md_sel); + dev_info(ice_hw_to_dev(hw), "\txlt2_md_sel = %d\n", + entry->xlt2_md_sel); +} + +/** + * ice_xlt_kb_dump - dump a xlt key build info + * @hw: pointer to the hardware structure + * @kb: key build to dump + */ +void ice_xlt_kb_dump(struct ice_hw *hw, struct ice_xlt_kb *kb) +{ + int i; + + dev_info(ice_hw_to_dev(hw), "xlt1_pm = %d\n", kb->xlt1_pm); + dev_info(ice_hw_to_dev(hw), "xlt2_pm = %d\n", kb->xlt2_pm); + dev_info(ice_hw_to_dev(hw), "prof_id_pm = %d\n", kb->prof_id_pm); + dev_info(ice_hw_to_dev(hw), "flag15 lo = 0x%08x\n", (u32)kb->flag15); + dev_info(ice_hw_to_dev(hw), "flag15 hi = 0x%08x\n", + (u32)(kb->flag15 >> (sizeof(u32) * BITS_PER_BYTE))); + + for (i = 0; i < ICE_XLT_KB_TBL_CNT; i++) + _ice_xlt_kb_entry_dump(hw, &kb->entries[i], i); +} + +/** The function parses a 192 bits XLT Key Builder entry with below format: + * BIT 0-31: reserved + * BIT 32-34: XLT1 AdSel (entry->xlt1_ad_sel) + * BIT 35-37: XLT2 AdSel (entry->xlt2_ad_sel) + * BIT 38-46: Flag 0 Select (entry->flg0_14_sel[0]) + * BIT 47-55: Flag 1 Select (entry->flg0_14_sel[1]) + * BIT 56-64: Flag 2 Select (entry->flg0_14_sel[2]) + * BIT 65-73: Flag 3 Select (entry->flg0_14_sel[3]) + * BIT 74-82: Flag 4 Select (entry->flg0_14_sel[4]) + * BIT 83-91: Flag 5 Select (entry->flg0_14_sel[5]) + * BIT 92-100: Flag 6 Select (entry->flg0_14_sel[6]) + * BIT 101-109:Flag 7 Select (entry->flg0_14_sel[7]) + * BIT 110-118:Flag 8 Select (entry->flg0_14_sel[8]) + * BIT 119-127:Flag 9 Select (entry->flg0_14_sel[9]) + * BIT 128-136:Flag 10 Select (entry->flg0_14_sel[10]) + * BIT 137-145:Flag 11 Select (entry->flg0_14_sel[11]) + * BIT 146-154:Flag 12 Select (entry->flg0_14_sel[12]) + * BIT 155-163:Flag 13 Select (entry->flg0_14_sel[13]) + * BIT 164-172:Flag 14 Select (entry->flg0_14_sel[14]) + * BIT 173-181:reserved + * BIT 182-186:XLT1 MdSel (entry->xlt1_md_sel) + * BIT 187-191:XLT2 MdSel (entry->xlt2_md_sel) + */ +static void _ice_kb_entry_init(struct ice_xlt_kb_entry *entry, u8 *data) +{ + u8 idd, off, i; + u64 d64; + + idd = ICE_XLT_KB_X1AS_S / BITS_PER_BYTE; + off = ICE_XLT_KB_X1AS_S % BITS_PER_BYTE; + d64 = *((u64 *)&data[idd]) >> off; + + off = ICE_XLT_KB_X1AS_S - ICE_XLT_KB_X1AS_S; + entry->xlt1_ad_sel = (u8)((d64 >> off) & ICE_XLT_KB_X1AS_M); + off = ICE_XLT_KB_X2AS_S - ICE_XLT_KB_X1AS_S; + entry->xlt2_ad_sel = (u8)((d64 >> off) & ICE_XLT_KB_X2AS_M); + + i = 0; + off = ICE_XLT_KB_FL00_S - ICE_XLT_KB_X1AS_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL00_M); + i++; + off = ICE_XLT_KB_FL01_S - ICE_XLT_KB_X1AS_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL01_M); + i++; + off = ICE_XLT_KB_FL02_S - ICE_XLT_KB_X1AS_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL02_M); + i++; + off = ICE_XLT_KB_FL03_S - ICE_XLT_KB_X1AS_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL03_M); + i++; + off = ICE_XLT_KB_FL04_S - ICE_XLT_KB_X1AS_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL04_M); + i++; + off = ICE_XLT_KB_FL05_S - ICE_XLT_KB_X1AS_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL05_M); + + idd = ICE_XLT_KB_FL06_S / BITS_PER_BYTE; + off = ICE_XLT_KB_FL06_S % BITS_PER_BYTE; + d64 = *((u64 *)&data[idd]) >> off; + + i++; + off = ICE_XLT_KB_FL06_S - ICE_XLT_KB_FL06_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL06_M); + i++; + off = ICE_XLT_KB_FL07_S - ICE_XLT_KB_FL06_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL07_M); + i++; + off = ICE_XLT_KB_FL08_S - ICE_XLT_KB_FL06_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL08_M); + i++; + off = ICE_XLT_KB_FL09_S - ICE_XLT_KB_FL06_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL09_M); + i++; + off = ICE_XLT_KB_FL10_S - ICE_XLT_KB_FL06_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL10_M); + i++; + off = ICE_XLT_KB_FL11_S - ICE_XLT_KB_FL06_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL11_M); + + idd = ICE_XLT_KB_FL12_S / BITS_PER_BYTE; + off = ICE_XLT_KB_FL12_S % BITS_PER_BYTE; + d64 = *((u64 *)&data[idd]) >> off; + + i++; + off = ICE_XLT_KB_FL12_S - ICE_XLT_KB_FL12_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL12_M); + i++; + off = ICE_XLT_KB_FL13_S - ICE_XLT_KB_FL12_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL13_M); + i++; + off = ICE_XLT_KB_FL14_S - ICE_XLT_KB_FL12_S; + entry->flg0_14_sel[i] = (u16)((d64 >> off) & ICE_XLT_KB_FL14_M); + + off = ICE_XLT_KB_X1MS_S - ICE_XLT_KB_FL12_S; + entry->xlt1_md_sel = (u8)((d64 >> off) & ICE_XLT_KB_X1MS_M); + off = ICE_XLT_KB_X2MS_S - ICE_XLT_KB_FL12_S; + entry->xlt2_md_sel = (u8)((d64 >> off) & ICE_XLT_KB_X2MS_M); +} + +/** The function parses a 204 bytes XLT Key Build Table with below format: + * byte 0: XLT1 Partition Mode (kb->xlt1_pm) + * byte 1: XLT2 Partition Mode (kb->xlt2_pm) + * byte 2: Profile ID Partition Mode (kb->prof_id_pm) + * byte 3: reserved + * byte 4-11: Flag15 Mask (kb->flag15) + * byte 12-203:8 Key Build entries (kb->entries) + */ +static void _ice_parse_kb_data(struct ice_hw *hw, struct ice_xlt_kb *kb, + void *data) +{ + u8 *buf = data; + int i; + + kb->xlt1_pm = buf[ICE_XLT_KB_X1PM_OFF]; + kb->xlt2_pm = buf[ICE_XLT_KB_X2PM_OFF]; + kb->prof_id_pm = buf[ICE_XLT_KB_PIPM_OFF]; + + kb->flag15 = *(u64 *)&buf[ICE_XLT_KB_FL15_OFF]; + for (i = 0; i < ICE_XLT_KB_TBL_CNT; i++) + _ice_kb_entry_init(&kb->entries[i], + &buf[ICE_XLT_KB_TBL_OFF + + i * ICE_XLT_KB_TBL_ENTRY_SIZE]); + + if (hw->debug_mask & ICE_DBG_PARSER) + ice_xlt_kb_dump(hw, kb); +} + +static struct ice_xlt_kb *_ice_xlt_kb_get(struct ice_hw *hw, u32 sect_type) +{ + struct ice_seg *seg = hw->seg; + struct ice_pkg_enum state; + struct ice_xlt_kb *kb; + void *data; + + if (!seg) + return NULL; + + kb = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*kb), GFP_KERNEL); + if (!kb) + return NULL; + + memset(&state, 0, sizeof(state)); + data = ice_pkg_enum_section(seg, &state, sect_type); + if (!data) { + ice_debug(hw, ICE_DBG_PARSER, "failed to find section type %d.\n", + sect_type); + return NULL; + } + + _ice_parse_kb_data(hw, kb, data); + + return kb; +} + +/** + * ice_xlt_kb_get_sw - create switch xlt key build + * @hw: pointer to the hardware structure + */ +struct ice_xlt_kb *ice_xlt_kb_get_sw(struct ice_hw *hw) +{ + return _ice_xlt_kb_get(hw, ICE_SID_XLT_KEY_BUILDER_SW); +} + +/** + * ice_xlt_kb_get_acl - create acl xlt key build + * @hw: pointer to the hardware structure + */ +struct ice_xlt_kb *ice_xlt_kb_get_acl(struct ice_hw *hw) +{ + return _ice_xlt_kb_get(hw, ICE_SID_XLT_KEY_BUILDER_ACL); +} + +/** + * ice_xlt_kb_get_fd - create fdir xlt key build + * @hw: pointer to the hardware structure + */ +struct ice_xlt_kb *ice_xlt_kb_get_fd(struct ice_hw *hw) +{ + return _ice_xlt_kb_get(hw, ICE_SID_XLT_KEY_BUILDER_FD); +} + +/** + * ice_xlt_kb_get_rss - create rss xlt key build + * @hw: pointer to the hardware structure + */ +struct ice_xlt_kb *ice_xlt_kb_get_rss(struct ice_hw *hw) +{ + return _ice_xlt_kb_get(hw, ICE_SID_XLT_KEY_BUILDER_RSS); +} diff --git a/drivers/net/ethernet/intel/ice/ice_xlt_kb.h b/drivers/net/ethernet/intel/ice/ice_xlt_kb.h new file mode 100644 index 000000000000..020f96bfdbe8 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_xlt_kb.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2023 Intel Corporation */ + +#ifndef _ICE_XLT_KB_H_ +#define _ICE_XLT_KB_H_ + +#define ICE_XLT_KB_FLAG0_14_CNT 15 + +#define ICE_XLT_KB_FLAG_M BITMAP_MASK(9) +#define ICE_XLT_KB_X1AS_S 32 +#define ICE_XLT_KB_X1AS_M BITMAP_MASK(3) +#define ICE_XLT_KB_X2AS_S 35 +#define ICE_XLT_KB_X2AS_M BITMAP_MASK(3) +#define ICE_XLT_KB_FL00_S 38 +#define ICE_XLT_KB_FL00_M BITMAP_MASK(9) +#define ICE_XLT_KB_FL01_S 47 +#define ICE_XLT_KB_FL01_M BITMAP_MASK(9) +#define ICE_XLT_KB_FL02_S 56 +#define ICE_XLT_KB_FL02_M BITMAP_MASK(9) +#define ICE_XLT_KB_FL03_S 65 +#define ICE_XLT_KB_FL03_M BITMAP_MASK(9) +#define ICE_XLT_KB_FL04_S 74 +#define ICE_XLT_KB_FL04_M BITMAP_MASK(9) +#define ICE_XLT_KB_FL05_S 83 +#define ICE_XLT_KB_FL05_M BITMAP_MASK(9) +#define ICE_XLT_KB_FL06_S 92 +#define ICE_XLT_KB_FL06_M BITMAP_MASK(9) +#define ICE_XLT_KB_FL07_S 101 +#define ICE_XLT_KB_FL07_M BITMAP_MASK(9) +#define ICE_XLT_KB_FL08_S 110 +#define ICE_XLT_KB_FL08_M BITMAP_MASK(9) +#define ICE_XLT_KB_FL09_S 119 +#define ICE_XLT_KB_FL09_M BITMAP_MASK(9) +#define ICE_XLT_KB_FL10_S 128 +#define ICE_XLT_KB_FL10_M BITMAP_MASK(9) +#define ICE_XLT_KB_FL11_S 137 +#define ICE_XLT_KB_FL11_M BITMAP_MASK(9) +#define ICE_XLT_KB_FL12_S 146 +#define ICE_XLT_KB_FL12_M BITMAP_MASK(9) +#define ICE_XLT_KB_FL13_S 155 +#define ICE_XLT_KB_FL13_M BITMAP_MASK(9) +#define ICE_XLT_KB_FL14_S 164 +#define ICE_XLT_KB_FL14_M BITMAP_MASK(9) +#define ICE_XLT_KB_X1MS_S 182 +#define ICE_XLT_KB_X1MS_M BITMAP_MASK(5) +#define ICE_XLT_KB_X2MS_S 187 +#define ICE_XLT_KB_X2MS_M BITMAP_MASK(5) + +struct ice_xlt_kb_entry { + u8 xlt1_ad_sel; + u8 xlt2_ad_sel; + u16 flg0_14_sel[ICE_XLT_KB_FLAG0_14_CNT]; + u8 xlt1_md_sel; + u8 xlt2_md_sel; +}; + +#define ICE_XLT_KB_X1PM_OFF 0 +#define ICE_XLT_KB_X2PM_OFF 1 +#define ICE_XLT_KB_PIPM_OFF 2 +#define ICE_XLT_KB_FL15_OFF 4 +#define ICE_XLT_KB_TBL_CNT 8 +#define ICE_XLT_KB_TBL_OFF 12 +#define ICE_XLT_KB_TBL_ENTRY_SIZE 24 + +struct ice_xlt_kb { + u8 xlt1_pm; + u8 xlt2_pm; + u8 prof_id_pm; + u64 flag15; + + struct ice_xlt_kb_entry entries[ICE_XLT_KB_TBL_CNT]; +}; + +void ice_xlt_kb_dump(struct ice_hw *hw, struct ice_xlt_kb *kb); +struct ice_xlt_kb *ice_xlt_kb_get_sw(struct ice_hw *hw); +struct ice_xlt_kb *ice_xlt_kb_get_acl(struct ice_hw *hw); +struct ice_xlt_kb *ice_xlt_kb_get_fd(struct ice_hw *hw); +struct ice_xlt_kb *ice_xlt_kb_get_rss(struct ice_hw *hw); +#endif /* _ICE_XLT_KB_H */ From patchwork Mon Aug 21 08:14:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359251 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 019E64C6A for ; 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21 Aug 2023 01:15:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="685577587" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577587" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:15:17 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 10/15] ice: add parser runtime skeleton Date: Mon, 21 Aug 2023 16:14:33 +0800 Message-Id: <20230821081438.2937934-11-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Add parser runtime data struct ice_parser_rt. Add below APIs for parser runtime preparation: - ice_parser_rt_reset - ice_parser_rt_pkt_buf_set Add below API skeleton for parser runtime execution: - ice_parser_rt_execute Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/ice_parser.c | 40 ++++++++ drivers/net/ethernet/intel/ice/ice_parser.h | 28 ++++++ .../net/ethernet/intel/ice/ice_parser_rt.c | 92 +++++++++++++++++++ .../net/ethernet/intel/ice/ice_parser_rt.h | 39 ++++++++ 4 files changed, 199 insertions(+) create mode 100644 drivers/net/ethernet/intel/ice/ice_parser_rt.c create mode 100644 drivers/net/ethernet/intel/ice/ice_parser_rt.h diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c index 6499bb774667..1bd1417e32c6 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.c +++ b/drivers/net/ethernet/intel/ice/ice_parser.c @@ -156,6 +156,7 @@ int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr) return -ENOMEM; p->hw = hw; + p->rt.psr = p; p->imem_table = ice_imem_table_get(hw); if (!p->imem_table) { @@ -285,3 +286,42 @@ void ice_parser_destroy(struct ice_parser *psr) devm_kfree(ice_hw_to_dev(psr->hw), psr); } + +/** + * ice_parser_run - parse on a packet in binary and return the result + * @psr: pointer to a parser instance + * @pkt_buf: packet data + * @pkt_len: packet length + * @rslt: input/output parameter to save parser result. + */ +int ice_parser_run(struct ice_parser *psr, const u8 *pkt_buf, + int pkt_len, struct ice_parser_result *rslt) +{ + ice_parser_rt_reset(&psr->rt); + ice_parser_rt_pktbuf_set(&psr->rt, pkt_buf, pkt_len); + + return ice_parser_rt_execute(&psr->rt, rslt); +} + +/** + * ice_parser_result_dump - dump a parser result info + * @hw: pointer to the hardware structure + * @rslt: parser result info to dump + */ +void ice_parser_result_dump(struct ice_hw *hw, struct ice_parser_result *rslt) +{ + int i; + + dev_info(ice_hw_to_dev(hw), "ptype = %d\n", rslt->ptype); + for (i = 0; i < rslt->po_num; i++) + dev_info(ice_hw_to_dev(hw), "proto = %d, offset = %d\n", + rslt->po[i].proto_id, rslt->po[i].offset); + + dev_info(ice_hw_to_dev(hw), "flags_psr = 0x%016llx\n", + (unsigned long long)rslt->flags_psr); + dev_info(ice_hw_to_dev(hw), "flags_pkt = 0x%016llx\n", + (unsigned long long)rslt->flags_pkt); + dev_info(ice_hw_to_dev(hw), "flags_sw = 0x%04x\n", rslt->flags_sw); + dev_info(ice_hw_to_dev(hw), "flags_fd = 0x%04x\n", rslt->flags_fd); + dev_info(ice_hw_to_dev(hw), "flags_rss = 0x%04x\n", rslt->flags_rss); +} diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h index ca71ef4f50f5..5f98f3031294 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.h +++ b/drivers/net/ethernet/intel/ice/ice_parser.h @@ -13,6 +13,7 @@ #include "ice_proto_grp.h" #include "ice_flg_rd.h" #include "ice_xlt_kb.h" +#include "ice_parser_rt.h" #define ICE_SEC_DATA_OFFSET 4 #define ICE_SID_RXPARSER_IMEM_ENTRY_SIZE 48 @@ -30,6 +31,8 @@ #define ICE_SEC_LBL_DATA_OFFSET 2 #define ICE_SID_LBL_ENTRY_SIZE 66 +#define ICE_PARSER_PROTO_OFF_PAIR_SIZE 16 + struct ice_parser { struct ice_hw *hw; /* pointer to the hardware structure */ @@ -65,8 +68,33 @@ struct ice_parser { struct ice_xlt_kb *xlt_kb_fd; /* load data from section ICE_SID_XLT_KEY_BUILDER_RSS */ struct ice_xlt_kb *xlt_kb_rss; + struct ice_parser_rt rt; /* parser runtime */ }; int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr); void ice_parser_destroy(struct ice_parser *psr); + +struct ice_parser_proto_off { + u8 proto_id; /* hardware protocol ID */ + u16 offset; /* offset from the start of the protocol header */ +}; + +#define ICE_PARSER_FLAG_PSR_SIZE 8 + +struct ice_parser_result { + u16 ptype; /* 16 bits hardware PTYPE */ + /* array of protocol and header offset pairs */ + struct ice_parser_proto_off po[ICE_PARSER_PROTO_OFF_PAIR_SIZE]; + int po_num; /* # of protocol-offset pairs must <= 16 */ + u64 flags_psr; /* 64 bits parser flags */ + u64 flags_pkt; /* 64 bits packet flags */ + u16 flags_sw; /* 16 bits key builder flag for SW */ + u16 flags_acl; /* 16 bits key builder flag for ACL */ + u16 flags_fd; /* 16 bits key builder flag for FD */ + u16 flags_rss; /* 16 bits key builder flag for RSS */ +}; + +int ice_parser_run(struct ice_parser *psr, const u8 *pkt_buf, + int pkt_len, struct ice_parser_result *rslt); +void ice_parser_result_dump(struct ice_hw *hw, struct ice_parser_result *rslt); #endif /* _ICE_PARSER_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_parser_rt.c b/drivers/net/ethernet/intel/ice/ice_parser_rt.c new file mode 100644 index 000000000000..a6644f4b3324 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_parser_rt.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2023 Intel Corporation */ + +#include "ice_common.h" + +static void _ice_rt_tsr_set(struct ice_parser_rt *rt, u16 tsr) +{ + rt->gpr[ICE_GPR_TSR_IDX] = tsr; +} + +static void _ice_rt_ho_set(struct ice_parser_rt *rt, u16 ho) +{ + rt->gpr[ICE_GPR_HO_IDX] = ho; + memcpy(&rt->gpr[ICE_GPR_HV_IDX], &rt->pkt_buf[ho], ICE_GPR_HV_SIZE); +} + +static void _ice_rt_np_set(struct ice_parser_rt *rt, u16 pc) +{ + rt->gpr[ICE_GPR_NP_IDX] = pc; +} + +static void _ice_rt_nn_set(struct ice_parser_rt *rt, u16 node) +{ + rt->gpr[ICE_GPR_NN_IDX] = node; +} + +static void _ice_rt_flag_set(struct ice_parser_rt *rt, int idx, bool val) +{ + int y = idx / ICE_GPR_FLG_SIZE; + int x = idx % ICE_GPR_FLG_SIZE; + + if (val) + rt->gpr[ICE_GPR_FLG_IDX + y] |= (u16)BIT(x); +} + +/** + * ice_parser_rt_reset - reset the parser runtime + * @rt: pointer to the parser runtime + */ +void ice_parser_rt_reset(struct ice_parser_rt *rt) +{ + struct ice_parser *psr = rt->psr; + struct ice_metainit_item *mi = &psr->mi_table[0]; + int i; + + memset(rt, 0, sizeof(*rt)); + + /* TSR: TCAM Search Register */ + _ice_rt_tsr_set(rt, mi->tsr); + /* HO: Next Parsing Cycle Header Offset */ + _ice_rt_ho_set(rt, mi->ho); + /* NP: Next Parsing Cycle */ + _ice_rt_np_set(rt, mi->pc); + /* NN: Next Parsing Cycle Node ID */ + _ice_rt_nn_set(rt, mi->pg_rn); + + rt->psr = psr; + + for (i = 0; i < ICE_PARSER_FLG_NUM; i++) { + if ((mi->flags & BIT(i)) != 0ul) + _ice_rt_flag_set(rt, i, true); + } +} + +/** + * ice_parser_rt_pktbuf_set - set a packet into parser runtime + * @rt: pointer to the parser runtime + * @pkt_buf: buffer with packet data + * @pkt_len: packet buffer length + */ +void ice_parser_rt_pktbuf_set(struct ice_parser_rt *rt, const u8 *pkt_buf, + int pkt_len) +{ + int len = min(ICE_PARSER_MAX_PKT_LEN, pkt_len); + u16 ho = rt->gpr[ICE_GPR_HO_IDX]; + + memcpy(rt->pkt_buf, pkt_buf, len); + rt->pkt_len = pkt_len; + + memcpy(&rt->gpr[ICE_GPR_HV_IDX], &rt->pkt_buf[ho], ICE_GPR_HV_SIZE); +} + +/** + * ice_parser_rt_execute - parser execution routine + * @rt: pointer to the parser runtime + * @rslt: input/output parameter to save parser result + */ +int ice_parser_rt_execute(struct ice_parser_rt *rt, + struct ice_parser_result *rslt) +{ + return ICE_ERR_NOT_IMPL; +} diff --git a/drivers/net/ethernet/intel/ice/ice_parser_rt.h b/drivers/net/ethernet/intel/ice/ice_parser_rt.h new file mode 100644 index 000000000000..dadcb8791430 --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_parser_rt.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2023 Intel Corporation */ + +#ifndef _ICE_PARSER_RT_H_ +#define _ICE_PARSER_RT_H_ + +#define ICE_GPR_HV_IDX 64 +#define ICE_GPR_HV_SIZE 32 +#define ICE_GPR_ERR_IDX 84 +#define ICE_GPR_FLG_IDX 104 +#define ICE_GPR_FLG_SIZE 16 + +#define ICE_GPR_TSR_IDX 108 +#define ICE_GPR_NN_IDX 109 +#define ICE_GPR_HO_IDX 110 +#define ICE_GPR_NP_IDX 111 + +struct ice_parser_ctx; + +#define ICE_PARSER_MAX_PKT_LEN 504 +#define ICE_PARSER_PKT_REV 32 +#define ICE_PARSER_GPR_NUM 128 + +struct ice_parser_rt { + struct ice_parser *psr; + u16 gpr[ICE_PARSER_GPR_NUM]; + u8 pkt_buf[ICE_PARSER_MAX_PKT_LEN + ICE_PARSER_PKT_REV]; + u16 pkt_len; + u16 po; +}; + +void ice_parser_rt_reset(struct ice_parser_rt *rt); +void ice_parser_rt_pktbuf_set(struct ice_parser_rt *rt, const u8 *pkt_buf, + int pkt_len); + +struct ice_parser_result; +int ice_parser_rt_execute(struct ice_parser_rt *rt, + struct ice_parser_result *rslt); +#endif /* _ICE_PARSER_RT_H_ */ From patchwork Mon Aug 21 08:14:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359252 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18E50524D for ; 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21 Aug 2023 01:15:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="685577594" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577594" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:15:20 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 11/15] ice: add internal help functions Date: Mon, 21 Aug 2023 16:14:34 +0800 Message-Id: <20230821081438.2937934-12-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Add below internal helper function: - [ice_bst_tcam_match]: to perform ternary match on boost TCAM. - [ice_pg_cam_match]: to perform parse graph key match in cam table. - [ice_pg_nm_cam_match]: to perform parse graph key no match in cam table. - [ice_ptype_mk_tcam_match]: to perform ptype markers match in tcam table. - [ice_flg_redirect]: to redirect parser flags to packet flags. - [ice_xlt_kb_flg_get]: to aggregate 64 bit packet flag into 16 bit key builder flags. Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/ice_bst_tcam.c | 23 ++++++ drivers/net/ethernet/intel/ice/ice_bst_tcam.h | 3 + drivers/net/ethernet/intel/ice/ice_flg_rd.c | 23 ++++++ drivers/net/ethernet/intel/ice/ice_flg_rd.h | 1 + drivers/net/ethernet/intel/ice/ice_parser.h | 1 + drivers/net/ethernet/intel/ice/ice_pg_cam.c | 76 +++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_pg_cam.h | 6 ++ drivers/net/ethernet/intel/ice/ice_ptype_mk.c | 22 ++++++ drivers/net/ethernet/intel/ice/ice_ptype_mk.h | 3 + drivers/net/ethernet/intel/ice/ice_tmatch.h | 40 ++++++++++ drivers/net/ethernet/intel/ice/ice_xlt_kb.c | 27 +++++++ drivers/net/ethernet/intel/ice/ice_xlt_kb.h | 1 + 12 files changed, 226 insertions(+) create mode 100644 drivers/net/ethernet/intel/ice/ice_tmatch.h diff --git a/drivers/net/ethernet/intel/ice/ice_bst_tcam.c b/drivers/net/ethernet/intel/ice/ice_bst_tcam.c index 9f232db164d9..f31023da0a41 100644 --- a/drivers/net/ethernet/intel/ice/ice_bst_tcam.c +++ b/drivers/net/ethernet/intel/ice/ice_bst_tcam.c @@ -271,3 +271,26 @@ struct ice_lbl_item *ice_bst_lbl_table_get(struct ice_hw *hw) ice_parser_sect_item_get, _ice_parse_lbl_item, true); } + +/** + * ice_bst_tcam_match - match a pattern on the boost tcam table + * @tcam_table: boost tcam table to search + * @pat: pattern to match + */ +struct ice_bst_tcam_item * +ice_bst_tcam_match(struct ice_bst_tcam_item *tcam_table, u8 *pat) +{ + int i; + + for (i = 0; i < ICE_BST_TCAM_TABLE_SIZE; i++) { + struct ice_bst_tcam_item *item = &tcam_table[i]; + + if (item->hit_idx_grp == 0) + continue; + if (ice_ternary_match(item->key, item->key_inv, pat, + ICE_BST_TCAM_KEY_SIZE)) + return item; + } + + return NULL; +} diff --git a/drivers/net/ethernet/intel/ice/ice_bst_tcam.h b/drivers/net/ethernet/intel/ice/ice_bst_tcam.h index b1b1dc224d70..960c8ff09171 100644 --- a/drivers/net/ethernet/intel/ice/ice_bst_tcam.h +++ b/drivers/net/ethernet/intel/ice/ice_bst_tcam.h @@ -42,4 +42,7 @@ void ice_bst_tcam_dump(struct ice_hw *hw, struct ice_bst_tcam_item *item); struct ice_bst_tcam_item *ice_bst_tcam_table_get(struct ice_hw *hw); struct ice_lbl_item *ice_bst_lbl_table_get(struct ice_hw *hw); + +struct ice_bst_tcam_item * +ice_bst_tcam_match(struct ice_bst_tcam_item *tcam_table, u8 *pat); #endif /*_ICE_BST_TCAM_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_flg_rd.c b/drivers/net/ethernet/intel/ice/ice_flg_rd.c index 9d5d66d0c773..057bcd68125f 100644 --- a/drivers/net/ethernet/intel/ice/ice_flg_rd.c +++ b/drivers/net/ethernet/intel/ice/ice_flg_rd.c @@ -48,3 +48,26 @@ struct ice_flg_rd_item *ice_flg_rd_table_get(struct ice_hw *hw) ice_parser_sect_item_get, _ice_flg_rd_parse_item, false); } + +/** + * ice_flg_redirect - redirect a parser flag to packet flag + * @table: flag redirect table + * @psr_flg: parser flag to redirect + */ +u64 ice_flg_redirect(struct ice_flg_rd_item *table, u64 psr_flg) +{ + u64 flg = 0; + int i; + + for (i = 0; i < ICE_FLG_RDT_SIZE; i++) { + struct ice_flg_rd_item *item = &table[i]; + + if (!item->expose) + continue; + + if (psr_flg & BIT(item->intr_flg_id)) + flg |= BIT(i); + } + + return flg; +} diff --git a/drivers/net/ethernet/intel/ice/ice_flg_rd.h b/drivers/net/ethernet/intel/ice/ice_flg_rd.h index b3b4fd7a9002..9215c8e0cdfd 100644 --- a/drivers/net/ethernet/intel/ice/ice_flg_rd.h +++ b/drivers/net/ethernet/intel/ice/ice_flg_rd.h @@ -20,4 +20,5 @@ struct ice_flg_rd_item { void ice_flg_rd_dump(struct ice_hw *hw, struct ice_flg_rd_item *item); struct ice_flg_rd_item *ice_flg_rd_table_get(struct ice_hw *hw); +u64 ice_flg_redirect(struct ice_flg_rd_item *table, u64 psr_flg); #endif /* _ICE_FLG_RD_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h index 5f98f3031294..bfcef4f597bf 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.h +++ b/drivers/net/ethernet/intel/ice/ice_parser.h @@ -14,6 +14,7 @@ #include "ice_flg_rd.h" #include "ice_xlt_kb.h" #include "ice_parser_rt.h" +#include "ice_tmatch.h" #define ICE_SEC_DATA_OFFSET 4 #define ICE_SID_RXPARSER_IMEM_ENTRY_SIZE 48 diff --git a/drivers/net/ethernet/intel/ice/ice_pg_cam.c b/drivers/net/ethernet/intel/ice/ice_pg_cam.c index 70b0b0b93a8d..bd17e85834ed 100644 --- a/drivers/net/ethernet/intel/ice/ice_pg_cam.c +++ b/drivers/net/ethernet/intel/ice/ice_pg_cam.c @@ -319,3 +319,79 @@ struct ice_pg_nm_cam_item *ice_pg_nm_sp_cam_table_get(struct ice_hw *hw) ice_parser_sect_item_get, _ice_pg_nm_sp_cam_parse_item, false); } + +static bool _ice_pg_cam_match(struct ice_pg_cam_item *item, + struct ice_pg_cam_key *key) +{ + if (!item->key.valid || + item->key.node_id != key->node_id || + item->key.flag0 != key->flag0 || + item->key.flag1 != key->flag1 || + item->key.flag2 != key->flag2 || + item->key.flag3 != key->flag3 || + item->key.boost_idx != key->boost_idx || + item->key.alu_reg != key->alu_reg || + item->key.next_proto != key->next_proto) + return false; + + return true; +} + +static bool _ice_pg_nm_cam_match(struct ice_pg_nm_cam_item *item, + struct ice_pg_cam_key *key) +{ + if (!item->key.valid || + item->key.node_id != key->node_id || + item->key.flag0 != key->flag0 || + item->key.flag1 != key->flag1 || + item->key.flag2 != key->flag2 || + item->key.flag3 != key->flag3 || + item->key.boost_idx != key->boost_idx || + item->key.alu_reg != key->alu_reg) + return false; + + return true; +} + +/** + * ice_pg_cam_match - search parse graph cam table by key + * @table: parse graph cam table to search + * @size: cam table size + * @key: search key + */ +struct ice_pg_cam_item *ice_pg_cam_match(struct ice_pg_cam_item *table, + int size, struct ice_pg_cam_key *key) +{ + int i; + + for (i = 0; i < size; i++) { + struct ice_pg_cam_item *item = &table[i]; + + if (_ice_pg_cam_match(item, key)) + return item; + } + + return NULL; +} + +/** + * ice_pg_nm_cam_match - search parse graph no match cam table by key + * @table: parse graph no match cam table to search + * @size: cam table size + * @key: search key + */ +struct ice_pg_nm_cam_item * +ice_pg_nm_cam_match(struct ice_pg_nm_cam_item *table, int size, + struct ice_pg_cam_key *key) +{ + int i; + + for (i = 0; i < size; i++) { + struct ice_pg_nm_cam_item *item = &table[i]; + + if (_ice_pg_nm_cam_match(item, key)) + return item; + } + + return NULL; +} diff --git a/drivers/net/ethernet/intel/ice/ice_pg_cam.h b/drivers/net/ethernet/intel/ice/ice_pg_cam.h index 0d5c84d380d3..301165b19b6a 100644 --- a/drivers/net/ethernet/intel/ice/ice_pg_cam.h +++ b/drivers/net/ethernet/intel/ice/ice_pg_cam.h @@ -133,4 +133,10 @@ struct ice_pg_cam_item *ice_pg_sp_cam_table_get(struct ice_hw *hw); struct ice_pg_nm_cam_item *ice_pg_nm_cam_table_get(struct ice_hw *hw); struct ice_pg_nm_cam_item *ice_pg_nm_sp_cam_table_get(struct ice_hw *hw); + +struct ice_pg_cam_item *ice_pg_cam_match(struct ice_pg_cam_item *table, + int size, struct ice_pg_cam_key *key); +struct ice_pg_nm_cam_item * +ice_pg_nm_cam_match(struct ice_pg_nm_cam_item *table, int size, + struct ice_pg_cam_key *key); #endif /* _ICE_PG_CAM_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_ptype_mk.c b/drivers/net/ethernet/intel/ice/ice_ptype_mk.c index ee7b09618d54..fbd46ae857a3 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptype_mk.c +++ b/drivers/net/ethernet/intel/ice/ice_ptype_mk.c @@ -49,3 +49,25 @@ struct ice_ptype_mk_tcam_item *ice_ptype_mk_tcam_table_get(struct ice_hw *hw) ice_parser_sect_item_get, _ice_parse_ptype_mk_tcam_item, true); } + +/** + * ice_ptype_mk_tcam_match - match a pattern on a ptype marker tcam table + * @table: ptype marker tcam table to search + * @pat: pattern to match + * @len: length of the pattern + */ +struct ice_ptype_mk_tcam_item * +ice_ptype_mk_tcam_match(struct ice_ptype_mk_tcam_item *table, + u8 *pat, int len) +{ + int i; + + for (i = 0; i < ICE_PTYPE_MK_TCAM_TABLE_SIZE; i++) { + struct ice_ptype_mk_tcam_item *item = &table[i]; + + if (ice_ternary_match(item->key, item->key_inv, pat, len)) + return item; + } + + return NULL; +} diff --git a/drivers/net/ethernet/intel/ice/ice_ptype_mk.h b/drivers/net/ethernet/intel/ice/ice_ptype_mk.h index 4a071d823bea..c8061f55cccc 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptype_mk.h +++ b/drivers/net/ethernet/intel/ice/ice_ptype_mk.h @@ -17,4 +17,7 @@ struct ice_ptype_mk_tcam_item { void ice_ptype_mk_tcam_dump(struct ice_hw *hw, struct ice_ptype_mk_tcam_item *item); struct ice_ptype_mk_tcam_item *ice_ptype_mk_tcam_table_get(struct ice_hw *hw); +struct ice_ptype_mk_tcam_item * +ice_ptype_mk_tcam_match(struct ice_ptype_mk_tcam_item *table, + u8 *pat, int len); #endif /* _ICE_PTYPE_MK_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_tmatch.h b/drivers/net/ethernet/intel/ice/ice_tmatch.h new file mode 100644 index 000000000000..e7adcf22ae3f --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_tmatch.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2023 Intel Corporation */ + +#ifndef _ICE_TMATCH_H_ +#define _ICE_TMATCH_H_ + +static inline bool ice_ternary_match_byte(u8 key, u8 key_inv, u8 pat) +{ + u8 k1, k2, vv; + int i; + + for (i = 0; i < BITS_PER_BYTE; i++) { + k1 = (u8)(key & BIT(i)); + k2 = (u8)(key_inv & BIT(i)); + vv = (u8)(pat & BIT(i)); + + if (k1 != 0 && k2 != 0) + continue; + if (k1 == 0 && k2 == 0) + return false; + + if (k1 == vv) + return false; + } + + return true; +} + +static inline bool ice_ternary_match(const u8 *key, const u8 *key_inv, + const u8 *pat, int len) +{ + int i; + + for (i = 0; i < len; i++) + if (!ice_ternary_match_byte(key[i], key_inv[i], pat[i])) + return false; + + return true; +} +#endif /* _ICE_TMATCH_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_xlt_kb.c b/drivers/net/ethernet/intel/ice/ice_xlt_kb.c index 4fca88fb7d77..1cb00fabbaf4 100644 --- a/drivers/net/ethernet/intel/ice/ice_xlt_kb.c +++ b/drivers/net/ethernet/intel/ice/ice_xlt_kb.c @@ -233,3 +233,30 @@ struct ice_xlt_kb *ice_xlt_kb_get_rss(struct ice_hw *hw) { return _ice_xlt_kb_get(hw, ICE_SID_XLT_KEY_BUILDER_RSS); } + +/** + * ice_xlt_kb_flag_get - aggregate 64 bits packet flag into 16 bits xlt flag + * @kb: xlt key build + * @pkt_flag: 64 bits packet flag + */ +u16 ice_xlt_kb_flag_get(struct ice_xlt_kb *kb, u64 pkt_flag) +{ + struct ice_xlt_kb_entry *entry = &kb->entries[0]; + u16 flg = 0; + int i; + + /* check flag 15 */ + if (kb->flag15 & pkt_flag) + flg = (u16)BIT(ICE_XLT_KB_FLAG0_14_CNT); + + /* check flag 0 - 14 */ + for (i = 0; i < ICE_XLT_KB_FLAG0_14_CNT; i++) { + /* only check first entry */ + u16 idx = (u16)(entry->flg0_14_sel[i] & ICE_XLT_KB_FLAG_M); + + if (pkt_flag & BIT(idx)) + flg |= (u16)BIT(i); + } + + return flg; +} diff --git a/drivers/net/ethernet/intel/ice/ice_xlt_kb.h b/drivers/net/ethernet/intel/ice/ice_xlt_kb.h index 020f96bfdbe8..dbd80fe8b0b9 100644 --- a/drivers/net/ethernet/intel/ice/ice_xlt_kb.h +++ b/drivers/net/ethernet/intel/ice/ice_xlt_kb.h @@ -76,4 +76,5 @@ struct ice_xlt_kb *ice_xlt_kb_get_sw(struct ice_hw *hw); struct ice_xlt_kb *ice_xlt_kb_get_acl(struct ice_hw *hw); struct ice_xlt_kb *ice_xlt_kb_get_fd(struct ice_hw *hw); struct ice_xlt_kb *ice_xlt_kb_get_rss(struct ice_hw *hw); +u16 ice_xlt_kb_flag_get(struct ice_xlt_kb *kb, u64 pkt_flag); #endif /* _ICE_XLT_KB_H */ From patchwork Mon Aug 21 08:14:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359253 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E8DB5381 for ; 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21 Aug 2023 01:15:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="685577616" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577616" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:15:24 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 12/15] ice: add parser execution main loop Date: Mon, 21 Aug 2023 16:14:35 +0800 Message-Id: <20230821081438.2937934-13-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Implement function ice_parser_rt_execute which perform the main loop of the parser. Also include the Parser Library files into ice Makefile. Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/Makefile | 11 + .../net/ethernet/intel/ice/ice_parser_rt.c | 787 +++++++++++++++++- .../net/ethernet/intel/ice/ice_parser_rt.h | 34 + 3 files changed, 831 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ice/Makefile b/drivers/net/ethernet/intel/ice/Makefile index 5d89392f969b..a0c3d4804300 100644 --- a/drivers/net/ethernet/intel/ice/Makefile +++ b/drivers/net/ethernet/intel/ice/Makefile @@ -26,6 +26,17 @@ ice-y := ice_main.o \ ice_vlan_mode.o \ ice_flex_pipe.o \ ice_flow.o \ + ice_parser.o \ + ice_imem.o \ + ice_pg_cam.o \ + ice_metainit.o \ + ice_bst_tcam.o \ + ice_ptype_mk.o \ + ice_mk_grp.o \ + ice_proto_grp.o \ + ice_flg_rd.o \ + ice_xlt_kb.o \ + ice_parser_rt.o \ ice_idc.o \ ice_devlink.o \ ice_ddp.o \ diff --git a/drivers/net/ethernet/intel/ice/ice_parser_rt.c b/drivers/net/ethernet/intel/ice/ice_parser_rt.c index a6644f4b3324..21a6d0b3c2b4 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser_rt.c +++ b/drivers/net/ethernet/intel/ice/ice_parser_rt.c @@ -31,6 +31,33 @@ static void _ice_rt_flag_set(struct ice_parser_rt *rt, int idx, bool val) if (val) rt->gpr[ICE_GPR_FLG_IDX + y] |= (u16)BIT(x); + else + rt->gpr[ICE_GPR_FLG_IDX + y] &= ~(u16)BIT(x); + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Set parser flag %d value %d\n", + idx, val); +} + +static void _ice_rt_gpr_set(struct ice_parser_rt *rt, int idx, u16 val) +{ + if (idx == ICE_GPR_HO_IDX) + _ice_rt_ho_set(rt, val); + else + rt->gpr[idx] = val; + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Set GPR %d value %d\n", + idx, val); +} + +static void _ice_rt_err_set(struct ice_parser_rt *rt, int idx, bool val) +{ + if (val) + rt->gpr[ICE_GPR_ERR_IDX] |= (u16)BIT(idx); + else + rt->gpr[ICE_GPR_ERR_IDX] &= ~(u16)BIT(idx); + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Set parser error %d value %d\n", + idx, val); } /** @@ -80,6 +107,666 @@ void ice_parser_rt_pktbuf_set(struct ice_parser_rt *rt, const u8 *pkt_buf, memcpy(&rt->gpr[ICE_GPR_HV_IDX], &rt->pkt_buf[ho], ICE_GPR_HV_SIZE); } +static void _ice_bst_key_init(struct ice_parser_rt *rt, + struct ice_imem_item *imem) +{ + u8 tsr = (u8)rt->gpr[ICE_GPR_TSR_IDX]; + u16 ho = rt->gpr[ICE_GPR_HO_IDX]; + u8 *key = rt->bst_key; + int idd, i; + + idd = ICE_BST_TCAM_KEY_SIZE - 1; + if (imem->b_kb.tsr_ctrl) + key[idd] = (u8)tsr; + else + key[idd] = imem->b_kb.prio; + + idd = ICE_BST_KEY_TCAM_SIZE - 1; + for (i = idd; i >= 0; i--) { + int j; + + j = ho + idd - i; + if (j < ICE_PARSER_MAX_PKT_LEN) + key[i] = rt->pkt_buf[ho + idd - i]; + else + key[i] = 0; + } + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Generated Boost TCAM Key:\n"); + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", + key[0], key[1], key[2], key[3], key[4], + key[5], key[6], key[7], key[8], key[9], + key[10], key[11], key[12], key[13], key[14], + key[15], key[16], key[17], key[18], key[19]); + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "\n"); +} + +static u8 _ice_bit_rev_u8(u8 v) +{ + u8 r = 0; + int i; + + for (i = 0; i < BITS_PER_BYTE; i++) { + r |= (u8)((v & BIT(1)) << (BITS_PER_BYTE - 1 - i)); + v >>= 1; + } + + return r; +} + +static u8 _ice_bit_rev_u16(u16 v, int len) +{ + u16 r = 0; + int i; + + for (i = 0; i < len; i++) { + r |= (u16)((v & BIT(1)) << (len - 1 - i)); + v >>= 1; + } + + return r; +} + +static u32 _ice_bit_rev_u32(u32 v, int len) +{ + u32 r = 0; + int i; + + for (i = 0; i < len; i++) { + r |= (u32)((v & BIT(1)) << (len - 1 - i)); + v >>= 1; + } + + return r; +} + +static u32 _ice_hv_bit_sel(struct ice_parser_rt *rt, int start, int len) +{ + u8 b[ICE_NPKB_HV_SIZE]; + u64 d64, msk; + int i; + + int offset = ICE_GPR_HV_IDX + start / BITS_PER_WORD; + + memcpy(b, &rt->gpr[offset], ICE_NPKB_HV_SIZE); + + for (i = 0; i < ICE_NPKB_HV_SIZE; i++) + b[i] = _ice_bit_rev_u8(b[i]); + + d64 = *(u64 *)b; + msk = BITMAP_MASK(len); + + return _ice_bit_rev_u32((u32)((d64 >> (start % BITS_PER_WORD)) & msk), + len); +} + +static u32 _ice_pk_build(struct ice_parser_rt *rt, + struct ice_np_keybuilder *kb) +{ + if (kb->opc == ICE_NPKB_OPC_EXTRACT) + return _ice_hv_bit_sel(rt, kb->start_reg0, kb->len_reg1); + else if (kb->opc == ICE_NPKB_OPC_BUILD) + return rt->gpr[kb->start_reg0] | + ((u32)rt->gpr[kb->len_reg1] << BITS_PER_WORD); + else if (kb->opc == ICE_NPKB_OPC_BYPASS) + return 0; + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Unsupported opc %d\n", kb->opc); + return U32_MAX; +} + +static bool _ice_flag_get(struct ice_parser_rt *rt, int index) +{ + int y = index / ICE_GPR_FLG_SIZE; + int x = index % ICE_GPR_FLG_SIZE; + + return (rt->gpr[ICE_GPR_FLG_IDX + y] & (u16)BIT(x)) != 0; +} + +static void _ice_imem_pgk_init(struct ice_parser_rt *rt, + struct ice_imem_item *imem) +{ + memset(&rt->pg_key, 0, sizeof(rt->pg_key)); + rt->pg_key.next_proto = _ice_pk_build(rt, &imem->np_kb); + + if (imem->pg_kb.flag0_ena) + rt->pg_key.flag0 = _ice_flag_get(rt, imem->pg_kb.flag0_idx); + if (imem->pg_kb.flag1_ena) + rt->pg_key.flag1 = _ice_flag_get(rt, imem->pg_kb.flag1_idx); + if (imem->pg_kb.flag2_ena) + rt->pg_key.flag2 = _ice_flag_get(rt, imem->pg_kb.flag2_idx); + if (imem->pg_kb.flag3_ena) + rt->pg_key.flag3 = _ice_flag_get(rt, imem->pg_kb.flag3_idx); + + rt->pg_key.alu_reg = rt->gpr[imem->pg_kb.alu_reg_idx]; + rt->pg_key.node_id = rt->gpr[ICE_GPR_NN_IDX]; + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Generate Parse Graph Key: node_id(%d),flag0(%d), flag1(%d), flag2(%d), flag3(%d), boost_idx(%d), alu_reg(0x%04x), next_proto(0x%08x)\n", + rt->pg_key.node_id, + rt->pg_key.flag0, + rt->pg_key.flag1, + rt->pg_key.flag2, + rt->pg_key.flag3, + rt->pg_key.boost_idx, + rt->pg_key.alu_reg, + rt->pg_key.next_proto); +} + +static void _ice_imem_alu0_set(struct ice_parser_rt *rt, + struct ice_imem_item *imem) +{ + rt->alu0 = &imem->alu0; + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load ALU0 from imem pc %d\n", + imem->idx); +} + +static void _ice_imem_alu1_set(struct ice_parser_rt *rt, + struct ice_imem_item *imem) +{ + rt->alu1 = &imem->alu1; + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load ALU1 from imem pc %d\n", + imem->idx); +} + +static void _ice_imem_alu2_set(struct ice_parser_rt *rt, + struct ice_imem_item *imem) +{ + rt->alu2 = &imem->alu2; + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load ALU2 from imem pc %d\n", + imem->idx); +} + +static void _ice_imem_pgp_set(struct ice_parser_rt *rt, + struct ice_imem_item *imem) +{ + rt->pg_pri = imem->pg_pri; + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load PG priority %d from imem pc %d\n", + rt->pg_pri, imem->idx); +} + +static void _ice_bst_pgk_init(struct ice_parser_rt *rt, + struct ice_bst_tcam_item *bst) +{ + memset(&rt->pg_key, 0, sizeof(rt->pg_key)); + rt->pg_key.boost_idx = bst->hit_idx_grp; + rt->pg_key.next_proto = _ice_pk_build(rt, &bst->np_kb); + + if (bst->pg_kb.flag0_ena) + rt->pg_key.flag0 = _ice_flag_get(rt, bst->pg_kb.flag0_idx); + if (bst->pg_kb.flag1_ena) + rt->pg_key.flag1 = _ice_flag_get(rt, bst->pg_kb.flag1_idx); + if (bst->pg_kb.flag2_ena) + rt->pg_key.flag2 = _ice_flag_get(rt, bst->pg_kb.flag2_idx); + if (bst->pg_kb.flag3_ena) + rt->pg_key.flag3 = _ice_flag_get(rt, bst->pg_kb.flag3_idx); + + rt->pg_key.alu_reg = rt->gpr[bst->pg_kb.alu_reg_idx]; + rt->pg_key.node_id = rt->gpr[ICE_GPR_NN_IDX]; + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Generate Parse Graph Key: node_id(%d),flag0(%d), flag1(%d), flag2(%d), flag3(%d), boost_idx(%d), alu_reg(0x%04x), next_proto(0x%08x)\n", + rt->pg_key.node_id, + rt->pg_key.flag0, + rt->pg_key.flag1, + rt->pg_key.flag2, + rt->pg_key.flag3, + rt->pg_key.boost_idx, + rt->pg_key.alu_reg, + rt->pg_key.next_proto); +} + +static void _ice_bst_alu0_set(struct ice_parser_rt *rt, + struct ice_bst_tcam_item *bst) +{ + rt->alu0 = &bst->alu0; + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load ALU0 from boost address %d\n", + bst->addr); +} + +static void _ice_bst_alu1_set(struct ice_parser_rt *rt, + struct ice_bst_tcam_item *bst) +{ + rt->alu1 = &bst->alu1; + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load ALU1 from boost address %d\n", + bst->addr); +} + +static void _ice_bst_alu2_set(struct ice_parser_rt *rt, + struct ice_bst_tcam_item *bst) +{ + rt->alu2 = &bst->alu2; + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load ALU2 from boost address %d\n", + bst->addr); +} + +static void _ice_bst_pgp_set(struct ice_parser_rt *rt, + struct ice_bst_tcam_item *bst) +{ + rt->pg_pri = bst->pg_pri; + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load PG priority %d from boost address %d\n", + rt->pg_pri, bst->addr); +} + +static struct ice_pg_cam_item *_ice_pg_cam_match(struct ice_parser_rt *rt) +{ + struct ice_parser *psr = rt->psr; + struct ice_pg_cam_item *item; + + item = ice_pg_cam_match(psr->pg_cam_table, ICE_PG_CAM_TABLE_SIZE, + &rt->pg_key); + if (item) + return item; + + item = ice_pg_cam_match(psr->pg_sp_cam_table, ICE_PG_SP_CAM_TABLE_SIZE, + &rt->pg_key); + return item; +} + +static struct ice_pg_nm_cam_item *_ice_pg_nm_cam_match(struct ice_parser_rt *rt) +{ + struct ice_parser *psr = rt->psr; + struct ice_pg_nm_cam_item *item; + + item = ice_pg_nm_cam_match(psr->pg_nm_cam_table, + ICE_PG_NM_CAM_TABLE_SIZE, &rt->pg_key); + + if (item) + return item; + + item = ice_pg_nm_cam_match(psr->pg_nm_sp_cam_table, + ICE_PG_NM_SP_CAM_TABLE_SIZE, + &rt->pg_key); + return item; +} + +static void _ice_gpr_add(struct ice_parser_rt *rt, int idx, u16 val) +{ + rt->pu.gpr_val_upd[idx] = true; + rt->pu.gpr_val[idx] = val; + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Pending update for register %d value %d\n", + idx, val); +} + +static void _ice_pg_exe(struct ice_parser_rt *rt) +{ + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ParseGraph action ...\n"); + + _ice_gpr_add(rt, ICE_GPR_NP_IDX, rt->action->next_pc); + _ice_gpr_add(rt, ICE_GPR_NN_IDX, rt->action->next_node); + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ParseGraph action done.\n"); +} + +static void _ice_flg_add(struct ice_parser_rt *rt, int idx, bool val) +{ + rt->pu.flg_msk |= BIT(idx); + if (val) + rt->pu.flg_val |= BIT(idx); + else + rt->pu.flg_val &= ~BIT(idx); + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Pending update for flag %d value %d\n", + idx, val); +} + +static void _ice_flg_update(struct ice_parser_rt *rt, struct ice_alu *alu) +{ + int i; + + if (!alu->dedicate_flags_ena) + return; + + if (alu->flags_extr_imm) + for (i = 0; i < alu->dst_len; i++) + _ice_flg_add(rt, alu->dst_start + i, + (alu->flags_start_imm & BIT(i)) != 0); + else + for (i = 0; i < alu->dst_len; i++) + _ice_flg_add(rt, alu->dst_start + i, + _ice_hv_bit_sel(rt, + alu->flags_start_imm + i, + 1) != 0); +} + +static void _ice_po_update(struct ice_parser_rt *rt, struct ice_alu *alu) +{ + if (alu->proto_offset_opc == ICE_PO_OFF_HDR_ADD) + rt->po = (u16)(rt->gpr[ICE_GPR_HO_IDX] + alu->proto_offset); + else if (alu->proto_offset_opc == ICE_PO_OFF_HDR_SUB) + rt->po = (u16)(rt->gpr[ICE_GPR_HO_IDX] - alu->proto_offset); + else if (alu->proto_offset_opc == ICE_PO_OFF_REMAIN) + rt->po = rt->gpr[ICE_GPR_HO_IDX]; + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Update Protocol Offset = %d\n", + rt->po); +} + +static u16 _ice_reg_bit_sel(struct ice_parser_rt *rt, int reg_idx, + int start, int len) +{ + u8 b[ICE_ALU_REG_SIZE]; + u8 v[ICE_ALU_REG_SIZE]; + u32 d32, msk; + int i; + + memcpy(b, &rt->gpr[reg_idx + start / BITS_PER_WORD], ICE_ALU_REG_SIZE); + + for (i = 0; i < ICE_ALU_REG_SIZE; i++) + v[i] = _ice_bit_rev_u8(b[i]); + + d32 = *(u32 *)v; + msk = BITMAP_MASK(len); + + return _ice_bit_rev_u16((u16)((d32 >> (start % BITS_PER_WORD)) & msk), + len); +} + +static void _ice_err_add(struct ice_parser_rt *rt, int idx, bool val) +{ + rt->pu.err_msk |= (u16)BIT(idx); + if (val) + rt->pu.flg_val |= (u64)BIT_ULL(idx); + else + rt->pu.flg_val &= ~(u64)BIT_ULL(idx); + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Pending update for error %d value %d\n", + idx, val); +} + +static void _ice_dst_reg_bit_set(struct ice_parser_rt *rt, struct ice_alu *alu, + bool val) +{ + u16 flg_idx; + + if (alu->dedicate_flags_ena) { + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "DedicatedFlagsEnable should not be enabled in opcode %d\n", + alu->opc); + return; + } + + if (alu->dst_reg_id == ICE_GPR_ERR_IDX) { + if (alu->dst_start >= ICE_PARSER_ERR_NUM) { + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Invalid error %d\n", + alu->dst_start); + return; + } + _ice_err_add(rt, alu->dst_start, val); + } else if (alu->dst_reg_id >= ICE_GPR_FLG_IDX) { + flg_idx = (u16)(((alu->dst_reg_id - ICE_GPR_FLG_IDX) << 4) + + alu->dst_start); + + if (flg_idx >= ICE_PARSER_FLG_NUM) { + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Invalid flag %d\n", + flg_idx); + return; + } + _ice_flg_add(rt, flg_idx, val); + } else { + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Unexpected Dest Register Bit set, RegisterID %d Start %d\n", + alu->dst_reg_id, alu->dst_start); + } +} + +static void _ice_alu_exe(struct ice_parser_rt *rt, struct ice_alu *alu) +{ + u16 dst, src, shift, imm; + + if (alu->shift_xlate_sel) { + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "shift_xlate_sel != 0 is not expected\n"); + return; + } + + _ice_po_update(rt, alu); + _ice_flg_update(rt, alu); + + dst = rt->gpr[alu->dst_reg_id]; + src = _ice_reg_bit_sel(rt, + alu->src_reg_id, alu->src_start, alu->src_len); + shift = alu->shift_xlate_key; + imm = alu->imm; + + switch (alu->opc) { + case ICE_ALU_PARK: + break; + case ICE_ALU_MOV_ADD: + dst = (u16)((src << shift) + imm); + _ice_gpr_add(rt, alu->dst_reg_id, dst); + break; + case ICE_ALU_ADD: + dst += (u16)((src << shift) + imm); + _ice_gpr_add(rt, alu->dst_reg_id, dst); + break; + case ICE_ALU_ORLT: + if (src < imm) + _ice_dst_reg_bit_set(rt, alu, true); + _ice_gpr_add(rt, ICE_GPR_NP_IDX, alu->branch_addr); + break; + case ICE_ALU_OREQ: + if (src == imm) + _ice_dst_reg_bit_set(rt, alu, true); + _ice_gpr_add(rt, ICE_GPR_NP_IDX, alu->branch_addr); + break; + case ICE_ALU_SETEQ: + if (src == imm) + _ice_dst_reg_bit_set(rt, alu, true); + else + _ice_dst_reg_bit_set(rt, alu, false); + _ice_gpr_add(rt, ICE_GPR_NP_IDX, alu->branch_addr); + break; + case ICE_ALU_MOV_XOR: + dst = (u16)((u16)(src << shift) ^ (u16)imm); + _ice_gpr_add(rt, alu->dst_reg_id, dst); + break; + default: + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Unsupported ALU instruction %d\n", + alu->opc); + break; + } +} + +static void _ice_alu0_exe(struct ice_parser_rt *rt) +{ + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU0 ...\n"); + _ice_alu_exe(rt, rt->alu0); + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU0 done.\n"); +} + +static void _ice_alu1_exe(struct ice_parser_rt *rt) +{ + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU1 ...\n"); + _ice_alu_exe(rt, rt->alu1); + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU1 done.\n"); +} + +static void _ice_alu2_exe(struct ice_parser_rt *rt) +{ + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU2 ...\n"); + _ice_alu_exe(rt, rt->alu2); + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU2 done.\n"); +} + +static void _ice_pu_exe(struct ice_parser_rt *rt) +{ + struct ice_gpr_pu *pu = &rt->pu; + int i; + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Updating Registers ...\n"); + + for (i = 0; i < ICE_PARSER_GPR_NUM; i++) { + if (pu->gpr_val_upd[i]) + _ice_rt_gpr_set(rt, i, pu->gpr_val[i]); + } + + for (i = 0; i < ICE_PARSER_FLG_NUM; i++) { + if (pu->flg_msk & BIT(i)) + _ice_rt_flag_set(rt, i, pu->flg_val & BIT(i)); + } + + for (i = 0; i < ICE_PARSER_ERR_NUM; i++) { + if (pu->err_msk & BIT(1)) + _ice_rt_err_set(rt, i, pu->err_val & BIT(i)); + } + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Updating Registers done.\n"); +} + +static void _ice_alu_pg_exe(struct ice_parser_rt *rt) +{ + memset(&rt->pu, 0, sizeof(rt->pu)); + + if (rt->pg_pri == ICE_PG_P0) { + _ice_pg_exe(rt); + _ice_alu0_exe(rt); + _ice_alu1_exe(rt); + _ice_alu2_exe(rt); + } else if (rt->pg_pri == ICE_PG_P1) { + _ice_alu0_exe(rt); + _ice_pg_exe(rt); + _ice_alu1_exe(rt); + _ice_alu2_exe(rt); + } else if (rt->pg_pri == ICE_PG_P2) { + _ice_alu0_exe(rt); + _ice_alu1_exe(rt); + _ice_pg_exe(rt); + _ice_alu2_exe(rt); + } else if (rt->pg_pri == ICE_PG_P3) { + _ice_alu0_exe(rt); + _ice_alu1_exe(rt); + _ice_alu2_exe(rt); + _ice_pg_exe(rt); + } + + _ice_pu_exe(rt); + + if (rt->action->ho_inc == 0) + return; + + if (rt->action->ho_polarity) + _ice_rt_ho_set(rt, + rt->gpr[ICE_GPR_HO_IDX] + rt->action->ho_inc); + else + _ice_rt_ho_set(rt, + rt->gpr[ICE_GPR_HO_IDX] - rt->action->ho_inc); +} + +static void _ice_proto_off_update(struct ice_parser_rt *rt) +{ + struct ice_parser *psr = rt->psr; + + if (rt->action->is_pg) { + struct ice_proto_grp_item *proto_grp = + &psr->proto_grp_table[rt->action->proto_id]; + u16 po; + int i; + + for (i = 0; i < ICE_PROTO_COUNT_PER_GRP; i++) { + struct ice_proto_off *entry = &proto_grp->po[i]; + + if (entry->proto_id == U8_MAX) + break; + + if (!entry->polarity) + po = (u16)(rt->po + entry->offset); + else + po = (u16)(rt->po - entry->offset); + + rt->protocols[entry->proto_id] = true; + rt->offsets[entry->proto_id] = po; + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Set Protocol %d at offset %d\n", + entry->proto_id, po); + } + } else { + rt->protocols[rt->action->proto_id] = true; + rt->offsets[rt->action->proto_id] = rt->po; + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Set Protocol %d at offset %d\n", + rt->action->proto_id, rt->po); + } +} + +static void _ice_marker_set(struct ice_parser_rt *rt, int idx) +{ + int x = idx / BITS_PER_BYTE; + int y = idx % BITS_PER_BYTE; + + rt->markers[x] |= (u8)BIT(y); +} + +static void _ice_marker_update(struct ice_parser_rt *rt) +{ + struct ice_parser *psr = rt->psr; + + if (rt->action->is_mg) { + struct ice_mk_grp_item *mk_grp = + &psr->mk_grp_table[rt->action->marker_id]; + int i; + + for (i = 0; i < ICE_MARKER_ID_NUM; i++) { + u8 marker = mk_grp->markers[i]; + + if (marker == (ICE_MARKER_ID_SIZE * BITS_PER_BYTE - 1)) + break; + + _ice_marker_set(rt, marker); + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Set Marker %d\n", + marker); + } + } else { + if (rt->action->marker_id != + (ICE_MARKER_ID_SIZE * BITS_PER_BYTE - 1)) + _ice_marker_set(rt, rt->action->marker_id); + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Set Marker %d\n", + rt->action->marker_id); + } +} + +static u16 _ice_ptype_resolve(struct ice_parser_rt *rt) +{ + struct ice_parser *psr = rt->psr; + struct ice_ptype_mk_tcam_item *item; + + item = ice_ptype_mk_tcam_match(psr->ptype_mk_tcam_table, + rt->markers, ICE_MARKER_ID_SIZE); + if (item) + return item->ptype; + + return U16_MAX; +} + +static void _ice_proto_off_resolve(struct ice_parser_rt *rt, + struct ice_parser_result *rslt) +{ + int i; + + for (i = 0; i < ICE_PO_PAIR_SIZE - 1; i++) { + if (rt->protocols[i]) { + rslt->po[rslt->po_num].proto_id = (u8)i; + rslt->po[rslt->po_num].offset = rt->offsets[i]; + rslt->po_num++; + } + } +} + +static void _ice_result_resolve(struct ice_parser_rt *rt, + struct ice_parser_result *rslt) +{ + struct ice_parser *psr = rt->psr; + + memset(rslt, 0, sizeof(*rslt)); + + rslt->ptype = _ice_ptype_resolve(rt); + + memcpy(&rslt->flags_psr, &rt->gpr[ICE_GPR_FLG_IDX], + ICE_PARSER_FLAG_PSR_SIZE); + rslt->flags_pkt = ice_flg_redirect(psr->flg_rd_table, rslt->flags_psr); + rslt->flags_sw = ice_xlt_kb_flag_get(psr->xlt_kb_sw, rslt->flags_pkt); + rslt->flags_fd = ice_xlt_kb_flag_get(psr->xlt_kb_fd, rslt->flags_pkt); + rslt->flags_rss = ice_xlt_kb_flag_get(psr->xlt_kb_rss, rslt->flags_pkt); + + _ice_proto_off_resolve(rt, rslt); +} + /** * ice_parser_rt_execute - parser execution routine * @rt: pointer to the parser runtime @@ -88,5 +775,103 @@ void ice_parser_rt_pktbuf_set(struct ice_parser_rt *rt, const u8 *pkt_buf, int ice_parser_rt_execute(struct ice_parser_rt *rt, struct ice_parser_result *rslt) { - return ICE_ERR_NOT_IMPL; + struct ice_pg_nm_cam_item *pg_nm_cam; + struct ice_parser *psr = rt->psr; + struct ice_pg_cam_item *pg_cam; + int status = 0; + u16 node; + u16 pc; + + node = rt->gpr[ICE_GPR_NN_IDX]; + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Start with Node: %d\n", node); + + while (true) { + struct ice_bst_tcam_item *bst; + struct ice_imem_item *imem; + + pc = rt->gpr[ICE_GPR_NP_IDX]; + imem = &psr->imem_table[pc]; + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load imem at pc: %d\n", + pc); + + _ice_bst_key_init(rt, imem); + bst = ice_bst_tcam_match(psr->bst_tcam_table, rt->bst_key); + + if (!bst) { + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "No Boost TCAM Match\n"); + _ice_imem_pgk_init(rt, imem); + _ice_imem_alu0_set(rt, imem); + _ice_imem_alu1_set(rt, imem); + _ice_imem_alu2_set(rt, imem); + _ice_imem_pgp_set(rt, imem); + } else { + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Boost TCAM Match address: %d\n", + bst->addr); + if (imem->b_m.pg) { + _ice_bst_pgk_init(rt, bst); + _ice_bst_pgp_set(rt, bst); + } else { + _ice_imem_pgk_init(rt, imem); + _ice_imem_pgp_set(rt, imem); + } + + if (imem->b_m.alu0) + _ice_bst_alu0_set(rt, bst); + else + _ice_imem_alu0_set(rt, imem); + + if (imem->b_m.alu1) + _ice_bst_alu1_set(rt, bst); + else + _ice_imem_alu1_set(rt, imem); + + if (imem->b_m.alu2) + _ice_bst_alu2_set(rt, bst); + else + _ice_imem_alu2_set(rt, imem); + } + + rt->action = NULL; + pg_cam = _ice_pg_cam_match(rt); + if (!pg_cam) { + pg_nm_cam = _ice_pg_nm_cam_match(rt); + if (pg_nm_cam) { + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Match ParseGraph Nomatch CAM Address %d\n", + pg_nm_cam->idx); + rt->action = &pg_nm_cam->action; + } + } else { + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Match ParseGraph CAM Address %d\n", + pg_cam->idx); + rt->action = &pg_cam->action; + } + + if (!rt->action) { + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Failed to match ParseGraph CAM, stop parsing.\n"); + status = -EINVAL; + break; + } + + _ice_alu_pg_exe(rt); + _ice_marker_update(rt); + _ice_proto_off_update(rt); + + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Go to node %d\n", + rt->action->next_node); + + if (rt->action->is_last_round) { + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Last Round in ParseGraph Action, stop parsing.\n"); + break; + } + + if (rt->gpr[ICE_GPR_HO_IDX] >= rt->pkt_len) { + ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Header Offset %d is larger than packet len %d, stop parsing\n", + rt->gpr[ICE_GPR_HO_IDX], rt->pkt_len); + break; + } + } + + _ice_result_resolve(rt, rslt); + + return status; } diff --git a/drivers/net/ethernet/intel/ice/ice_parser_rt.h b/drivers/net/ethernet/intel/ice/ice_parser_rt.h index dadcb8791430..7a11ffd3d5a7 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser_rt.h +++ b/drivers/net/ethernet/intel/ice/ice_parser_rt.h @@ -20,6 +20,29 @@ struct ice_parser_ctx; #define ICE_PARSER_MAX_PKT_LEN 504 #define ICE_PARSER_PKT_REV 32 #define ICE_PARSER_GPR_NUM 128 +#define ICE_PARSER_FLG_NUM 64 +#define ICE_PARSER_ERR_NUM 16 +#define ICE_BST_KEY_SIZE 10 +#define ICE_MARKER_ID_SIZE 9 +#define ICE_MARKER_ID_NUM 8 +#define ICE_PO_PAIR_SIZE 256 + +struct ice_gpr_pu { + /* array of flags to indicate if GRP needs to be updated */ + bool gpr_val_upd[ICE_PARSER_GPR_NUM]; + u16 gpr_val[ICE_PARSER_GPR_NUM]; + u64 flg_msk; + u64 flg_val; + u16 err_msk; + u16 err_val; +}; + +enum ice_pg_pri { + ICE_PG_P0 = 0, + ICE_PG_P1 = 1, + ICE_PG_P2 = 2, + ICE_PG_P3 = 3, +}; struct ice_parser_rt { struct ice_parser *psr; @@ -27,6 +50,17 @@ struct ice_parser_rt { u8 pkt_buf[ICE_PARSER_MAX_PKT_LEN + ICE_PARSER_PKT_REV]; u16 pkt_len; u16 po; + u8 bst_key[ICE_BST_KEY_SIZE]; + struct ice_pg_cam_key pg_key; + struct ice_alu *alu0; + struct ice_alu *alu1; + struct ice_alu *alu2; + struct ice_pg_cam_action *action; + u8 pg_pri; + struct ice_gpr_pu pu; + u8 markers[ICE_MARKER_ID_SIZE]; + bool protocols[ICE_PO_PAIR_SIZE]; + u16 offsets[ICE_PO_PAIR_SIZE]; }; void ice_parser_rt_reset(struct ice_parser_rt *rt); From patchwork Mon Aug 21 08:14:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359254 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BE665381 for ; Mon, 21 Aug 2023 08:15:33 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B4D1BB for ; Mon, 21 Aug 2023 01:15:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692605732; x=1724141732; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VSHxor5T1n5k59lTMgvGBkeoaMOvQnCXz0VOwWNR2sM=; b=aNbeVcKOghEeCeuYa/BC+zyknC9kuFR2QjPvtmzu8A2mjZNW3G6qP+9s C9YQsuylbzZ0MBCsVuPN4gBBFGnz8bz1dJW7Vtc+FzXibOviE2wwnCsX1 l1S9yhVQ4us9s/iiA+WxO8TgDmPhgvbgc8/TGq58+b1T8nIQXV9QheW/j +BtgY9BtBklaBdHauUvAYBs2zCY7eYYSBHTigAZTIIpo48rKrrf5Zoqbf 5g0BHCAU/kqd4KDeXNXpuTN2utlfMP4b5PT+DiS+qObaGjQikHSBeHERz AdplMNhWHdFor4vBssLlA9YNCu3SE1Mxgsl6aMSOgNXCvTpZ2b5GhDzxL g==; X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="376280538" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="376280538" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2023 01:15:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="685577621" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577621" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:15:27 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 13/15] ice: support double vlan mode configure for parser Date: Mon, 21 Aug 2023 16:14:36 +0800 Message-Id: <20230821081438.2937934-14-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Add API ice_parser_dvm_set to support turn on/off parser's double vlan mode. Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/ice_bst_tcam.c | 17 +++++++++ drivers/net/ethernet/intel/ice/ice_bst_tcam.h | 4 +++ drivers/net/ethernet/intel/ice/ice_parser.c | 36 +++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_parser.h | 2 ++ 4 files changed, 59 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_bst_tcam.c b/drivers/net/ethernet/intel/ice/ice_bst_tcam.c index f31023da0a41..fd8d06d400c3 100644 --- a/drivers/net/ethernet/intel/ice/ice_bst_tcam.c +++ b/drivers/net/ethernet/intel/ice/ice_bst_tcam.c @@ -294,3 +294,20 @@ ice_bst_tcam_match(struct ice_bst_tcam_item *tcam_table, u8 *pat) return NULL; } + +struct ice_bst_tcam_item * +ice_bst_tcam_search(struct ice_bst_tcam_item *tcam_table, + struct ice_lbl_item *lbl_table, + const char *prefix, u16 *start) +{ + u16 i = *start; + + for (; i < ICE_BST_TCAM_TABLE_SIZE; i++) { + if (strstarts(lbl_table[i].label, prefix)) { + *start = i; + return &tcam_table[lbl_table[i].idx]; + } + } + + return NULL; +} diff --git a/drivers/net/ethernet/intel/ice/ice_bst_tcam.h b/drivers/net/ethernet/intel/ice/ice_bst_tcam.h index 960c8ff09171..d812c76c0549 100644 --- a/drivers/net/ethernet/intel/ice/ice_bst_tcam.h +++ b/drivers/net/ethernet/intel/ice/ice_bst_tcam.h @@ -45,4 +45,8 @@ struct ice_lbl_item *ice_bst_lbl_table_get(struct ice_hw *hw); struct ice_bst_tcam_item * ice_bst_tcam_match(struct ice_bst_tcam_item *tcam_table, u8 *pat); +struct ice_bst_tcam_item * +ice_bst_tcam_search(struct ice_bst_tcam_item *tcam_table, + struct ice_lbl_item *lbl_table, + const char *prefix, u16 *start); #endif /*_ICE_BST_TCAM_H_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c index 1bd1417e32c6..5ce98cd303e1 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.c +++ b/drivers/net/ethernet/intel/ice/ice_parser.c @@ -325,3 +325,39 @@ void ice_parser_result_dump(struct ice_hw *hw, struct ice_parser_result *rslt) dev_info(ice_hw_to_dev(hw), "flags_fd = 0x%04x\n", rslt->flags_fd); dev_info(ice_hw_to_dev(hw), "flags_rss = 0x%04x\n", rslt->flags_rss); } + +#define ICE_BT_VLD_KEY 0xFF +#define ICE_BT_INV_KEY 0xFE + +static void _ice_bst_vm_set(struct ice_parser *psr, const char *prefix, + bool on) +{ + u16 i = 0; + + while (true) { + struct ice_bst_tcam_item *item; + + item = ice_bst_tcam_search(psr->bst_tcam_table, + psr->bst_lbl_table, + prefix, &i); + if (!item) + break; + + item->key[ICE_BT_VM_OFF] = + (u8)(on ? ICE_BT_VLD_KEY : ICE_BT_INV_KEY); + item->key_inv[ICE_BT_VM_OFF] = + (u8)(on ? ICE_BT_VLD_KEY : ICE_BT_INV_KEY); + i++; + } +} + +/** + * ice_parser_dvm_set - configure double vlan mode for parser + * @psr: pointer to a parser instance + * @on: true to turn on; false to turn off + */ +void ice_parser_dvm_set(struct ice_parser *psr, bool on) +{ + _ice_bst_vm_set(psr, "BOOST_MAC_VLAN_DVM", on); + _ice_bst_vm_set(psr, "BOOST_MAC_VLAN_SVM", !on); +} diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h index bfcef4f597bf..c9eee988ebb2 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.h +++ b/drivers/net/ethernet/intel/ice/ice_parser.h @@ -33,6 +33,7 @@ #define ICE_SID_LBL_ENTRY_SIZE 66 #define ICE_PARSER_PROTO_OFF_PAIR_SIZE 16 +#define ICE_BT_VM_OFF 0 struct ice_parser { struct ice_hw *hw; /* pointer to the hardware structure */ @@ -74,6 +75,7 @@ struct ice_parser { int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr); void ice_parser_destroy(struct ice_parser *psr); +void ice_parser_dvm_set(struct ice_parser *psr, bool on); struct ice_parser_proto_off { u8 proto_id; /* hardware protocol ID */ From patchwork Mon Aug 21 08:14:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359255 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E6AE4C80 for ; Mon, 21 Aug 2023 08:15:36 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28238BB for ; Mon, 21 Aug 2023 01:15:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692605735; x=1724141735; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9VVAzoph9bkRZBHLWwGeyUb9l+/n3HuJxnr1k8LVCiQ=; b=PzzrLpREZDyHY4tgOef0lyUW6RUHnVULOlhkOVyfhAceoXYF5Gw4Y8wq uqPiIyC2zm7hbioTwDExMqKzvlhm7iAXsmqcrdmRLzGysPJ0/LH723wdY qv/HLfTBuzX0WFGm/gapCZT4coyu++Vm79PCbAFjAbbczphPOsFcMnylk UhIbZexQ7ZcM0sEGJJun/m80b0WR+MvTmoEGTXb0tjlBOY3K5MFHDDOfD 9LCCf8p/2hTSD73oI3u4WRfTIk5eHfl9QOUtinVkLWiE0U6KFRdWYkL37 XQ7caibjqx34EsohUvFnChr3KKGTlDje4v9dbUVZBUl3O8ECVTNzVa8rY Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="376280561" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="376280561" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2023 01:15:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="685577629" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577629" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:15:31 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 14/15] ice: add tunnel port support for parser Date: Mon, 21 Aug 2023 16:14:37 +0800 Message-Id: <20230821081438.2937934-15-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org UDP tunnel can be added/deleted for vxlan, geneve, ecpri through below APIs: - ice_parser_vxlan_tunnel_set - ice_parser_geneve_tunnel_set - ice_parser_ecpri_tunnel_set Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/ice_parser.c | 85 +++++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_parser.h | 10 +++ 2 files changed, 95 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c index 5ce98cd303e1..85a2833ffc58 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.c +++ b/drivers/net/ethernet/intel/ice/ice_parser.c @@ -361,3 +361,88 @@ void ice_parser_dvm_set(struct ice_parser *psr, bool on) _ice_bst_vm_set(psr, "BOOST_MAC_VLAN_DVM", on); _ice_bst_vm_set(psr, "BOOST_MAC_VLAN_SVM", !on); } + +static int _ice_tunnel_port_set(struct ice_parser *psr, const char *prefix, + u16 udp_port, bool on) +{ + u8 *buf = (u8 *)&udp_port; + u16 i = 0; + + while (true) { + struct ice_bst_tcam_item *item; + + item = ice_bst_tcam_search(psr->bst_tcam_table, + psr->bst_lbl_table, + prefix, &i); + if (!item) + break; + + /* found empty slot to add */ + if (on && item->key[ICE_BT_TUN_PORT_OFF_H] == ICE_BT_INV_KEY && + item->key_inv[ICE_BT_TUN_PORT_OFF_H] == ICE_BT_INV_KEY) { + item->key_inv[ICE_BT_TUN_PORT_OFF_L] = + buf[ICE_UDP_PORT_OFF_L]; + item->key_inv[ICE_BT_TUN_PORT_OFF_H] = + buf[ICE_UDP_PORT_OFF_H]; + + item->key[ICE_BT_TUN_PORT_OFF_L] = + (u8)(ICE_BT_VLD_KEY - buf[ICE_UDP_PORT_OFF_L]); + item->key[ICE_BT_TUN_PORT_OFF_H] = + (u8)(ICE_BT_VLD_KEY - buf[ICE_UDP_PORT_OFF_H]); + + return 0; + /* found a matched slot to delete */ + } else if (!on && + (item->key_inv[ICE_BT_TUN_PORT_OFF_L] == + buf[ICE_UDP_PORT_OFF_L] || + item->key_inv[ICE_BT_TUN_PORT_OFF_H] == + buf[ICE_UDP_PORT_OFF_H])) { + item->key_inv[ICE_BT_TUN_PORT_OFF_L] = ICE_BT_VLD_KEY; + item->key_inv[ICE_BT_TUN_PORT_OFF_H] = ICE_BT_INV_KEY; + + item->key[ICE_BT_TUN_PORT_OFF_L] = ICE_BT_VLD_KEY; + item->key[ICE_BT_TUN_PORT_OFF_H] = ICE_BT_INV_KEY; + + return 0; + } + i++; + } + + return -EINVAL; +} + +/** + * ice_parser_vxlan_tunnel_set - configure vxlan tunnel for parser + * @psr: pointer to a parser instance + * @udp_port: vxlan tunnel port in UDP header + * @on: true to turn on; false to turn off + */ +int ice_parser_vxlan_tunnel_set(struct ice_parser *psr, + u16 udp_port, bool on) +{ + return _ice_tunnel_port_set(psr, "TNL_VXLAN", udp_port, on); +} + +/** + * ice_parser_geneve_tunnel_set - configure geneve tunnel for parser + * @psr: pointer to a parser instance + * @udp_port: geneve tunnel port in UDP header + * @on: true to turn on; false to turn off + */ +int ice_parser_geneve_tunnel_set(struct ice_parser *psr, + u16 udp_port, bool on) +{ + return _ice_tunnel_port_set(psr, "TNL_GENEVE", udp_port, on); +} + +/** + * ice_parser_ecpri_tunnel_set - configure ecpri tunnel for parser + * @psr: pointer to a parser instance + * @udp_port: ecpri tunnel port in UDP header + * @on: true to turn on; false to turn off + */ +int ice_parser_ecpri_tunnel_set(struct ice_parser *psr, + u16 udp_port, bool on) +{ + return _ice_tunnel_port_set(psr, "TNL_UDP_ECPRI", udp_port, on); +} diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h index c9eee988ebb2..3cfcec4dc477 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.h +++ b/drivers/net/ethernet/intel/ice/ice_parser.h @@ -33,6 +33,10 @@ #define ICE_SID_LBL_ENTRY_SIZE 66 #define ICE_PARSER_PROTO_OFF_PAIR_SIZE 16 +#define ICE_BT_TUN_PORT_OFF_H 16 +#define ICE_BT_TUN_PORT_OFF_L 15 +#define ICE_UDP_PORT_OFF_H 1 +#define ICE_UDP_PORT_OFF_L 0 #define ICE_BT_VM_OFF 0 struct ice_parser { @@ -76,6 +80,12 @@ struct ice_parser { int ice_parser_create(struct ice_hw *hw, struct ice_parser **psr); void ice_parser_destroy(struct ice_parser *psr); void ice_parser_dvm_set(struct ice_parser *psr, bool on); +int ice_parser_vxlan_tunnel_set(struct ice_parser *psr, + u16 udp_port, bool on); +int ice_parser_geneve_tunnel_set(struct ice_parser *psr, + u16 udp_port, bool on); +int ice_parser_ecpri_tunnel_set(struct ice_parser *psr, + u16 udp_port, bool on); struct ice_parser_proto_off { u8 proto_id; /* hardware protocol ID */ From patchwork Mon Aug 21 08:14:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junfeng Guo X-Patchwork-Id: 13359256 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE280567B for ; Mon, 21 Aug 2023 08:15:39 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67702BB for ; Mon, 21 Aug 2023 01:15:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692605738; x=1724141738; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7NI0c1Wfuj/LYqrEnvCEufY2tS1g4s8hS42RUAcXI0c=; b=PjmRX5dSwvCDlPeouRJ33V6woK5JND47+DjYzgs5F++JWU0+t+tMXoIH +LQkom4VSEP9QgYMVpEqsN1vrXR8lLOScNHciLJpKqTrI1dz/nwUA3dnm N/l7duqnrg0aEq6WGluz+/unT+eFYuPuKx21g0eKCi1hjX5e8vgQ6pX8F FPIHnmMrPCy6sNLIYBovez80HdyGEPh2n0qAsH6wOl2Ut7ikPyBBs8yVk 70MwG96aJZSiz+WkK6m37mdMXGisSRhT6zyzcKo0ecyj0qCxy3FtgTm7j TZCE0ft4Tm4qmWyeC1R9epvIxJHmUAhk8zJIHaNYAitSI9pe9KKKLiUob A==; X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="376280592" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="376280592" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2023 01:15:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10808"; a="685577637" X-IronPort-AV: E=Sophos;i="6.01,189,1684825200"; d="scan'208";a="685577637" Received: from dpdk-jf-ntb-v2.sh.intel.com ([10.67.119.19]) by orsmga003.jf.intel.com with ESMTP; 21 Aug 2023 01:15:34 -0700 From: Junfeng Guo To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, jesse.brandeburg@intel.com, qi.z.zhang@intel.com, ivecera@redhat.com, sridhar.samudrala@intel.com, horms@kernel.org, Junfeng Guo Subject: [PATCH iwl-next v6 15/15] ice: add API for parser profile initialization Date: Mon, 21 Aug 2023 16:14:38 +0800 Message-Id: <20230821081438.2937934-16-junfeng.guo@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821081438.2937934-1-junfeng.guo@intel.com> References: <20230821023833.2700902-1-junfeng.guo@intel.com> <20230821081438.2937934-1-junfeng.guo@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Add API ice_parser_profile_init to init a parser profile base on a parser result and a mask buffer. The ice_parser_profile can feed to low level FXP engine to create HW profile / field vector directly. Signed-off-by: Junfeng Guo --- drivers/net/ethernet/intel/ice/ice_parser.c | 114 ++++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_parser.h | 27 +++++ 2 files changed, 141 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_parser.c b/drivers/net/ethernet/intel/ice/ice_parser.c index 85a2833ffc58..7a4cf7e9da57 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.c +++ b/drivers/net/ethernet/intel/ice/ice_parser.c @@ -446,3 +446,117 @@ int ice_parser_ecpri_tunnel_set(struct ice_parser *psr, { return _ice_tunnel_port_set(psr, "TNL_UDP_ECPRI", udp_port, on); } + +static bool _ice_nearest_proto_id(struct ice_parser_result *rslt, u16 offset, + u8 *proto_id, u16 *proto_off) +{ + u16 dist = U16_MAX; + u8 proto = 0; + int i; + + for (i = 0; i < rslt->po_num; i++) { + if (offset < rslt->po[i].offset) + continue; + if (offset - rslt->po[i].offset < dist) { + proto = rslt->po[i].proto_id; + dist = offset - rslt->po[i].offset; + } + } + + if (dist % 2) + return false; + + *proto_id = proto; + *proto_off = dist; + + return true; +} + +/** default flag mask to cover GTP_EH_PDU, GTP_EH_PDU_LINK and TUN2 + * In future, the flag masks should learn from DDP + */ +#define ICE_KEYBUILD_FLAG_MASK_DEFAULT_SW 0x4002 +#define ICE_KEYBUILD_FLAG_MASK_DEFAULT_ACL 0x0000 +#define ICE_KEYBUILD_FLAG_MASK_DEFAULT_FD 0x6080 +#define ICE_KEYBUILD_FLAG_MASK_DEFAULT_RSS 0x6010 + +/** + * ice_parser_profile_init - initialize a FXP profile base on parser result + * @rslt: a instance of a parser result + * @pkt_buf: packet data buffer + * @msk_buf: packet mask buffer + * @buf_len: packet length + * @blk: FXP pipeline stage + * @prefix_match: match protocol stack exactly or only prefix + * @prof: input/output parameter to save the profile + */ +int ice_parser_profile_init(struct ice_parser_result *rslt, + const u8 *pkt_buf, const u8 *msk_buf, + int buf_len, enum ice_block blk, + bool prefix_match, + struct ice_parser_profile *prof) +{ + u8 proto_id = U8_MAX; + u16 proto_off = 0; + u16 off; + + memset(prof, 0, sizeof(*prof)); + set_bit(rslt->ptype, prof->ptypes); + if (blk == ICE_BLK_SW) { + prof->flags = rslt->flags_sw; + prof->flags_msk = ICE_KEYBUILD_FLAG_MASK_DEFAULT_SW; + } else if (blk == ICE_BLK_ACL) { + prof->flags = rslt->flags_acl; + prof->flags_msk = ICE_KEYBUILD_FLAG_MASK_DEFAULT_ACL; + } else if (blk == ICE_BLK_FD) { + prof->flags = rslt->flags_fd; + prof->flags_msk = ICE_KEYBUILD_FLAG_MASK_DEFAULT_FD; + } else if (blk == ICE_BLK_RSS) { + prof->flags = rslt->flags_rss; + prof->flags_msk = ICE_KEYBUILD_FLAG_MASK_DEFAULT_RSS; + } else { + return -EINVAL; + } + + for (off = 0; off < buf_len - 1; off++) { + if (msk_buf[off] == 0 && msk_buf[off + 1] == 0) + continue; + if (!_ice_nearest_proto_id(rslt, off, &proto_id, &proto_off)) + continue; + if (prof->fv_num >= ICE_PARSER_FV_MAX) + return -EINVAL; + + prof->fv[prof->fv_num].proto_id = proto_id; + prof->fv[prof->fv_num].offset = proto_off; + prof->fv[prof->fv_num].spec = *(const u16 *)&pkt_buf[off]; + prof->fv[prof->fv_num].msk = *(const u16 *)&msk_buf[off]; + prof->fv_num++; + } + + return 0; +} + +/** + * ice_parser_profile_dump - dump an FXP profile info + * @hw: pointer to the hardware structure + * @prof: profile info to dump + */ +void ice_parser_profile_dump(struct ice_hw *hw, + struct ice_parser_profile *prof) +{ + u16 i; + + dev_info(ice_hw_to_dev(hw), "ptypes:\n"); + for (i = 0; i < ICE_FLOW_PTYPE_MAX; i++) + if (test_bit(i, prof->ptypes)) + dev_info(ice_hw_to_dev(hw), "\t%d\n", i); + + for (i = 0; i < prof->fv_num; i++) + dev_info(ice_hw_to_dev(hw), + "proto = %d, offset = %2d; spec = 0x%04x, mask = 0x%04x\n", + prof->fv[i].proto_id, prof->fv[i].offset, + prof->fv[i].spec, prof->fv[i].msk); + + dev_info(ice_hw_to_dev(hw), "flags = 0x%04x\n", prof->flags); + dev_info(ice_hw_to_dev(hw), "flags_msk = 0x%04x\n", prof->flags_msk); +} diff --git a/drivers/net/ethernet/intel/ice/ice_parser.h b/drivers/net/ethernet/intel/ice/ice_parser.h index 3cfcec4dc477..503c610b5c92 100644 --- a/drivers/net/ethernet/intel/ice/ice_parser.h +++ b/drivers/net/ethernet/intel/ice/ice_parser.h @@ -33,6 +33,8 @@ #define ICE_SID_LBL_ENTRY_SIZE 66 #define ICE_PARSER_PROTO_OFF_PAIR_SIZE 16 +#define ICE_PARSER_FV_SIZE 48 +#define ICE_PARSER_FV_MAX 24 #define ICE_BT_TUN_PORT_OFF_H 16 #define ICE_BT_TUN_PORT_OFF_L 15 #define ICE_UDP_PORT_OFF_H 1 @@ -110,4 +112,29 @@ struct ice_parser_result { int ice_parser_run(struct ice_parser *psr, const u8 *pkt_buf, int pkt_len, struct ice_parser_result *rslt); void ice_parser_result_dump(struct ice_hw *hw, struct ice_parser_result *rslt); + +struct ice_parser_fv { + u8 proto_id; /* hardware protocol ID */ + u16 offset; /* offset from the start of the protocol header */ + u16 spec; /* 16 bits pattern to match */ + u16 msk; /* 16 bits pattern mask */ +}; + +struct ice_parser_profile { + /* array of field vectors */ + struct ice_parser_fv fv[ICE_PARSER_FV_SIZE]; + int fv_num; /* # of field vectors must <= 48 */ + u16 flags; /* 16 bits key builder flags */ + u16 flags_msk; /* key builder flag mask */ + + DECLARE_BITMAP(ptypes, ICE_FLOW_PTYPE_MAX); /* PTYPE bitmap */ +}; + +int ice_parser_profile_init(struct ice_parser_result *rslt, + const u8 *pkt_buf, const u8 *msk_buf, + int buf_len, enum ice_block blk, + bool prefix_match, + struct ice_parser_profile *prof); +void ice_parser_profile_dump(struct ice_hw *hw, + struct ice_parser_profile *prof); #endif /* _ICE_PARSER_H_ */