From patchwork Tue Aug 29 16:03:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369120 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8FCC4C83F12 for ; Tue, 29 Aug 2023 15:59:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B15110E3D0; Tue, 29 Aug 2023 15:58:49 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7B37E10E3C7; Tue, 29 Aug 2023 15:58:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324726; x=1724860726; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rB6jTV1QKl1OfUoWo3vsbFXqCa6j/dbf0RZ5sbKnuU0=; b=bHb2EeR6HFdgkLAGvNZUm24Mej4YXVke1GXyjqGeDs2f7ql9m1sxCM6Z yAqdvaBxTSILIUHJ7Hlb+N0oJYF5d0lWpwiuqJ8IF8seRWTIlOIsXV7Tt RCK6sLTbeYx2HxBHFmuxAh65GPeko+64faS95yXOZ3aIZbZZa+mA8cASL 4QPueM5XXJxkZjlMfnDVUIhNd9VPBU9jcAuQDGnb6tgTH38b0/u/bc1Mc r42efXzzNgE5D7b/uo8sZ/2hgQmQpVmY8k4z89Yq31lvRYSjFpWVx+GQY 4AugtQx7RsCAQ6AK3/zlGtDMCs+Fx/zYob9B7ku8/YyGOXYAuMPpxW3TR w==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769171" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769171" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:58:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688554889" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688554889" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:58:44 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 01/33] drm/doc/rfc: Add RFC document for proposed Plane Color Pipeline Date: Tue, 29 Aug 2023 21:33:50 +0530 Message-ID: <20230829160422.1251087-2-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the documentation for the new proposed Plane Color Pipeline. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- .../gpu/rfc/plane_color_pipeline.rst | 394 ++++++++++++++++++ 1 file changed, 394 insertions(+) create mode 100644 Documentation/gpu/rfc/plane_color_pipeline.rst diff --git a/Documentation/gpu/rfc/plane_color_pipeline.rst b/Documentation/gpu/rfc/plane_color_pipeline.rst new file mode 100644 index 000000000000..60ce515b6ea7 --- /dev/null +++ b/Documentation/gpu/rfc/plane_color_pipeline.rst @@ -0,0 +1,394 @@ +======================================= + Plane Color Pipeline: A UAPI proposal +======================================= + +To build the proposal on, lets take the premise of a color pipeline as shown +below. + + +-------------------------------------------+ + | RAM | + | +------+ +---------+ +---------+ | + | | FB 1 | | FB 2 | | FB N | | + | +------+ +---------+ +---------+ | + +-------------------------------------------+ + | Plane Color Hardware Block | + +--------------------------------------------+ + | +---v-----+ +---v-------+ +---v------+ | + | | Plane A | | Plane B | | Plane N | | + | | Pre-CSC | | Pre-CSC | | Pre-CSC | | + | +---+-----+ +---+-------+ +---+------+ | + | | | | | + | +---v-----+ +---v-------+ +---v------+ | + | |Plane A | | Plane B | | Plane N | | + | |CSC/CTM | | CSC/CTM | | CSC/CTM | | + | +---+-----+ +----+------+ +----+-----+ | + | | | | | + | +---v-----+ +----v------+ +----v-----+ | + | | Plane A | | Plane B | | Plane N | | + | |Post-CSC | | Post-CSC | | Post-CSC | | + | +---+-----+ +----+------+ +----+-----+ | + | | | | | + +--------------------------------------------+ ++------v--------------v---------------v-------| +|| || +|| Pipe Blender || ++--------------------+------------------------+ +| | | +| +-----------v----------+ | +| | Pipe Pre-CSC | | +| | | | +| +-----------+----------+ | +| | Pipe Color | +| +-----------v----------+ Hardware | +| | Pipe CSC/CTM | | +| | | | +| +-----------+----------+ | +| | | +| +-----------v----------+ | +| | Pipe Post-CSC | | +| | | | +| +-----------+----------+ | +| | | ++---------------------------------------------+ + | + v + Pipe Output + +Each plane consists of the following color blocks + * Pre-CSC : This block can used to linearize the input frame buffer data. + The linear data then can be further acted on by the following + color hardware blocks in the display hardware pipeline + + * CSC/CTM: Used to program color transformation matrix, this block is used + to perform color space conversions like BT2020 to BT709 or BT601 + etc. This block acts on the linearized data coming from the + Pre-CSC HW block. + + * Post-CSC: This HW block can be used to non-linearize frame buffer data to + match the sink. Another use case of it could be to perform Tone + mapping for HDR use-cases. + +Data from multiple planes will then be fed to pipe/crtc where it will get blended. +There is a similar set of HW blocks available at pipe/crtc level which acts on +this blended data. + +Below is a sample usecase fo video playback with sub-titles and playback +controls + +┌────────────┐ ┌─────────────┐ ┌─────────────┐ ┌─────────────┐ +│FB1 │ │PRE-CSC │ │ CTM Matrix │ │ POST-CSC │ +│ ├───►│Linearize ├────►│ BT709 to ├───►│ SDR to HDR │ +│BT709 SDR │ │ │ │ BT2020 │ │ Tone Mapping├─────┐ +└────────────┘ └─────────────┘ └─────────────┘ └─────────────┘ │ +(subtitles) │ + │ +┌────────────┐ ┌─────────────┐ ┌─────────────┐ ┌─────────────┐ │ +│FB2 │ │PRE-CSC │ │ CTM Matrix │ │ POST-CSC │ │ +│ ├───►│Linearize ├────►│ BT601 to ├───►│ SDR to HDR ├───┐ │ +│BT601 SDR │ │ │ │ BT2020 │ │ Tone Mapping│ │ │ +└────────────┘ └─────────────┘ └─────────────┘ └─────────────┘ │ │ +(Playback controls UI) │ │ + │ │ +┌────────────┐ ┌─────────────┐ ┌─────────────┐ ┌─────────────┐ │ │ +│FB2 │ │PRE-CSC │ │ CTM Matrix │ │ POST-CSC │ │ │ +│ ├───►│Linearize ├────►│ BT601 to ├───►│ SDR to HDR ├─┐ │ │ +│BT2020 HDR │ │ │ │ pass-through│ │ pass-through│ │ │ │ +└────────────┘ └─────────────┘ └─────────────┘ └─────────────┘ │ │ │ +(video frame) │ │ │ + │ │ │ +┌────────────────────────────────────────────────────────────────────────┴─┴─┘ +│ +│ ┌─────────────┐ ┌─────────────┐ ┌───────────────┐ +│ │ CRTC │ │ CRTC │ │ CRTC │ +└─┤ PRE-CSC ├─────►│ CSC/CTM ├─────►│ POST-CSC ├─────► TO Port + │ │ │ │ │ │ + └─────────────┘ └─────────────┘ └───────────────┘ + +This RFC is intended to propose an uAPI for the pre-blending color pipeline +(however, can be also extended to post blending pipeline). + +Below are the design considerations while designing the uAPI. + +1. Individual HW blocks can be muxed. (e.g. out of two HW blocks only one can be used) +2. Position of the HW block can be programmable +3. LUTs can be one dimentional or three dimentional +4. Number of LUT entries can vary across platforms +5. Precision of LUT entries can vary across platforms +6. Distribution of LUT entries may vary. e.g Mutli-segmented, Logarithmic, + Piece-Wise Linear(PWL) etc +7. There can be parameterized/non-parameterized fixed function HW blocks. + e.g. Just a hardware bit, to convert from one color space to another. + +Plane Color Pipeline: Design Proposal +===================================== +Each Color Hardware block will be represented by the structure drm_color_op. + +struct drm_color_op { + enum color_op_block name; + enum color_op_type type; + u32 blob_id; + u32 private_flags; +}; + +The members of which will constitute: +1. name: A standardised enum for the color hardware block +2. type: The type of mathematical operation done by the hardware block. + e.g. 1D Curve, 3D Curve, Matrix etc. +3. blob id: Id pointing to a blob containing information about the hardware + block advertising the respective capabilities to the userspace. + It can be an optional field depending on the members "name" and "type". +4. private_flags: This can be used to provide vendor specific hints + to user space + + + For example to represent LUTs, we introduce the drm_color_lut_range + structure. It can represent LUTs with varied number of entries and + distributions (Multi segmented, Logarithmic etc). + + struct drm_color_lut_range { + /* DRM_MODE_LUT_* */ + __u32 flags; + /* number of points on the curve */ + __u16 count; + /* input/output bits per component */ + __u8 input_bpc, output_bpc; + /* input start/end values */ + __s32 start, end; + /* output min/max values */ + __s32 min, max; + }; + +Note: More details on exact usage and implementation of this structure can be + found in the RFC. This structure is taken as is from the series. + https://patchwork.freedesktop.org/series/90825/ + However, we can add more members to it to encompass all use-cases. + For example. we can add a precision field to advertise the + bitdepth of the LUTs. Similarly, we can reserve some bits in the flag + field for vendor specific use cases. + + At the same time, we don't need to pass any additional information for the + CSC block as userspace and driver already agrees struct drm_color_ctm as + a uAPI to pass on data. + +These color operations will form the building blocks of a color pipeline which +best represents the underlying Hardware. Color operations can be re-arranged, +substracted or added to create distinct color pipelines to accurately describe +the Hardware blocks present in the display engine. + +In this proposal, a color pipeline is represented as an array of +struct drm_color_op. + +struct drm_color_op color_pipeline_1[] + +For example to represent the pre-blending color pipeline as described above + +We can create a color pipeline like this. + +struct drm_color_op color_pipeline_1[] = { + { + .name = DRM_CB_PRE_CSC, + .type = CURVE_1D, + .blob_id = 0; /* actual value to be populated during plane + initialization*/ + }, + { + .name = DRM_CB_CSC, + .type = MATRIX, + .blob_id = 0; + }, + { + .name = DRM_CB_POST_CSC, + .type = CURVE_1D, + .blob_id = 0; + }, +}; + +Then, for individual color operation, we add blobs to advertise the capability +of the particular Hardware block. In case of the example pipeline, we add +blobs of type drm_color_lut_range for the "pre-csc" and "post-csc". +For the "csc" block we pass no blob id to user space as it is known to both +user space and driver that drm_color_ctm structure is to be used for such +operation. + +To represent, this in a diagram. + + struct drm_color_op color_pipeline_1[] + +---------------------------+ + | | drm_color_op + | +---------------------+--+-----------+---------------------+ + | | | | | | + | | | | | +-----------------+ | + | | | | | | name | | + | | | | | +-----------------+ | + | | | | | | type | | + | | color_op_1 | | | +-----------------+ | + | | | | | | blob id | +--------+ + | | | | | +-----------------+ | | + | | | | | | private | | | + | | | | | | flags | | | + | | | | | +-----------------+ | | + | | | | | | | + | +---------------------+--+-----------+---------------------+ | + | | | + | | | + | +---------------------+ | | + | | | | drm_color_lut_range | + | | color_op_2 | | +-------------------------+ | + | | | | | | | + | | | | | +---------------------+ | | + | +---------------------+ | | | segment 1 { | |<---+ + | | | | ... | | + | +---------------------+ | | | .input_bpc = 16, | | + | | | | | | .output_bpc = 16, | | + | | color_op_3 | | | | ... | | + | | | | | | } | | + | | | | | +---------------------+ | + | +---------------------+ | | | + | . | | +---------------------+ | + | . | | | segment 2 { | | + | . | | | ... | | + +---------------------------+ | | } | | + | | | | + | | | | + | | | | + | +---------------------+ | + | . | + | . | + | . | + +-------------------------+ + + + +This color pipeline is then packaged within a blob for the user space to +retrieve it. Details can be found in the next section + +Exposing a color pipeline to user space +======================================= + +To advertise the available color pipelines, an immutable ENUM property +"GET_COLOR_PIPELINE" is introduced. +This enum property has blob id's as values. With each blob id representing +a distinct color pipeline based on underlying HW capabilities and their +respective combinations. + +The following output of drm_info [1], shows how color pipelines are visible +to userspace. + +├───Plane 0 + │ ├───Object ID: 31 + │ ├───CRTCs: {0} + │ ├───Legacy info + ... + │ ├───"GET_COLOR_PIPELINE" (immutable): enum {no color pipeline, + color pipeline 1, color pipeline 2}= no color pipeline + +To understand the capabilities of individual pipelines, first the userspace +need to retrieve the pipeline blob with the blob ids retrieved by reading the +enum property. + +Once the color pipeline is retrieved, user can then parse through +individual drm_color_op blocks to understand the capabilities of each +hardware block. + +Check IGT series to see how user space can parse through color pipelines. +Refer the IGT series here: https://patchwork.freedesktop.org/series/123018/ + +Setting up a color pipeline +=========================== + +Once the user space decides on a color pipeline, it can set the pipeline and +the corresponding data for the hardware blocks within the pipeline with +the BLOB property "SET_COLOR_PIPELINE". + +To achieve this two structures are introduced + +1. struct drm_color_op_data: It represents data to be passed onto individual + color hardware blocks. It contains three members + a) name: to identify the color operation block + b) blob_id: pointing to the blob with data for the + corresponding hardware block + + struct drm_color_op_data { + enum color_op_block name; + u32 blob_id; + }; + +2. struct drm_color_pipeline: This structure represents the aggregate + pipeline to be set. it contains the following members + a) num: pipeline number to be selected + b) size: size of the data to be passed onto the driver + c) data: array of struct drm_color_op_data with data for + the hardware block/s that userspace wants to + set values for. + + struct drm_color_pipeline { + int num; + int size; + struct drm_color_op_data *data; + }; + + User can either: + 1. send data for all the color operations in a pipeline as shown in [2]. + The color operation data need not be in order that the pipeline advertises + however, it should not contain data for any + color operation that is not present in the pipeline. + + Note: This check for pipeline is not yet implemented but if the + wider proposal is accepted we have few solutions in mind. + + 2. send data for a subset of color operations as shown in [3].For the + color operation that userspace does not send data will retain their + older state. + + 3. reset/disable the pipeline by setting the "SET_COLOR_PIPELINE" blob + property to NULL as shown in both [2] and [3] + + 4. change the color pipeline as demonstrated in [3]. + On the new pipeline, the user is expected to setup all the color hardware block + Once the user requests a pipeline change, the driver will provide it a clean slate + which means that all the data previously set by the user will be discarded even if + there are common hardware blocks between the two(previous and current) pipelines. + +IGT implementation can be found here [4] + +Representing Fixed function hardware +==================================== + +To provide support for fixed function hardware, the driver could expose vendor +specific struct drm_color_op with parameters that both the userspace and +driver agrees on. To demonstrate, let's consider a hyphothetical fixed +function hardware block that converts BT601 to BT2020. +The driver can choose to advertise the block as such. + +struct drm_color_op color_pipeline_X[] = { + { + .name = DRM_CB_PRIVATE, + .type = FIXED_FUNCTION, + .blob_id = 45; + }, +} + +Where the blob represents some vendor specific enums, strings or any other +appropriate data types which both the user-space and drivers are aligned on. + +blob:45 { + VENDORXXX_BT602_TO_BT2020, +}; + +For enabling or passing parameters to such blocks, the user can send data +to the driver wrapped within a blob like any other color operation block. + + struct drm_color_op_data { + .name = DRM_CB_PRIVATE; + .blob_id = 46; + } ; + +where blob with id 46 contains data to enable the fixed function hardware(s). + +References +========== + +[1] https://gitlab.freedesktop.org/emersion/drm_info +[2] https://patchwork.freedesktop.org/patch/554827/?series=123018&rev=1 +[3] https://patchwork.freedesktop.org/patch/554826/?series=123018&rev=1 +[4] https://patchwork.freedesktop.org/series/123018/ From patchwork Tue Aug 29 16:03:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369122 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F17E4C83F12 for ; Tue, 29 Aug 2023 15:59:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5364D10E3D1; Tue, 29 Aug 2023 15:58:56 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id A0F9110E3CF; Tue, 29 Aug 2023 15:58:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324728; x=1724860728; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5Qp097ctCLHkcAcTxQXD4sQQnKT9TKGccAFF/oQntIc=; b=VKh2Gq920WrdQx4BUzgud5bkjU7gdoLPxez7T97kn8JGK3Y1DhPvNvDk nHtY9l3h69kiH7sDu8a/z4mVO4Wi2MxeNCmM6QZ9Xbdv/qgCcDLxapFKu 9JSvAVODJ9UcI9Pnz97+roHjOuXU1+Ji2TlYcAaE41uXLBuf8FENMbP+u m1kVFRWbiOR7Cf9wB79hem2120dKgwESgUbpgo4LqF8nw/p0gkD0ToJCE 4MZ8wwRcWF+RrF0YQrjSRZX7w1IJyG23baZ/SjqnfBMor5xngU5ACf8le B6UDx9jWG0BUE1dIMtriqgl9FP6h+ehPMfzw7VOVsKBudDGMi/718ZILg w==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769188" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769188" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:58:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688554912" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688554912" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:58:46 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 02/33] drm: Add color operation structure Date: Tue, 29 Aug 2023 21:33:51 +0530 Message-ID: <20230829160422.1251087-3-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chaitanya Kumar Borah Each Color Hardware block will be represented uniquely in the color pipeline. Define the structure to represent the same. These color operations will form the building blocks of a color pipeline which best represents the underlying Hardware. Color operations can be re-arranged, substracted or added to create distinct color pipelines to accurately describe the Hardware blocks present in the display engine. Co-developed-by: Uma Shankar Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- include/uapi/drm/drm_mode.h | 72 +++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index ea1b639bcb28..882479f41745 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -943,6 +943,78 @@ struct hdr_output_metadata { }; }; +/** + * enum color_op_block + * + * Enums to identify hardware color blocks. + * + * @DRM_CB_PRE_CSC: LUT before the CTM unit + * @DRM_CB_CSC: CTM hardware supporting 3x3 matrix + * @DRM_CB_POST_CSC: LUT after the CTM unit + * @DRM_CB_3D_LUT: LUT hardware with coefficients for all + * color components + * @DRM_CB_PRIVATE: Vendor specific hardware unit. Vendor + * can expose a custom hardware by defining a + * color operation block with this name as + * identifier + */ +enum color_op_block { + DRM_CB_INVAL = -1, + + DRM_CB_PRE_CSC = 0, + DRM_CB_CSC, + DRM_CB_POST_CSC, + DRM_CB_3D_LUT, + + /* Any new generic hardware block can be updated here */ + + /* + * PRIVATE is kept at 255 to make it future proof and leave + * scope for any new addition + */ + DRM_CB_PRIVATE = 255, + DRM_CB_MAX = DRM_CB_PRIVATE, +}; + +/** + * enum color_op_type + * + * These enums are to identify the mathematical operation that + * a hardware block is capable of. + * @CURVE_1D: It represents a one dimensional lookup table + * @CURVE_3D: Represents lut value for each color component for 3d lut capable hardware + * @MATRIX: It represents co-efficients for a CSC/CTM matrix hardware + * @FIXED_FUNCTION: To enable and program any custom fixed function hardware unit + */ +enum color_op_type { + CURVE_1D, + CURVE_3D, + MATRIX, + FIXED_FUNCTION, +}; + +/** + * @struct drm_color_op + * + * This structure is used to represent the capability of + * individual color hardware blocks. + * + * @name: a standardized enum to identify the color hardware block + * @type: The type of mathematical operation it can perform + * @blob_id: Id pointing to a blob containing information about + * the hardware block which advertizes its capabilities + * to the userspace. It can be an optional field depending + * on the members "name" and "type". + * @private_flags: This can be used to provide vendor specific hints + * to user space + */ +struct drm_color_op { + enum color_op_block name; + enum color_op_type type; + __u32 blob_id; + __u32 private_flags; +}; + /** * DRM_MODE_PAGE_FLIP_EVENT * From patchwork Tue Aug 29 16:03:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369123 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 013EDC6FA8F for ; Tue, 29 Aug 2023 15:59:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E8C610E3DB; Tue, 29 Aug 2023 15:58:57 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id D1C6910E3C9; Tue, 29 Aug 2023 15:58:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324730; x=1724860730; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ks/6Ptti4eurEareDUW5/GmLuij5qSCK1TgsQsJBBS8=; b=OAWLOmMqIDFyka4XRVrE8iL8a/5GyAI6u46J1MOxCH8mWZjUpO6pBh6I A37YoA9zPVXDRLbarW/Rkbq0vU8F9OuAeMMNS79WhSzXJGr2JIRJdfoZT IXLfwjDAKf8WvCPNHq71NWSr7FFNZQI5Fma6lzYaYV7kkP2G7LiBoQLAo 2qpEgaOJYOH4W5u3q62EsHHEFM9tq7XtdGnH++MKLUpOPBECXKrPEo7R8 YCTof6VmXGX864LAc3Gw6HDyQkVaqrj7RLXiZzw6whSQh83YPLx2FoP3F RGTGxJjiSAPPkOqkHB+HHjyidtJAmUHLDy9Gb6no16Z1SavcThbxjyw4E A==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769204" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769204" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:58:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688554933" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688554933" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:58:48 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 03/33] drm: Add plane get color pipeline property Date: Tue, 29 Aug 2023 21:33:52 +0530 Message-ID: <20230829160422.1251087-4-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chaitanya Kumar Borah Each hardware plane can consist of multiple color hardware blocks. These hardware blocks are defined by a color pipeline. In case, hardware blocks can be re-arranged/muxed a distinct pipeline can be defined to represent the same. Introduce a new enum plane property "GET_COLOR_PIPELINE" to expose the color pipelines that a particular plane supports. This enum property has blob id's as values. With each blob id representing a distinct color pipeline based on underlying HW capabilities and their respective combinations. Add helpers to create and attach the property to a plane. Co-developed-by: Uma Shankar Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/drm_color_mgmt.c | 46 ++++++++++++++++++++++++++++++++ include/drm/drm_plane.h | 10 +++++++ 2 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index d021497841b8..026d057d1f1f 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -588,6 +588,52 @@ int drm_plane_create_color_properties(struct drm_plane *plane, } EXPORT_SYMBOL(drm_plane_create_color_properties); +/** + * drm_plane_create_get_color_pipeline_property - create property to expose color pipelines + * @dev: DRM device + * @plane: plane object + * @num_val: number of color pipelines supported + * + * create enum property to expose color pipelines to userspace. This enum + * property has blob id's as values. With each blob id representing + * a distinct color pipeline based on underlying HW capabilities and + * their respective combinations. + */ +int drm_plane_create_get_color_pipeline_property(struct drm_device *dev, + struct drm_plane *plane, + int num_val) +{ + struct drm_property *prop; + + prop = drm_property_create(dev, DRM_MODE_PROP_ENUM | + DRM_MODE_PROP_IMMUTABLE, + "GET_COLOR_PIPELINE", num_val); + if (!prop) + return -ENOMEM; + + plane->get_color_pipeline_prop = prop; + + return 0; +} +EXPORT_SYMBOL(drm_plane_create_get_color_pipeline_property); + +/** + * drm_plane_attach_get_color_pipeline_property - attach get color pipeline property to a plane + * @plane: plane object + * + * Attach "GET_COLOR_PIPELINE" property to a plane. The property will be visible to + * the userspace once we attach the property. + */ +void drm_plane_attach_get_color_pipeline_property(struct drm_plane *plane) +{ + if (!plane->get_color_pipeline_prop) + return; + + drm_object_attach_property(&plane->base, + plane->get_color_pipeline_prop, 0); +} +EXPORT_SYMBOL(drm_plane_attach_get_color_pipeline_property); + /** * drm_color_lut_check - check validity of lookup table * @lut: property blob containing LUT to check diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 79d62856defb..256c97ead698 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -748,6 +748,12 @@ struct drm_plane { * scaling. */ struct drm_property *scaling_filter_property; + + /** + * @get_color_pipeline_prop: Optional Plane property to get the color pipelines + * that the plane supports + */ + struct drm_property *get_color_pipeline_prop; }; #define obj_to_plane(x) container_of(x, struct drm_plane, base) @@ -945,5 +951,9 @@ drm_plane_get_damage_clips(const struct drm_plane_state *state); int drm_plane_create_scaling_filter_property(struct drm_plane *plane, unsigned int supported_filters); +int drm_plane_create_get_color_pipeline_property(struct drm_device *dev, + struct drm_plane *plane, + int num_val); +void drm_plane_attach_get_color_pipeline_property(struct drm_plane *plane); #endif From patchwork Tue Aug 29 16:03:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369121 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9A9DC83F14 for ; Tue, 29 Aug 2023 15:59:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 55B2D10E3D7; Tue, 29 Aug 2023 15:58:56 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id DB6AC10E3D6; Tue, 29 Aug 2023 15:58:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324732; x=1724860732; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gMnns/I+M8dtpSyv33inv7RJyJ4Y6bB3ZfRrxD5OPS4=; b=PtHqgsD/xTcPr1EQyfht3XR+XWm4OkwvyEoAG3q+oQUpZEqSjgtPn8qZ kJxffWqA/hxR1lv7L1wbvuSxINtubg8dbUa6ZIGjiY+5vNY4OiF9OLBwC NoroUsLhKQYtuC/WtVVu8J76wjkG2f6JyZMSmQbuzh+MVFDyIUNV3xT7w yqFfBysKeroTTAKHDU0mN/nZpvYQdNJYHzxF+IJLzjJ4vP4pLHQUS7wJ1 rNHKgB4jIwu+AZ6N5yQFJdDaxlT2FmraMjN+9tnzyHDY16Eyct3yJtloa EzsBcNlj2vQG/CbA/Zwm36MNqqBxyOv63zOHLHUzD0Qqgg9u0WSt4/EJv w==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769215" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769215" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:58:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688554953" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688554953" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:58:50 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 04/33] drm: Add helper to add color pipeline Date: Tue, 29 Aug 2023 21:33:53 +0530 Message-ID: <20230829160422.1251087-5-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chaitanya Kumar Borah Create a helper function to add a color pipeline for a plane. Color pipeline is an array of struct drm_color_op which represent a possible logical combination of color operations. Color operations can be re-arranged, substracted or added to create distinct color pipelines to accurately describe the Hardware blocks present in the display engine. Co-developed-by: Uma Shankar Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/drm_color_mgmt.c | 42 ++++++++++++++++++++++++++++++++ include/drm/drm_plane.h | 3 +++ 2 files changed, 45 insertions(+) diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 026d057d1f1f..43d0187faa98 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -634,6 +634,48 @@ void drm_plane_attach_get_color_pipeline_property(struct drm_plane *plane) } EXPORT_SYMBOL(drm_plane_attach_get_color_pipeline_property); +/** + * drm_plane_add_color_pipeline - helper to add a color pipeline + * @plane: plane object + * @name: name of the color pipeline + * @color_pipeline: an array of 'struct drm_color_op' to represent a color pipeline + * @len: size of the color pipeline + * + * This helper can be used to add a distinct color pipeline to a plane. A driver + * can provide a meaningful name to the pipeline as it desires. + */ +int drm_plane_add_color_pipeline(struct drm_plane *plane, char *name, + struct drm_color_op *color_pipeline, + size_t len) +{ + int ret; + struct drm_property *prop; + struct drm_property_blob *blob; + u32 id = 0; + + prop = plane->get_color_pipeline_prop; + + if (color_pipeline && !len) + return -EINVAL; + + if (color_pipeline) { + blob = drm_property_create_blob(plane->dev, len, color_pipeline); + if (IS_ERR(blob)) + return PTR_ERR(blob); + + id = blob->base.id; + }; + + ret = drm_property_add_enum(prop, id, name); + if (ret) { + if (blob) + drm_property_blob_put(blob); + return ret; + } + return 0; +} +EXPORT_SYMBOL(drm_plane_add_color_pipeline); + /** * drm_color_lut_check - check validity of lookup table * @lut: property blob containing LUT to check diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 256c97ead698..ffd7887c2acf 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -955,5 +955,8 @@ int drm_plane_create_get_color_pipeline_property(struct drm_device *dev, struct drm_plane *plane, int num_val); void drm_plane_attach_get_color_pipeline_property(struct drm_plane *plane); +int drm_plane_add_color_pipeline(struct drm_plane *plane, char *name, + struct drm_color_op *color_pipeline, + size_t len); #endif From patchwork Tue Aug 29 16:03:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369124 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 68C7EC83F18 for ; Tue, 29 Aug 2023 15:59:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D43ED10E3E1; Tue, 29 Aug 2023 15:58:58 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id A632B10E3D1; Tue, 29 Aug 2023 15:58:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324734; x=1724860734; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hbW9+YdA04nud4kbR3D2ODKFMs+DMFvhK3hsr9+XUUU=; b=RqT4LrLALaHkOt00ek0H8TngoauvAdwA/4HrcMd3X1zY87sqpCiGD0TE bPknC10iQhspOW0YkDer8i8QhWMpYEGemqjOniO67JzuB0VIYAN7sxNxn fKhiIbescRy714UP2T6cBkxYwF9fX0nIzM8L4NS/aw7zDzZuPboWvgVxo zei67EVumpJfkgrqTOVTGI1usOk4J2G7FMkGPLjitkx/YcKHevnCXlb6H ga4DcL5M47tDaV0ZBwqB5lVT9FE1WR3rVS72EEWl0fRPeqeoKiMvujOot oXjQkN87TXEU+d0bFF5uyfk4VNAum+Z1fso0TGOq2MjuXx666ci5haPfE g==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769223" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769223" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:58:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688554964" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688554964" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:58:52 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 05/33] drm: Add structures for setting color pipeline Date: Tue, 29 Aug 2023 21:33:54 +0530 Message-ID: <20230829160422.1251087-6-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add structures using which user space can set a color pipeline it desires. The patch introduces two structures struct drm_color_op_data represents data to be passed onto individual color hardware blocks. struct drm_color_pipeline represents the aggregate of drm_color_op_data structures to program the respective color hardware blocks of the pipeline. It also contains the pipeline number to be set. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- include/uapi/drm/drm_mode.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 882479f41745..a21825ee93e2 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -1015,6 +1015,36 @@ struct drm_color_op { __u32 private_flags; }; +/** + * struct drm_color_op_data + * + * Structure for userspace to send data to a particular color operation + * block. + * + * @name: Name of the color block for which the data is being sent + * @blob_id: Id pointing to blob with data for the color operation block + */ +struct drm_color_op_data { + enum color_op_block name; + __u32 blob_id; +}; + +/** + * struct drm_color_pipeline + * + * This structure represents the aggregate pipeline to be set + * + * @num: pipeline number to be selected + * @size: size of the data to be passed onto the driver + * @data: array of struct drm_color_op_data with data for the + * hardware block/s that user space wants to set values for + */ +struct drm_color_pipeline { + int num; + int size; + struct drm_color_op_data *data; +}; + /** * DRM_MODE_PAGE_FLIP_EVENT * From patchwork Tue Aug 29 16:03:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED34FC6FA8F for ; Tue, 29 Aug 2023 15:59:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 923C810E3CC; Tue, 29 Aug 2023 15:59:05 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id C4D7E10E3D6; Tue, 29 Aug 2023 15:58:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324736; x=1724860736; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pECIUcai/xvs+H32dYiF4qVFleTcHmcDoMYY+bCO1Ms=; b=OUyiUBue4U7upQ0taJnlfpRCRKQsN1xaqCXV1i3B2zFdKhyHDDsy4E8K k3LP0lb+/OFYrQLykOMNxLuhUR2OJq2xjTcWM8m1NG3E7Zz6t6SK6sOaC VvRR5ZERWCVMdjeVy+Mojq/S3FGO9hpCAjlyoLf00kZfSOxCNaMB//aSG BiSOAEmKyNmhQVnYo+oKYHYllW0IXfY6NqvJbP8d2VsQi4U5wjbCVzPaC kXvl6yEpJuelCGhFkS/hBVunbtBIPKdWmO0aSKmAc47vUAXpmAiGSY1MI KcwUvaVHjfDm0K10Wg8reKpZ8KsEeloQlpfdGMmwcnCDlRhaXDkySQsO5 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769232" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769232" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:58:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688554983" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688554983" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:58:54 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 06/33] drm: Add set colorpipeline property Date: Tue, 29 Aug 2023 21:33:55 +0530 Message-ID: <20230829160422.1251087-7-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a new plane blob property "SET_COLOR_PIPELINE" using which the user can select a color pipeline and send data for corresponding hardware blocks. Once the user space decides on a color pipeline, it can set the pipeline and corresponding data for the hardware blocks within the pipeline. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- drivers/gpu/drm/drm_atomic_uapi.c | 12 +++++++++ drivers/gpu/drm/drm_color_mgmt.c | 42 +++++++++++++++++++++++++++++++ include/drm/drm_plane.h | 22 ++++++++++++++++ 3 files changed, 76 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 98d3b10c08ae..a2d3393d21a2 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -590,6 +590,15 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, return ret; } else if (property == plane->scaling_filter_property) { state->scaling_filter = val; + } else if (property == plane->set_color_pipeline_prop) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->set_color_pipeline_data, + val, + -1, + sizeof(struct drm_color_pipeline), + &replaced); + state->color_mgmt_changed |= replaced; + return ret; } else if (plane->funcs->atomic_set_property) { return plane->funcs->atomic_set_property(plane, state, property, val); @@ -651,6 +660,9 @@ drm_atomic_plane_get_property(struct drm_plane *plane, state->fb_damage_clips->base.id : 0; } else if (property == plane->scaling_filter_property) { *val = state->scaling_filter; + } else if (property == plane->set_color_pipeline_prop) { + *val = (state->set_color_pipeline_data) ? + state->set_color_pipeline_data->base.id : 0; } else if (plane->funcs->atomic_get_property) { return plane->funcs->atomic_get_property(plane, state, property, val); } else { diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c index 43d0187faa98..3ef58da94556 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c @@ -634,6 +634,48 @@ void drm_plane_attach_get_color_pipeline_property(struct drm_plane *plane) } EXPORT_SYMBOL(drm_plane_attach_get_color_pipeline_property); +/** + * drm_plane_create_set_color_pipeline_property - create property to set color pipeline + * @dev: DRM device + * @plane: plane object + * + * create blob property using which the user space can set up a plane color pipeline. + * Userspace can send data for one or multiple hardware blocks in the pipeline. + */ +int drm_plane_create_set_color_pipeline_property(struct drm_device *dev, + struct drm_plane *plane) +{ + struct drm_property *prop; + + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB, + "SET_COLOR_PIPELINE", 0); + if (!prop) + return -ENOMEM; + + plane->set_color_pipeline_prop = prop; + + return 0; +} +EXPORT_SYMBOL(drm_plane_create_set_color_pipeline_property); + +/** + * drm_plane_attach_set_color_pipeline_property - attach set color pipeline property to a plane + * @plane: plane object + * + * Attach "SET_COLOR_PIPELINE" property to a plane. The property will be visible to + * the userspace once we attach the property. The default value is set to 0 indicating + * no colorpipeline which essentially disables all the color HW blocks in the pipeline. + */ +void drm_plane_attach_set_color_pipeline_property(struct drm_plane *plane) +{ + if (!plane->set_color_pipeline_prop) + return; + + drm_object_attach_property(&plane->base, + plane->set_color_pipeline_prop, 0); +} +EXPORT_SYMBOL(drm_plane_attach_set_color_pipeline_property); + /** * drm_plane_add_color_pipeline - helper to add a color pipeline * @plane: plane object diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index ffd7887c2acf..fcd589cb38f2 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -237,6 +237,20 @@ struct drm_plane_state { /** @state: backpointer to global drm_atomic_state */ struct drm_atomic_state *state; + + /** + * @set_color_pipeline_data: + * + * Stores information about the current selected color pipeline + */ + struct drm_property_blob *set_color_pipeline_data; + + /** + * @color_mgmt_changed: Plane color pipeline state has changed + * Used by the atomic helpers and + * drivers to steer the atomic commit control flow. + */ + u8 color_mgmt_changed : 1; }; static inline struct drm_rect @@ -754,6 +768,11 @@ struct drm_plane { * that the plane supports */ struct drm_property *get_color_pipeline_prop; + + /** + * @set_color_pipeline_prop: Optional Plane property to set the color pipeline + */ + struct drm_property *set_color_pipeline_prop; }; #define obj_to_plane(x) container_of(x, struct drm_plane, base) @@ -955,6 +974,9 @@ int drm_plane_create_get_color_pipeline_property(struct drm_device *dev, struct drm_plane *plane, int num_val); void drm_plane_attach_get_color_pipeline_property(struct drm_plane *plane); +int drm_plane_create_set_color_pipeline_property(struct drm_device *dev, + struct drm_plane *plane); +void drm_plane_attach_set_color_pipeline_property(struct drm_plane *plane); int drm_plane_add_color_pipeline(struct drm_plane *plane, char *name, struct drm_color_op *color_pipeline, size_t len); From patchwork Tue Aug 29 16:03:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2418FC6FA8F for ; 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X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769240" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769240" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:58:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688554991" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688554991" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:58:56 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 07/33] drm: Add Enhanced Gamma LUT precision structure Date: Tue, 29 Aug 2023 21:33:56 +0530 Message-ID: <20230829160422.1251087-8-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Existing LUT precision structure is having only 16 bit precision. This is not enough for upcoming enhanced hardwares and advance usecases like HDR processing. Hence added a new structure with 32 bit precision values. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- include/uapi/drm/drm_mode.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index a21825ee93e2..1cd656b0e994 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -943,6 +943,23 @@ struct hdr_output_metadata { }; }; +/** + * struct drm_color_lut_ext - Represents high precision lut values + * + * Creating 64 bit palette entries for better data + * precision. This will be required for HDR and + * similar color processing usecases. + */ +struct drm_color_lut_ext { + /* + * Data is U32.32 fixed point format. + */ + __u64 red; + __u64 green; + __u64 blue; + __u64 reserved; +}; + /** * enum color_op_block * From patchwork Tue Aug 29 16:03:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8085C83F12 for ; Tue, 29 Aug 2023 15:59:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2685F10E3E6; Tue, 29 Aug 2023 15:59:06 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7FC5810E3E2; Tue, 29 Aug 2023 15:59:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324740; x=1724860740; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FB7ss4kmHop2yaKxXN25+gcSbQ8RmW+Dh4y7g/Bgb5o=; b=RRN+8jELxiRNyqp2ZeAZgYcJZEm5bZAF6L9P/5qZJUMdFOMzRjTLwOJn gxtR6ZpA1bRILLq4WPbIoNS9Sd7bELeIVgDo4LgUlr2owwU5E4gAi5DKc +HR4ZlLpsm46xtfx7311AlnWS2CPj/CuhhAcTTvsxVx3lRMCOcBYXChTc 8LvtTLc86Ut6z+fRJeuEUsff02wdvjH+BY8XZ7uH63+D8j0z3WfEd6cNb UJbXMKgEh4iY/YnnkugdT+LYdeXZkIWIYp5MnPHdpa75ok/I05ydmoZ0E f36KKADNUf2NnyIJBxfl4a50rTmdLVbgdnyajKlxkpVUrEPe83girAEVi g==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769251" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769251" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688554994" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688554994" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:58:58 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 08/33] drm: Add color lut range structure Date: Tue, 29 Aug 2023 21:33:57 +0530 Message-ID: <20230829160422.1251087-9-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add color lut range structure which is to be used to advertize the capabilities of pre-csc/post-csc color operation blocks. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- include/uapi/drm/drm_mode.h | 77 +++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 1cd656b0e994..6ce7bd0926e0 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -1091,6 +1091,83 @@ struct drm_color_pipeline { DRM_MODE_PAGE_FLIP_ASYNC | \ DRM_MODE_PAGE_FLIP_TARGET) +/** + * DRM_MODE_LUT_POST_CSC + * + * LUT is for post csc (after CTM) + */ +#define DRM_MODE_LUT_POST_CSC BIT(0) + +/** + * DRM_MODE_LUT_PRE_CSC + * + * LUT is for pre csc (before CTM) + */ +#define DRM_MODE_LUT_PRE_CSC BIT(1) + +/** + * DRM_MODE_LUT_INTERPOLATE + * + * linearly interpolate between the points + */ +#define DRM_MODE_LUT_INTERPOLATE BIT(2) + +/** + * DRM_MODE_LUT_REUSE_LAST + * + * the last value of the previous range is the + * first value of the current range. + */ +#define DRM_MODE_LUT_REUSE_LAST BIT(3) + +/** + * DRM_MODE_LUT_NON_DECREASING + * + * the curve must be non-decreasing + */ +#define DRM_MODE_LUT_NON_DECREASING BIT(4) + +/** + * DRM_MODE_LUT_REFLECT_NEGATIVE + * + * the curve is reflected across origin for negative inputs + */ +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(5) + +/** + * DRM_MODE_LUT_SINGLE_CHANNEL + * + * the same curve (red) is used for blue and green channels as well + */ +#define DRM_MODE_LUT_SINGLE_CHANNEL BIT(6) + +/** + * struct drm_color_lut_range + * + * structure to advertise capability of a color hardware + * block that accepts LUT values. It can represent LUTs with + * varied number of entries and distributions + * (Multi segmented, Logarithmic etc). + */ + +struct drm_color_lut_range { + /* DRM_MODE_LUT_* */ + __u32 flags; + /* number of points on the curve */ + __u16 count; + /* input/output bits per component */ + __u8 input_bpc, output_bpc; + /* input start/end values */ + __s32 start, end; + /* output min/max values */ + __s32 min, max; +}; + +enum lut_type { + LUT_TYPE_PRE_CSC = 0, + LUT_TYPE_POST_CSC = 1, +}; + /* * Request a page flip on the specified crtc. * From patchwork Tue Aug 29 16:03:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369128 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B632C6FA8F for ; Tue, 29 Aug 2023 15:59:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 07E3710E3DF; Tue, 29 Aug 2023 15:59:08 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6E10910E3DD; Tue, 29 Aug 2023 15:59:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324742; x=1724860742; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FTnaNI/dqfL0mN5AB3xSetNKJE1kZExcpPoMiYYhpds=; b=ISgcOQKKNPRjca/MLpzACLi0yW+YooOH5dar98eNT1hfdxvBMojAOfFR w3uIFVWwvvg/kW9b4bteTw6Wwt0fERCKqFH5RTeNxPjKdDmf9X3l5R4Go rHfmnzO3WxoLz1PX4yC84zywe6AoQXa67gxMewmWCLT9p7tfpUHjKiy1T BnQKxCq57LgU2oUnAk1hfSj7QOwg+U0FzWdL+NiIfd57376MPyBX17Rxv XRRU3X04ec3Il3JYhz8995lpqsa/4o6jhICHMRLPUqEhsQ+8XyUbljcyA 7na1PTmPUmyCQFQcZYcdrMRuU7d8r0P8LRnWoglNJ6ITVqVbvMCh2mwUj Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769266" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769266" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688554999" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688554999" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:00 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 09/33] drm: Add color information to plane state Date: Tue, 29 Aug 2023 21:33:58 +0530 Message-ID: <20230829160422.1251087-10-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add a new structure drm_plane_color to plane state. It consists of blobs with data needed for respective color HW blocks. Currently defining below blobs pre-csc: can be used to linearize the input frame buffer data. csc: used for color space conversion. post-csc: can be used non-linearize frame buffer data or to perform Tone mapping for HDR use-cases private: can be used for vendor specific fixed function operations This can be extended to include other color operations as well. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- include/drm/drm_plane.h | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index fcd589cb38f2..601b01e47a93 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -245,6 +245,47 @@ struct drm_plane_state { */ struct drm_property_blob *set_color_pipeline_data; + /** + * @drm_plane_color: + * + * Encapsulates all color states. + */ + struct drm_plane_color { + /** + * @pre_csc_lut: + * + * Lookup table for converting framebuffer pixel data before apply the + * color conversion matrix @ctm. See drm_plane_enable_color_mgmt(). The + * blob (if not NULL) is an array of &struct drm_color_lut_ext. + */ + struct drm_property_blob *pre_csc_lut; + + /** + * @ctm: + * + * Color transformation matrix. See drm_plane_enable_color_mgmt(). The + * blob (if not NULL) is a &struct drm_color_ctm. + */ + struct drm_property_blob *ctm; + + /** + * @post_csc_lut: + * + * Lookup table for converting framebuffer pixel data after applying the + * color conversion matrix @ctm. See drm_plane_enable_color_mgmt(). The + * blob (if not NULL) is an array of &struct drm_color_lut_ext. + */ + struct drm_property_blob *post_csc_lut; + + /** + * @private_color_op_data: + * + * This blob is intended for drivers to implement driver private color operations. + * For example: Parameterized/non-parameterized fixed function operations + */ + struct drm_property_blob *private_color_op_data; + } color; + /** * @color_mgmt_changed: Plane color pipeline state has changed * Used by the atomic helpers and From patchwork Tue Aug 29 16:03:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369133 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83503C83F12 for ; Tue, 29 Aug 2023 16:00:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E271710E3F5; Tue, 29 Aug 2023 15:59:16 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6654810E3E5; Tue, 29 Aug 2023 15:59:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324744; x=1724860744; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R61xpepqKpYQimlj4K6h7jVYR2oEcisvx/uzlHcstBE=; b=c9zEm7VHESDSd5+Euxqb/0KPzcWUz7Q/TKOtm6khnZOinmVvGENaxVYK vXZhNv05iufnrKPhsXgtxeL2PtZZAiEBRG7z0YjVjKneXyU08KgUZI/HC IQ2vw85COwg6dNFY+Z7ARNc47wxgSjl3n1pAmfKAjSVyDI0bBL0l3q+9S MU9OccbQsh5c/ay/CJR83dlD+jyKlQedQEYGpNVCtCrJJX5azNT5TYahH MPDCr4LaP76LpUGyOZYx+0XKYF0KWB9lLJ18EitNLW7AFg40k8zvBdv9p ol8s8tolX/F+LXMk/Wt7b0zf9zuk8o2LX4mEce4sDhdifogUnTPKCnSdl Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769281" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769281" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555005" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555005" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:02 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 10/33] drm: Manage color blob states Date: Tue, 29 Aug 2023 21:33:59 +0530 Message-ID: <20230829160422.1251087-11-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chaitanya Kumar Borah This patch manages the references for color blobs. Co-developed-by: Uma Shankar Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/drm_atomic_state_helper.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index 784e63d70a42..a554e04c2ce3 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -338,6 +338,19 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, state->fence = NULL; state->commit = NULL; state->fb_damage_clips = NULL; + + if (state->set_color_pipeline_data) + drm_property_blob_get(state->set_color_pipeline_data); + if (state->color.pre_csc_lut) + drm_property_blob_get(state->color.pre_csc_lut); + if (state->color.ctm) + drm_property_blob_get(state->color.ctm); + if (state->color.post_csc_lut) + drm_property_blob_get(state->color.post_csc_lut); + if (state->color.private_color_op_data) + drm_property_blob_get(state->color.private_color_op_data); + + state->color_mgmt_changed = false; } EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state); @@ -384,6 +397,11 @@ void __drm_atomic_helper_plane_destroy_state(struct drm_plane_state *state) drm_crtc_commit_put(state->commit); drm_property_blob_put(state->fb_damage_clips); + drm_property_blob_put(state->set_color_pipeline_data); + drm_property_blob_put(state->color.pre_csc_lut); + drm_property_blob_put(state->color.ctm); + drm_property_blob_put(state->color.post_csc_lut); + drm_property_blob_put(state->color.private_color_op_data); } EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state); From patchwork Tue Aug 29 16:04:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369130 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8BA94C83F18 for ; Tue, 29 Aug 2023 16:00:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6083110E3FC; Tue, 29 Aug 2023 15:59:17 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7E50610E3EA; Tue, 29 Aug 2023 15:59:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324746; x=1724860746; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cPWdhNLT68jHg/LMORxacdjWiK4TIkQARfJU1hq3OP4=; b=NRT64M3Ml/kDBdhxhgfcW6Mscbt73RY2pBZXKVXp68XbqQo6BPg33L64 TttVc9LhuX0ky0V0tZscQnXYaS7eOxa6QMfK6AoZmHxVwWdg/qyFwFmMI 7hPIqC/Om5r8bjUOs/0f2tq+erLaHN3KNQjd4JwHYiJeqdDnO+E5Wm7rW S+7/hU+CChm2EzYROqwj+rDm0MA7CDdRMoE6CznrPDmUYHJiLq+QoQwmS 6Q+Fi8Qik/ow7rKmw1ShoCyV6LkbFqeGGz7DlPTX32AQPqf0j8DZnkG7l FK0pQ3Av4le0Q1CNs09wLktQv02tl2HCOBsukt4L2w1tE/heGc0CEIwCI g==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769294" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769294" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555010" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555010" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:04 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 11/33] drm: Replace individual color blobs Date: Tue, 29 Aug 2023 21:34:00 +0530 Message-ID: <20230829160422.1251087-12-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chaitanya Kumar Borah Replace the color operation blobs depending on the values sent by userspace. Co-developed-by: Uma Shankar Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/drm_atomic_uapi.c | 97 +++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index a2d3393d21a2..20f9366865ca 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -404,6 +404,92 @@ drm_atomic_replace_property_blob_from_id(struct drm_device *dev, return 0; } +/* + * Helper to replace individual color blobs for a plane. The function + * changes all the color blobs sent by userspace agnostic of the color + * pipeline chosen. Since, the information about color pipeline is + * available at driver level, the driver should check for + * the sanity of the userspace data. + */ +static +int drm_plane_replace_color_op_blobs(struct drm_plane *plane, + struct drm_plane_state *state, + uint64_t color_pipeline_blob_id, + bool *replaced) +{ + struct drm_device *dev = plane->dev; + struct drm_property_blob *new_blob; + struct drm_color_pipeline *color_pipeline; + struct drm_color_op_data *color_op; + int ret = 0, i; + bool blob_replaced = false; + bool temp_replaced = false; + + new_blob = drm_property_lookup_blob(dev, color_pipeline_blob_id); + + if (!new_blob) { + ret = -EINVAL; + goto out; + } + + color_pipeline = new_blob->data; + color_op = kzalloc(color_pipeline->size, GFP_KERNEL); + if (!color_op) { + ret = -ENOMEM; + goto mem_fail; + } + + if (copy_from_user(color_op, color_pipeline->data, color_pipeline->size)) { + ret = -EFAULT; + goto copy_fail; + } + + for (i = 0; i < color_pipeline->size / sizeof(struct drm_color_op_data); i++) { + if (color_op[i].name == DRM_CB_CSC) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->color.ctm, + color_op[i].blob_id, + -1, sizeof(struct drm_color_ctm), + &blob_replaced); + } else if (color_op[i].name == DRM_CB_PRE_CSC) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->color.pre_csc_lut, + color_op[i].blob_id, + -1, sizeof(struct drm_color_lut_ext), + &blob_replaced); + } else if (color_op[i].name == DRM_CB_POST_CSC) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->color.post_csc_lut, + color_op[i].blob_id, + -1, sizeof(struct drm_color_lut_ext), + &blob_replaced); + } else if (color_op[i].name == DRM_CB_PRIVATE) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->color.private_color_op_data, + color_op[i].blob_id, + -1, -1, + &blob_replaced); + } else { + ret = -EINVAL; + goto copy_fail; + } + + if (ret) + goto copy_fail; + + temp_replaced |= blob_replaced; + } + +copy_fail: + kfree(color_op); +mem_fail: + drm_property_blob_put(new_blob); +out: + if (!ret) + *replaced |= temp_replaced; + return ret; +} + static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, struct drm_crtc_state *state, struct drm_property *property, uint64_t val) @@ -597,6 +683,17 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, -1, sizeof(struct drm_color_pipeline), &replaced); + if (replaced) { + /* Consider actual color parameter change only when + * individual color blobs are replaced. Hence, reset + * the replaced boolean. + */ + replaced = false; + ret = drm_plane_replace_color_op_blobs(plane, state, + val, + &replaced); + } + state->color_mgmt_changed |= replaced; return ret; } else if (plane->funcs->atomic_set_property) { From patchwork Tue Aug 29 16:04:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7034C83F12 for ; Tue, 29 Aug 2023 15:59:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 797BC10E3F2; Tue, 29 Aug 2023 15:59:11 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id A5B6510E3EA; Tue, 29 Aug 2023 15:59:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324748; x=1724860748; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DY7p5m0Mj5iFffaF3e2ykVgUwXzAxhI951ITRXu05p8=; b=e/nABQsKYlxp2j0MpOGKSiZU7cHDEmKGs+z+rfr1tnwODK/PlqLgY+ys 1PPo0My4LGoZMqfmnQ1IGdo9ijE8SSOVorrS8axeK0cjDC1T1XJDBXgvp QK93YJ9v8FlWf+zytQJ/gSEwSswwUYJ8ZC2VFf2Wps1StYL4vZkKN2ddt GQZRzB3rXFvwHwLarK4Zu4MJ9bazFF14yVXCVVdLEd3rgFLvDpCSctVQ+ 8UkxV5wHxOFIVcU6iQuTvYKRIeNY1nEGSOlmRWjzABMQ3ksSHoilr6SA+ hOiKBh7OAzBZaE6Tz9kpuvPEpREpurWxxZtFnEILJMobWo0kQ/pfDv9vK g==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769309" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769309" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555015" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555015" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:06 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 12/33] drm: Reset pipeline when user sends NULL blob Date: Tue, 29 Aug 2023 21:34:01 +0530 Message-ID: <20230829160422.1251087-13-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chaitanya Kumar Borah User can disable the color pipeline entirely, thereby disabling all the color hardware blocks in the pipeline. User should set NULL as the blob id and invoke SET_COLOR_PIPELINE property. Driver will disable all the color hardware blocks by updating respective blob id's as NULL. Co-developed-by: Uma Shankar Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/drm_atomic_uapi.c | 50 +++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 20f9366865ca..259cd4f5f520 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -411,6 +411,53 @@ drm_atomic_replace_property_blob_from_id(struct drm_device *dev, * available at driver level, the driver should check for * the sanity of the userspace data. */ +static +int drm_plane_reset_color_op_blobs(struct drm_plane *plane, + struct drm_plane_state *state, + bool *replaced) +{ + struct drm_device *dev = plane->dev; + int ret; + bool blob_replaced = false; + bool temp_replaced = false; + + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->color.ctm, + 0, -1, -1, + &blob_replaced); + temp_replaced |= blob_replaced; + if (ret) + goto out; + + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->color.pre_csc_lut, + 0, -1, -1, + &blob_replaced); + temp_replaced |= blob_replaced; + + if (ret) + goto out; + + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->color.post_csc_lut, + 0, -1, -1, + &blob_replaced); + temp_replaced |= blob_replaced; + + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->color.private_color_op_data, + 0, -1, -1, + &blob_replaced); + temp_replaced |= blob_replaced; + + if (ret) + goto out; +out: + if (!ret) + *replaced |= temp_replaced; + return ret; +} + static int drm_plane_replace_color_op_blobs(struct drm_plane *plane, struct drm_plane_state *state, @@ -425,6 +472,9 @@ int drm_plane_replace_color_op_blobs(struct drm_plane *plane, bool blob_replaced = false; bool temp_replaced = false; + if (!color_pipeline_blob_id) + return drm_plane_reset_color_op_blobs(plane, state, replaced); + new_blob = drm_property_lookup_blob(dev, color_pipeline_blob_id); if (!new_blob) { From patchwork Tue Aug 29 16:04:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369131 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EEB95C6FA8F for ; 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X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769329" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769329" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555022" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555022" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:08 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 13/33] drm: Reset plane color state on pipeline switch request Date: Tue, 29 Aug 2023 21:34:02 +0530 Message-ID: <20230829160422.1251087-14-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chaitanya Kumar Borah When a pipeline switch is requested by user, driver resets blobs for all the hardware blocks to get to clean state. These are then populated with the new blob id's as programmed by user. For the already enabled hardware blocks, if the user does not add entry in the new switch request, the blob id's will remain NULL eventually resulting in disabling of that hardware block. Co-developed-by: Uma Shankar Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/drm_atomic_uapi.c | 52 ++++++++++++++++++++++++++++--- 1 file changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 259cd4f5f520..9e0fb36d1f47 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -362,6 +362,38 @@ static s32 __user *get_out_fence_for_connector(struct drm_atomic_state *state, return fence_ptr; } +static +bool color_pipeline_change_requested(struct drm_device *dev, + struct drm_property_blob *plane_cp_set_blob, + uint64_t blob_id) +{ + bool is_change_requested = false; + struct drm_property_blob *new_blob = NULL; + struct drm_color_pipeline *old_cp, *new_cp; + + /* + * User is setting the pipeline for the first time + */ + if (!plane_cp_set_blob) + goto out; + + old_cp = plane_cp_set_blob->data; + + if (blob_id != 0) { + new_blob = drm_property_lookup_blob(dev, blob_id); + if (!new_blob) + goto out; + + new_cp = new_blob->data; + + if (old_cp->num != new_cp->num) + is_change_requested = true; + } + drm_property_blob_put(new_blob); +out: + return is_change_requested; +} + static int drm_atomic_replace_property_blob_from_id(struct drm_device *dev, struct drm_property_blob **blob, @@ -727,6 +759,12 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, } else if (property == plane->scaling_filter_property) { state->scaling_filter = val; } else if (property == plane->set_color_pipeline_prop) { + bool cp_change_requested; + + cp_change_requested = color_pipeline_change_requested(dev, + state->set_color_pipeline_data, + val); + ret = drm_atomic_replace_property_blob_from_id(dev, &state->set_color_pipeline_data, val, @@ -736,12 +774,18 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, if (replaced) { /* Consider actual color parameter change only when * individual color blobs are replaced. Hence, reset - * the replaced boolean. + * the replaced boolean but first reset all color + * blobs if color pipeline change is requested. */ + if (val && cp_change_requested) + ret = drm_plane_reset_color_op_blobs(plane, + state, &replaced); replaced = false; - ret = drm_plane_replace_color_op_blobs(plane, state, - val, - &replaced); + if (!ret) { + ret = drm_plane_replace_color_op_blobs(plane, state, + val, + &replaced); + } } state->color_mgmt_changed |= replaced; From patchwork Tue Aug 29 16:04:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369132 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70F75C83F14 for ; Tue, 29 Aug 2023 16:00:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B9EAC10E3FA; Tue, 29 Aug 2023 15:59:16 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id D5BC510E3E8; Tue, 29 Aug 2023 15:59:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324753; x=1724860753; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BkxhWwqLWw1PpEAtRsRC2Xy4hh82FaCIhbvRnJtc4Jg=; b=YQRauQT8GripLRVixjPMOD8c/E1ZEES15uwCo0/sXaFbGMSPE7nwa6vv A+D+xOYVRreNtc6LjiJv+KO94aaOsZ4I7kvJPs419JhVJMfVWc34RfiCS DREBNMLIzPN6M5A9nsLjeD3KOa4BB3mXflck4k2elFoQmxU/9gij/lmvc GoyTPrOO0xLYFmqc6o+Q3MJY08UgW6bR/NnapAShEvCU2URuh+pGa6r8a pFFT1eB0EhsL64cqF94qDOzExN41FguHLuBKb7WsiafaZyzww+MY47O3m 1Hsr4AtRYNPt/d2uDqTko8GWSl40Y4s7YgzoWKriQkaix22c42gHU6vFG w==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769338" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769338" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555026" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555026" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:10 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 14/33] drm/i915/color: Add lut range for SDR planes Date: Tue, 29 Aug 2023 21:34:03 +0530 Message-ID: <20230829160422.1251087-15-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add lut range information for SDR planes. This is used to hint the userspace what kind of LUT values are needed by the hardware block. Pre-CSC and Post-CSC blocks have similar lut range for HDR planes. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 5918e2e9bcdd..3900e3748a0e 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3778,6 +3778,61 @@ static const struct intel_color_funcs ilk_color_funcs = { .get_config = ilk_get_config, }; +/* FIXME input bpc? */ +static const struct drm_color_lut_range xelpd_pre_post_csc_sdr[] = { + /* segment 1 */ + { + .flags = (DRM_MODE_LUT_POST_CSC | + DRM_MODE_LUT_PRE_CSC | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_NON_DECREASING), + .count = 32, + .input_bpc = 16, .output_bpc = 16, + .start = 0, .end = (1 << 16) - (1 << 16) / 33, + .min = 0, .max = (1 << 16) - 1, + }, + /* segment 2 */ + { + .flags = (DRM_MODE_LUT_POST_CSC | + DRM_MODE_LUT_PRE_CSC | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 16, .output_bpc = 16, + .start = (1 << 16) - (1 << 16) / 33, .end = 1 << 16, + .min = 0, .max = 1 << 16, + }, + /* Segment 3 */ + { + .flags = (DRM_MODE_LUT_POST_CSC | + DRM_MODE_LUT_PRE_CSC | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 16, .output_bpc = 16, + .start = 1 << 16, .end = 3 << 16, + .min = 0, .max = (8 << 16) - 1, + }, + /* Segment 4 */ + { + .flags = (DRM_MODE_LUT_POST_CSC | + DRM_MODE_LUT_PRE_CSC | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 16, .output_bpc = 16, + .start = 3 << 16, .end = 7 << 16, + .min = 0, .max = (8 << 16) - 1, + }, +}; + void intel_color_crtc_init(struct intel_crtc *crtc) { struct drm_i915_private *i915 = to_i915(crtc->base.dev); From patchwork Tue Aug 29 16:04:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369138 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72958C6FA8F for ; Tue, 29 Aug 2023 16:00:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F08610E40B; Tue, 29 Aug 2023 15:59:36 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id A934210E3F3; Tue, 29 Aug 2023 15:59:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324754; x=1724860754; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rZoQ12nkjZqZBdVH2w4FJnuG3YN7ZC9A0VOAsDYnMbU=; b=JfM3q0gPyO92BQ78nPIBK9tIKgQ4B5rWZt944hGQ+D5301EDjkG10+HP 4qFR+yxYUyvIda7ZkxNfEwJ2MflfkQ2HiUhJ4zkeE/71CjU1nxQnRHdid CTsLGCqO3Vez3UfB+wT2VbWYGlKdXsGpJWsEItvnRzSHto+COrZwyWxZ1 x1vAStWr4jrNN1XEDEvv7CXtzK2JMvan0CgfV87mMFYTzP0opH6se8Bm7 +ByRFutqbKaBRNnwmZjvlRgxMi4+7X95tu1+0damcLtEfCnlFZ0UFLTvd i65CpPnn14oY/vlNirRPXfKVi20te+JB8C+ncdkyIPlXYP/j2sskoGEDg w==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769347" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769347" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555029" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555029" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:12 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 15/33] drm/i915/color: Add lut range for HDR planes Date: Tue, 29 Aug 2023 21:34:04 +0530 Message-ID: <20230829160422.1251087-16-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add lut range information for HDR planes. This is used to hint the userspace what kind of LUT values are needed by the hardware block. Pre-CSC and Post-CSC blocks have different lut ranges for HDR planes. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 108 +++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 3900e3748a0e..58b6d70043ca 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3833,6 +3833,114 @@ static const struct drm_color_lut_range xelpd_pre_post_csc_sdr[] = { }, }; +/* FIXME input bpc? */ +static const struct drm_color_lut_range xelpd_pre_csc_hdr[] = { + /* segment 1 */ + { + .flags = (DRM_MODE_LUT_PRE_CSC | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_NON_DECREASING), + .count = 128, + .input_bpc = 24, .output_bpc = 16, + .start = 0, .end = (1 << 24) - 1, + .min = 0, .max = (1 << 24) - 1, + }, + /* segment 2 */ + { + .flags = (DRM_MODE_LUT_PRE_CSC | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 24) - 1, .end = 1 << 24, + .min = 0, .max = (1 << 27) - 1, + }, + /* Segment 3 */ + { + .flags = (DRM_MODE_LUT_PRE_CSC | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = 1 << 24, .end = 3 << 24, + .min = 0, .max = (1 << 27) - 1, + }, + /* Segment 4 */ + { + .flags = (DRM_MODE_LUT_PRE_CSC | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = 3 << 24, .end = 7 << 24, + .min = 0, .max = (1 << 27) - 1, + }, +}; + +/* FIXME input bpc? */ +static const struct drm_color_lut_range xelpd_post_csc_hdr[] = { + /* + * ToDo: Add Segment 1 + * There is an optional fine segment added with 9 lut values + * Will be added later + */ + + /* segment 2 */ + { + .flags = (DRM_MODE_LUT_POST_CSC | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_NON_DECREASING), + .count = 32, + .input_bpc = 24, .output_bpc = 16, + .start = 0, .end = (1 << 24) - 1, + .min = 0, .max = (1 << 24) - 1, + }, + /* segment 3 */ + { + .flags = (DRM_MODE_LUT_POST_CSC | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = (1 << 24) - 1, .end = 1 << 24, + .min = 0, .max = 1 << 24, + }, + /* Segment 4 */ + { + .flags = (DRM_MODE_LUT_POST_CSC | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = 1 << 24, .end = 3 << 24, + .min = 0, .max = (3 << 24), + }, + /* Segment 5 */ + { + .flags = (DRM_MODE_LUT_POST_CSC | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_REUSE_LAST | + DRM_MODE_LUT_NON_DECREASING), + .count = 1, + .input_bpc = 24, .output_bpc = 16, + .start = 3 << 24, .end = 7 << 24, + .min = 0, .max = (7 << 24), + }, +}; + void intel_color_crtc_init(struct intel_crtc *crtc) { struct drm_i915_private *i915 = to_i915(crtc->base.dev); From patchwork Tue Aug 29 16:04:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369135 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3EA08C83F12 for ; Tue, 29 Aug 2023 16:00:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F1B0010E405; Tue, 29 Aug 2023 15:59:33 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id B64EB10E3F9; Tue, 29 Aug 2023 15:59:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324756; x=1724860756; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yCz85V0J2Ysvr38Yvcu/hreFnr217mkusD+0CH7N0I4=; b=dp16Ia8Jrn6DJXH3o5c3ZxF1VC4aQnzaGtLBUbrXoWSpfZLGg2WedIEA Ihp9qiIgdf5uPxLMh3ezyfVR5ZE/0dLXAUTvohKa+QMOr06syYVA8y4Bl fhhiX8+JSdpda2L9M0AjYuUVLSNCM8XQ9UsWkKu03TPze4yz1Tib7VF8I MqOp83RthxvNV5TNDKz5B7pX1OzkFAWMKQEh3fsMSVeq68uHz5Z/DdigC 0rNbv3V1BY4Wod+RVVaJu+i/rd+Y4yejm0PINvPvqg49V5cyvfYJ1Qr42 P1DmIg+IAKXRrU7VQAPuNtyxIOacNk3dAAwJQQcyCUs7WiYDIuBoer9oP A==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769353" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769353" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555033" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555033" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:14 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 16/33] drm/i915/color: Add color pipeline for HDR planes Date: Tue, 29 Aug 2023 21:34:05 +0530 Message-ID: <20230829160422.1251087-17-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add color pipeline for HDR planes. It consists of the following hardware blocks. * Pre-CSC : This block can used to linearize the input frame buffer data. The linear data then can be further acted on by the following color hardware blocks in the display hardware pipeline * CSC/CTM: Used to program color transformation matrix, this block is used to perform color space conversions like BT2020 to BT709 or BT601 etc. This block acts on the linearized data coming from the Pre-CSC HW block. * Post-CSC: This HW block can be used to non-linearize frame buffer data to match the sink. Another use case of it could be to perform Tone mapping for HDR use-cases. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 58b6d70043ca..8c2a858fc452 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3941,6 +3941,24 @@ static const struct drm_color_lut_range xelpd_post_csc_hdr[] = { }, }; +struct drm_color_op color_pipeline_hdr[] = { + { + .name = DRM_CB_PRE_CSC, + .type = CURVE_1D, + .blob_id = 0, /* To be updated during plane initialization */ + }, + { + .name = DRM_CB_CSC, + .type = MATRIX, + .blob_id = 0, + }, + { + .name = DRM_CB_POST_CSC, + .type = CURVE_1D, + .blob_id = 0, + }, +}; + void intel_color_crtc_init(struct intel_crtc *crtc) { struct drm_i915_private *i915 = to_i915(crtc->base.dev); From patchwork Tue Aug 29 16:04:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369136 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 180D0C83F14 for ; Tue, 29 Aug 2023 16:00:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 68DB810E407; Tue, 29 Aug 2023 15:59:34 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 66FE510E3FE; Tue, 29 Aug 2023 15:59:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324758; x=1724860758; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uqt8nZVfkTLVOlfw6Y6F3d3wLOYoZSyIo9m9VYPPAKk=; b=bKHzAe+r5HfJPqFYmwxn5SgMkAww/C9f9t5ZPULlCZoO4u1nZsDPHw/5 M9s7FbGmwxbd1QEqW0H8n1mm+0e39Qg1oM+Y0i/nHURvZS6djDsX3SBdR i9suFpE6ur7Jp1L2gxB5V18cphI1KHF/Y6dmJ5D3bCFcCuUib7OydDkPo hkkpxNOhFAFzS+6l32RgJ1gHyCLkkrtdiJ4arHux/dMwNtpBfeCaI25cr NPfF2VKg1uaJyXnb8GeMX9HAhMYOEPODZw6qNq7mF0iMLvuixfWoLZsua hfWQsrgO7TB/E3keqc2cFC+cPx8U+jy74k7VT9aPIKLhB5HLPtO3G3+Gb w==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769365" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769365" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555038" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555038" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:16 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 17/33] drm/i915/color: Add color pipeline for SDR planes Date: Tue, 29 Aug 2023 21:34:06 +0530 Message-ID: <20230829160422.1251087-18-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" SDR planes provides programmable color hardware blocks for Pre-CSC and Post-CSC operations. Add a color pipeline to expose these capabilities. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 8c2a858fc452..09e50659befd 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3941,6 +3941,23 @@ static const struct drm_color_lut_range xelpd_post_csc_hdr[] = { }, }; +struct drm_color_op color_pipeline_sdr[] = { + { + .name = DRM_CB_PRE_CSC, + .type = CURVE_1D, + .blob_id = 0, /* To be updated during plane initialization */ + }, + /* + * SDR planes have fixed function CSC capabilities. + * TODO: Add support for it + */ + { + .name = DRM_CB_POST_CSC, + .type = CURVE_1D, + .blob_id = 0, + }, +}; + struct drm_color_op color_pipeline_hdr[] = { { .name = DRM_CB_PRE_CSC, From patchwork Tue Aug 29 16:04:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369137 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15E47C83F12 for ; Tue, 29 Aug 2023 16:00:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9932D10E408; Tue, 29 Aug 2023 15:59:34 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6219310E3ED; Tue, 29 Aug 2023 15:59:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324760; x=1724860760; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iwg4rBH4m7ug9GjBkFE9l0ehZa1pDqfiYiwxbl/iRmU=; b=jJwhkCDUO2boxoDUz5uy+eb1rwDeoEnTLf2leXj3bmtjdjA7A6vEkZig 9/0RtlHLPcHDhBaLgPgxfTVQ1Ez/GpsT3gU5x8uwEHoE4TfrE3G/xAY2l vT91FjEBKEdsuR7y9na1uw6zAwa4LHcFYxeg+RMdmwQpqatwNyDr1ku9S zY1ZuwM5nNcpCKJZC2xLC4uFNNbmvGD+2GoPEPvVvLxti9DQ8VhwmTQbt xOhu9/XkxnxEpL27ZjE/ha1FvMhxE+sl0RxMuDMsD8X2JpGyjwPqY+TM2 PLDq0PKh/Ca3ikz7l7ayhwXU0DQ3rSONdwAiBuxafNDk5qpcdcrnqENMX w==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769380" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769380" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555044" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555044" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:18 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 18/33] drm/i915/color: Add HDR plane LUT range data to color pipeline Date: Tue, 29 Aug 2023 21:34:07 +0530 Message-ID: <20230829160422.1251087-19-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chaitanya Kumar Borah Create a helper function to add details about LUT ranges that HDR planes can support. Userspace can parse through this information to generate proper LUT data for respective hardware blocks. It will be exposed to the user space by the color pipeline. Co-developed-by: Uma Shankar Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_color.c | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 09e50659befd..99ae3f4fca05 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -28,6 +28,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_dsb.h" +#include "skl_universal_plane.h" struct intel_color_funcs { int (*color_check)(struct intel_crtc_state *crtc_state); @@ -3976,6 +3977,52 @@ struct drm_color_op color_pipeline_hdr[] = { }, }; +__maybe_unused +static int intel_prepare_plane_color_pipeline(struct drm_plane *plane) +{ + struct drm_i915_private *i915 = to_i915(plane->dev); + struct drm_property_blob *blob[2] = {NULL}; + int ret = 0, i = 0; + + if (icl_is_hdr_plane(i915, to_intel_plane(plane)->id)) { + blob[i] = drm_property_create_blob(plane->dev, + sizeof(xelpd_pre_csc_hdr), + xelpd_pre_csc_hdr); + if (IS_ERR(blob[i])) { + ret = PTR_ERR(blob[i]); + goto out; + } + + /* + * In HDR color pipeline PRE-CSC and POST-CSC are positioned + * at 0th and 2nd index/position + */ + color_pipeline_hdr[0].blob_id = + blob[i++]->base.id; + + blob[i] = drm_property_create_blob(plane->dev, + sizeof(xelpd_post_csc_hdr), + xelpd_post_csc_hdr); + if (IS_ERR(blob[i])) { + ret = PTR_ERR(blob[i]); + goto out; + } + + color_pipeline_hdr[2].blob_id = + blob[i++]->base.id; + } + +out: + if (ret) { + for (int j = 0; j < i; j++) { + if (blob[j]) + drm_property_blob_put(blob[j]); + } + } + + return ret; +}; + void intel_color_crtc_init(struct intel_crtc *crtc) { struct drm_i915_private *i915 = to_i915(crtc->base.dev); From patchwork Tue Aug 29 16:04:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369134 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE0D0C83F14 for ; Tue, 29 Aug 2023 16:00:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CCF4210E404; Tue, 29 Aug 2023 15:59:31 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id DA3FD10E3F3; Tue, 29 Aug 2023 15:59:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324765; x=1724860765; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=93hDMXKlUVtM6dMv2jIX3mE572Gifj58PoXC1o3U6zU=; b=h45URntJOgcUcFF0ad8USYYhomcfmZa0RjelVTwK6a9K+5c3tnuXkzHl Rv/W3r5sN2a9mTqBAD7ZeZHW5GyZk9Gh4KmQHbYFJZvYxtp8JY9eOchDG A85Yk2tUg3+tP2dwFFZEdXrR3Efvt/ty1XWBuUdkftvewzYXEompgICrn ff0IOmgi+wBKsrAC5/a4DciYU4qVlAJ7OJz3ZQa+8Sp4AwXSt2l7iI6QG z45D88JNbL5HrykIOk6MrIeOLQClyZ60tMukBcFMITNlfhndHctMRF1BN LjorpNiYLiT8KMZq8xj/0cL3PJObEVxFOzT4K2Mu0PNQpTD+e3DGxUf+5 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769393" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769393" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555048" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555048" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:20 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 19/33] drm/i915/color: Add SDR plane LUT range data to color pipeline Date: Tue, 29 Aug 2023 21:34:08 +0530 Message-ID: <20230829160422.1251087-20-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chaitanya Kumar Borah Add LUT ranges for color blocks in SDR planes. Userspace can parse through this information to generate proper LUT data for respective hardware blocks. It will be exposed to the user space by the color pipeline. Co-developed-by: Uma Shankar Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_color.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 99ae3f4fca05..a8c6be70c859 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -4010,6 +4010,22 @@ static int intel_prepare_plane_color_pipeline(struct drm_plane *plane) color_pipeline_hdr[2].blob_id = blob[i++]->base.id; + } else { + blob[i] = drm_property_create_blob(plane->dev, + sizeof(xelpd_pre_post_csc_sdr), + xelpd_pre_post_csc_sdr); + if (IS_ERR(blob[i])) { + ret = PTR_ERR(blob[i]); + goto out; + } + + /* + * In SDR color pipeline PRE-CSC and POST-CSC blocks are positioned + * at 0th and 1st index/postion. + * LUT ranges for SDR planes are similar for pre and post-csc blocks + */ + color_pipeline_sdr[0].blob_id = + color_pipeline_sdr[1].blob_id = blob[i++]->base.id; } out: From patchwork Tue Aug 29 16:04:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 658ADC83F14 for ; Tue, 29 Aug 2023 16:00:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B72DC10E40D; Tue, 29 Aug 2023 15:59:54 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1A96510E409; Tue, 29 Aug 2023 15:59:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324786; x=1724860786; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8FLbUJPdobfYe9GU9gw7M3bXy57hVNJSuvEc7LwC3GQ=; b=Lqn9XqIydwWhYNzDNVpXfM6XsyxnJfsiFqHPk7NAQp8FwgF7XHrOGpFb vAa/e/UvRyOH15/1TcI6g9BRPm4riXSkXnye5KUaxmczste0gh+tEdo0H 264KBITfKbh1T6Lh4sK7qOiup1Z7F6SotcsKo9OAu7UCMLAX2V7hjPmfe GMZDxKYbPyG6/CqEHfph2n6qgWEOCW6hL8MgZ00/xfvgJSgH70XGGt0ch sOhGZEXp5WJMv5khBMcTrvCJquSWQOHlp9+mRaP4+ndsOALsGmPvNfcIv GmhDQgLIbTv2Jq1/HYOmnzc/b2LXS2t/raf6AFW9aoMEMzOx0Dn9z9vct Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769405" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769405" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555052" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555052" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:22 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 20/33] drm/i915/color: Add color pipelines to plane Date: Tue, 29 Aug 2023 21:34:09 +0530 Message-ID: <20230829160422.1251087-21-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chaitanya Kumar Borah Add supported plane color pipelines. To represent all hardware blocks in their inactive state, we introduce a pipeline called "no color pipeline" which is the default pipeline. Add respective color pipelines for SDR and HDR planes. Create and attach plane enum property "GET_COLOR_PIPELINE" to expose these pipelines to userspace. Co-developed-by: Uma Shankar Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_color.c | 31 +++++++++++++++++++++- drivers/gpu/drm/i915/display/intel_color.h | 3 ++- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index a8c6be70c859..9f5d2cd0f97a 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3977,7 +3977,6 @@ struct drm_color_op color_pipeline_hdr[] = { }, }; -__maybe_unused static int intel_prepare_plane_color_pipeline(struct drm_plane *plane) { struct drm_i915_private *i915 = to_i915(plane->dev); @@ -4039,6 +4038,36 @@ static int intel_prepare_plane_color_pipeline(struct drm_plane *plane) return ret; }; +__maybe_unused +void intel_color_plane_init(struct drm_plane *plane) +{ + struct drm_i915_private *i915 = to_i915(plane->dev); + + if (DISPLAY_VER(i915) < 13) + return; + + drm_plane_create_get_color_pipeline_property(plane->dev, plane, 2); + + intel_prepare_plane_color_pipeline(plane); + + /* + * default pipeline is set as 0 or "no color pipeline". All color h/w + * blocks are disabled at this stage. + */ + drm_plane_add_color_pipeline(plane, "no color pipeline", NULL, 0); + + if (icl_is_hdr_plane(i915, to_intel_plane(plane)->id)) + drm_plane_add_color_pipeline(plane, "color pipeline hdr", + color_pipeline_hdr, + sizeof(color_pipeline_hdr)); + else + drm_plane_add_color_pipeline(plane, "color pipeline sdr", + color_pipeline_sdr, + sizeof(color_pipeline_sdr)); + + drm_plane_attach_get_color_pipeline_property(plane); +} + void intel_color_crtc_init(struct intel_crtc *crtc) { struct drm_i915_private *i915 = to_i915(crtc->base.dev); diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h index 8002492be709..aa649d13c6fa 100644 --- a/drivers/gpu/drm/i915/display/intel_color.h +++ b/drivers/gpu/drm/i915/display/intel_color.h @@ -10,6 +10,7 @@ struct intel_crtc_state; struct intel_crtc; +struct drm_plane; struct drm_i915_private; struct drm_property_blob; @@ -29,5 +30,5 @@ bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state, const struct drm_property_blob *blob2, bool is_pre_csc_lut); void intel_color_assert_luts(const struct intel_crtc_state *crtc_state); - +void intel_color_plane_init(struct drm_plane *plane); #endif /* __INTEL_COLOR_H__ */ From patchwork Tue Aug 29 16:04:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369140 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42486C6FA8F for ; Tue, 29 Aug 2023 16:00:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F14A10E40E; Tue, 29 Aug 2023 15:59:55 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4B08A10E40A; Tue, 29 Aug 2023 15:59:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324792; x=1724860792; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L496O12+gCB8MunXy6XwdLI99hzyun8QY3tnp7ytVO8=; b=bHDBISU1hvC/h5A8/Qp3Jp4c53cmKVtGi5UkHMVQSqxfJblN7srj50Aw p6hyiLiyfO59Y8IzDj3+rA+PYpbGQ22NWQPTFpHsLYXTsgVaIy6q3YKx0 kvgPSFQfeA7LPishAZXaN6X8rIqO/uvIXnp6Lwe/Prom4bc6hUSnzkW47 Dil43iyRUZ6dSGEqu+xS4EBjWwoFcdReggA1G2ERQ1NA/tgKWRnOfrZql DmyeLf7GT8jBByrKbk1PGVY6jpgZIoShdtpx/08zE90rprLhlOAFVQZha EfqnD0Ll96pSOKT3R8z73kp8eHUwL3vlZJtS6s2b2eCAwKs5TwNLbUcuM w==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769421" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769421" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555056" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555056" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:24 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 21/33] drm/i915/color: Create and attach set color pipeline property Date: Tue, 29 Aug 2023 21:34:10 +0530 Message-ID: <20230829160422.1251087-22-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chaitanya Kumar Borah Create and attach "SET_COLOR_PIPELINE" property to planes. Co-developed-by: Uma Shankar Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_color.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 9f5d2cd0f97a..feff8ac45f47 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -4066,6 +4066,9 @@ void intel_color_plane_init(struct drm_plane *plane) sizeof(color_pipeline_sdr)); drm_plane_attach_get_color_pipeline_property(plane); + + drm_plane_create_set_color_pipeline_property(plane->dev, plane); + drm_plane_attach_set_color_pipeline_property(plane); } void intel_color_crtc_init(struct intel_crtc *crtc) From patchwork Tue Aug 29 16:04:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5FC9C83F12 for ; Tue, 29 Aug 2023 16:00:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9F16310E40A; Tue, 29 Aug 2023 15:59:55 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id DDBF310E3F6; Tue, 29 Aug 2023 15:59:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324792; x=1724860792; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G80/t0E+Y7X7UG/FuuAwrW8sEE/xYeufMdF4yveur7o=; b=OIknZ0eweySJLcM7qjeKyNXhe9eLEeza4Q33z8br2pTlgP2T++8jlRq3 sHJNGkmkXupJFcDnk0nu8lYTzWjJx0Zy1jaKahw8CSxEH+yALo1Y1HT/C mIi1Ke2e4+INAFL3dLDBsn6VcsDKLr7VKYXbXi5iKrC0UrE/FCnvfaJxC Fathv7f/7Po6Pfk6307ttfQ1Mtc+2qMcY69QHzQYEGeSPJMP8Wt45voYv wKAJUkI5N+tHjUgEWYzsOYFuMn5GuzoB6skZuedc/azQlUVnFMW/ZbsQJ mTx969B/U0s3gC8cBRMhNjx2MnGrktAudqeTN94BOt0QITgG3lB7yHOMX w==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769427" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769427" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555060" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555060" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:26 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 22/33] drm/i915/color: Add plane color callbacks Date: Tue, 29 Aug 2023 21:34:11 +0530 Message-ID: <20230829160422.1251087-23-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add callbacks for color plane operations. load_plane_luts: used to load pre/post csc luts load_plane_csc_matrix: used to load csc matrix Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index feff8ac45f47..faf16107d339 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -81,6 +81,12 @@ struct intel_color_funcs { * Read config other than LUTs and CSCs, before them. Optional. */ void (*get_config)(struct intel_crtc_state *crtc_state); + + /* + * Plane color callbacks + */ + void (*load_plane_csc_matrix)(const struct drm_plane_state *plane_state); + void (*load_plane_luts)(const struct drm_plane_state *plane_state); }; #define CTM_COEFF_SIGN (1ULL << 63) From patchwork Tue Aug 29 16:04:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369143 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB5D3C83F14 for ; Tue, 29 Aug 2023 16:00:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 82DE510E419; Tue, 29 Aug 2023 15:59:58 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 94D9F10E3F6; Tue, 29 Aug 2023 15:59:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324793; x=1724860793; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XKsz5W2ug/xIaYidDGFv+JT8hXUWr3ikaI14+0D8wDA=; b=OaZMbC3aTV2ogWPqIvzCnC7uHADo5uZfnERaxgEfhKrPkgktgj2KyRpw wAHzydrQ3fKDRG3V61i4+/gJF/rEBH2iLJRym7IkUAnxlEJiUdnBdBfNC MkgwWVzX3JsKswtRGrxQyhZE6UV3oTIwOIRKQOH5EGIvER8IcIR+H0iMJ xzq2+Zyov/hqQZcJQoH0aWQoLFNjTn1aT2NNnCfFwLyams/PRO7WYLC+E 0TFO3YHGU2lSk49dmE5nk5Gazb7x484i9aFv2LM8My2PP+IW2oT2ZMHiT IAAKYxqUdWsYzkhhzNcFhzfl9Q20lCsQbJ3/AptTLtvM0QGOONcl+oJQE Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769439" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769439" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555070" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555070" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:28 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 23/33] drm/i915/color: Load plane color luts from atomic flip Date: Tue, 29 Aug 2023 21:34:12 +0530 Message-ID: <20230829160422.1251087-24-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Load plane color luts as part of atomic plane updates. This will be done only if the plane color luts are changed. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 8 ++++++++ drivers/gpu/drm/i915/display/intel_color.h | 2 ++ drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 ++++ 3 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index faf16107d339..df2fc8f98dc9 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1863,6 +1863,14 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state) i915->display.funcs.color->load_luts(crtc_state); } +void intel_color_load_plane_luts(const struct drm_plane_state *plane_state) +{ + struct drm_i915_private *i915 = to_i915(plane_state->plane->dev); + + if (i915->display.funcs.color->load_plane_luts) + i915->display.funcs.color->load_plane_luts(plane_state); +} + void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h index aa649d13c6fa..93382df101d9 100644 --- a/drivers/gpu/drm/i915/display/intel_color.h +++ b/drivers/gpu/drm/i915/display/intel_color.h @@ -13,6 +13,7 @@ struct intel_crtc; struct drm_plane; struct drm_i915_private; struct drm_property_blob; +struct drm_plane_state; void intel_color_init_hooks(struct drm_i915_private *i915); int intel_color_init(struct drm_i915_private *i915); @@ -31,4 +32,5 @@ bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state, bool is_pre_csc_lut); void intel_color_assert_luts(const struct intel_crtc_state *crtc_state); void intel_color_plane_init(struct drm_plane *plane); +void intel_color_load_plane_luts(const struct drm_plane_state *plane_state); #endif /* __INTEL_COLOR_H__ */ diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 4566c95da1ca..ce7c367fe2da 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -11,6 +11,7 @@ #include "i915_drv.h" #include "i915_reg.h" #include "intel_atomic_plane.h" +#include "intel_color.h" #include "intel_de.h" #include "intel_display_irq.h" #include "intel_display_types.h" @@ -1268,6 +1269,9 @@ icl_plane_update_noarm(struct intel_plane *plane, if (plane_state->force_black) icl_plane_csc_load_black(plane); + if (plane_state->uapi.color_mgmt_changed) + intel_color_load_plane_luts(&plane_state->uapi); + intel_psr2_program_plane_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane); } From patchwork Tue Aug 29 16:04:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369142 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ED09BC83F12 for ; Tue, 29 Aug 2023 16:00:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF4F710E411; Tue, 29 Aug 2023 15:59:57 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 339C910E3F6; Tue, 29 Aug 2023 15:59:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324794; x=1724860794; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=tYg5lYB+tJMLJfNr78dxtogN6tMe17OacfEWMUp0UHI=; b=CBWfv8mTalrGFIdPwFS3FHgCTfaywWog2fTd0BfvCyZUy7TDrhU542LW eZxZZCFhyfPTlVTfP5/45yR5eHq69RDpPKXYbQvTOZ3sJPtKYTSed1hT3 Dm1qi6KtWYG0Lx1HEETIJENgk2tacbS1QO1JlesA0TZamiwucGpWNiIw8 4Sd5Kmi/wQWsJQ0DSgZEL6jAD/duF/IQ+YodWRYJJy99lARA3sO+sE2h0 0b8mIfh/c7PfFYfbfznqCAdIl3oGwb/hHTKZXFtnj5BwZfLlrvq3N0KI2 Tq1kBVfoS0vKQND/NxgeR+fwRrcjDXO9bevKOV2J6X59WnN50IrSuxohn A==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769443" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769443" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555087" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555087" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:30 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 24/33] drm/i915/xelpd: Add plane color check to glk_plane_color_ctl Date: Tue, 29 Aug 2023 21:34:13 +0530 Message-ID: <20230829160422.1251087-25-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Extended glk_plane_color_ctl to have plane color checks. This helps enabling the csc, degamma or gamma block based on user inputs. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 13 ++++++++++++- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index ce7c367fe2da..c08875fa965e 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -965,7 +965,18 @@ static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); u32 plane_color_ctl = 0; - plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; + /* FIXME needs hw.gamma_lut */ + if (!plane_state->uapi.color.pre_csc_lut) + plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE; + + /* FIXME needs hw.degamma_lut */ + if (plane_state->uapi.color.post_csc_lut) + plane_color_ctl |= PLANE_COLOR_PRE_CSC_GAMMA_ENABLE; + + /* FIXME needs hw.ctm */ + if (plane_state->uapi.color.ctm) + plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE; + plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e00e4d569ba9..d50bfe1000d3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3730,6 +3730,7 @@ #define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) #define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) #define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) +#define PLANE_COLOR_PRE_CSC_GAMMA_ENABLE REG_BIT(14) #define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) #define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) From patchwork Tue Aug 29 16:04:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 909A5C83F14 for ; Tue, 29 Aug 2023 16:00:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D47B410E421; Tue, 29 Aug 2023 15:59:59 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 84B9910E40A; Tue, 29 Aug 2023 15:59:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324794; x=1724860794; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cvpcY2iePscV4T8xoYEZYxgs2BGhWDVtlGobxLU0hKI=; b=KrO4e63lidBuGCYQQOh+FPtbzlaTIxTQrMyL28991wfmwPW80iB1Si/L 836GAGPyXphY5uctCzt5iYIqsqEUNzmbz887Hp2z7ECxXIaMs4Z2gkoep u6XYHnqTQQyIuJZxLgvyhh4/tvX0HvlVRa9y0fjDGNs7Sag5uZPkEa1qd 2AEXBKVGB7jLWHnLywrsGJ/eGZCfEB8z56Y6qxxdm5qdN+WT9zRHa4fc7 hWa3xXIQki95xYmIKcFAAJ3tHeC6x9TWiDfCvfMc9k6czKieLuJE/lVK2 0AXxpZ95w3R45sRa3oxpNinObkpAVoiyTSkIvZWE/pmTgQTpwjeLWNLrE Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769451" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769451" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555107" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555107" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:32 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 25/33] drm/i915/xelpd: Add register definitions for Plane Degamma Date: Tue, 29 Aug 2023 21:34:14 +0530 Message-ID: <20230829160422.1251087-26-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add macros to define Plane Degamma registers Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 49 +++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d50bfe1000d3..5fa7461066ab 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6226,6 +6226,55 @@ enum skl_power_gate { #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) +/* Display13 Plane Degmma Reg */ +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x701d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x711d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A 0x702d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B 0x712d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A, \ + _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B) +#define _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_A, \ + _PLANE_PRE_CSC_GAMC_INDEX_ENH_2_B) +#define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \ + _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)) + +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A 0x701d4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B 0x711d4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A 0x702d4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B 0x712d4 +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A, \ + _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B) +#define _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_ENH_2_A, \ + _PLANE_PRE_CSC_GAMC_DATA_ENH_2_B) +#define PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_ENH_1(pipe), \ + _PLANE_PRE_CSC_GAMC_DATA_ENH_2(pipe)) + +#define _PLANE_PRE_CSC_GAMC_INDEX_1_A 0x704d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_1_B 0x714d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_2_A 0x705d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_2_B 0x715d0 +#define _PLANE_PRE_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_1_A, \ + _PLANE_PRE_CSC_GAMC_INDEX_1_B) +#define _PLANE_PRE_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_INDEX_2_A, \ + _PLANE_PRE_CSC_GAMC_INDEX_2_B) +#define PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_1(pipe), \ + _PLANE_PRE_CSC_GAMC_INDEX_2(pipe)) + +#define _PLANE_PRE_CSC_GAMC_DATA_1_A 0x704d4 +#define _PLANE_PRE_CSC_GAMC_DATA_1_B 0x714d4 +#define _PLANE_PRE_CSC_GAMC_DATA_2_A 0x705d4 +#define _PLANE_PRE_CSC_GAMC_DATA_2_B 0x715d4 +#define _PLANE_PRE_CSC_GAMC_DATA_1(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_1_A, \ + _PLANE_PRE_CSC_GAMC_DATA_1_B) +#define _PLANE_PRE_CSC_GAMC_DATA_2(pipe) _PIPE(pipe, _PLANE_PRE_CSC_GAMC_DATA_2_A, \ + _PLANE_PRE_CSC_GAMC_DATA_2_B) +#define PLANE_PRE_CSC_GAMC_DATA(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_DATA_1(pipe), \ + _PLANE_PRE_CSC_GAMC_DATA_2(pipe)) + /* Plane CSC Registers */ #define _PLANE_CSC_RY_GY_1_A 0x70210 #define _PLANE_CSC_RY_GY_2_A 0x70310 From patchwork Tue Aug 29 16:04:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369150 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0FD9C83F12 for ; Tue, 29 Aug 2023 16:01:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F72310E42F; Tue, 29 Aug 2023 16:00:13 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 754D910E3F6; Tue, 29 Aug 2023 15:59:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324795; x=1724860795; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jnrtTbHIlA7jcWZk+QTlZV5oxEPc3BTZwd7i8EI2OzI=; b=dTNHFYM8QqxqUPqubs+5oUkDKR93cZJ0MMpyr2nG6A4sX678Jc8/TLCA Hz6AfU6Vo461ZLU77Ah3I6qi2PfyjQbNx4eWWj0+YrvK2RO2+51tAx2Ca w9vo+6/zIfUYVSIPIo7O4t9jC9xdghHDxkv8r6MVK3mr5B074LracGKnR 1QjSRRLl01YkRNT7x9XGU3oCGzSWVC63rjuDxmqndqCcccMLQVCyNuma4 oK7q8sPAeysdI04mo2BAXXdy88/wrjvG9w5c7RFMBvLDaD2TSLpLv9qjj f+buIKw6FklTCMhwiwbogaUPuM2rTy21wJGegkC0uFoDar3o9aPFxHcAG w==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769456" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769456" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555123" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555123" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:34 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 26/33] drm/i915/color: Add color functions for ADL Date: Tue, 29 Aug 2023 21:34:15 +0530 Message-ID: <20230829160422.1251087-27-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Register color callbacks for ADL and beyond. While we have to register new callbacks for pre-blending color operations, re-use callbacks for post-blend operations. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index df2fc8f98dc9..3f3c1ac10330 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3704,6 +3704,16 @@ static const struct intel_color_funcs i9xx_color_funcs = { .get_config = i9xx_get_config, }; +static const struct intel_color_funcs xelpd_color_funcs = { + .color_check = icl_color_check, + .color_commit_noarm = icl_color_commit_noarm, + .color_commit_arm = icl_color_commit_arm, + .load_luts = icl_load_luts, + .read_luts = icl_read_luts, + .lut_equal = icl_lut_equal, + .read_csc = icl_read_csc, +}; + static const struct intel_color_funcs tgl_color_funcs = { .color_check = icl_color_check, .color_commit_noarm = icl_color_commit_noarm, @@ -4141,7 +4151,9 @@ void intel_color_init_hooks(struct drm_i915_private *i915) else i915->display.funcs.color = &i9xx_color_funcs; } else { - if (DISPLAY_VER(i915) >= 12) + if (DISPLAY_VER(i915) >= 13) + i915->display.funcs.color = &xelpd_color_funcs; + else if (DISPLAY_VER(i915) == 12) i915->display.funcs.color = &tgl_color_funcs; else if (DISPLAY_VER(i915) == 11) i915->display.funcs.color = &icl_color_funcs; From patchwork Tue Aug 29 16:04:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369145 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64AAAC83F14 for ; Tue, 29 Aug 2023 16:01:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D402B10E41E; Tue, 29 Aug 2023 16:00:10 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id D09BE10E40F; Tue, 29 Aug 2023 15:59:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324795; x=1724860795; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5Ws5Es71DzVgr1UntOP4MfujRZ0IKkLZq0t8bAledok=; b=S0ZYW8apkd6JugZ57v0Dy8661zMWiKsJkZ/zMm+Aj4So1pXgb7Dsw99m XjoBNdQxwuoDXGNXdE8i8HvVHK6I7W2GF8iNgdUXy/zEhqvlKMPs4hCIC sYBiqgS/kQjHjmcCLWOyHvydL6mffujw77jfK7s5cwsnmcTG6qthZBKkI GuFeAOThGR8zSqXGvNhtP6hc9ycP9G0fiFA6/sAoc/zqlzcACvEQQCmfs vS8Y7lowy/zGCtGkQVwsiyX+br7UuF/Q5zIbzxRUREYvYitfZX9v7tw/A fs+DjbD2L5n2kBDWK/SiZGYat73uEDSxcm47erZj3kbcsFBFh7QQCWJz3 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769460" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769460" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555143" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555143" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:36 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 27/33] drm/i915/color: Program Plane Pre-CSC Registers Date: Tue, 29 Aug 2023 21:34:16 +0530 Message-ID: <20230829160422.1251087-28-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Extract the LUT and program plane pre-csc registers. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 120 +++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 121 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 3f3c1ac10330..56bcf750b047 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -185,6 +185,29 @@ static bool lut_is_legacy(const struct drm_property_blob *lut) return lut && drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; } +/* + * Added to accommodate enhanced LUT precision. + * Max LUT precision is 32 bits. + */ +static u64 drm_color_lut_extract_ext(u64 user_input, u32 bit_precision) +{ + u64 val = user_input & 0xffffffff; + u32 max; + + if (bit_precision > 32) + return 0; + + max = 0xffffffff >> (32 - bit_precision); + /* Round only if we're not using full precision. */ + if (bit_precision < 32) { + val += 1UL << (32 - bit_precision - 1); + val >>= 32 - bit_precision; + } + + return ((user_input & 0xffffffff00000000) | + clamp_val(val, 0, max)); +} + /* * When using limited range, multiply the matrix given by userspace by * the matrix that we would use for the limited range. @@ -1856,6 +1879,102 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state) crtc_state->cgm_mode); } +static void xelpd_program_plane_pre_csc_lut(const struct drm_plane_state *state, + struct drm_color_lut_ext *pre_csc_lut, + u32 offset) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + u32 i, lut_size; + + if (icl_is_hdr_plane(dev_priv, plane)) { + lut_size = 128; + + intel_de_write_fw(dev_priv, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), + PLANE_PAL_PREC_AUTO_INCREMENT); + + if (pre_csc_lut) { + for (i = 0; i < lut_size; i++) { + u64 word = drm_color_lut_extract_ext(pre_csc_lut[i].green, 24); + u32 lut_val = (word & 0xffffff); + + intel_de_write_fw(dev_priv, + PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + lut_val); + } + + /* Program the max register to clamp values > 1.0. */ + while (i < 131) + intel_de_write_fw(dev_priv, + PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + pre_csc_lut[i++].green); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); + + intel_de_write_fw(dev_priv, + PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v); + } + + do { + intel_de_write_fw(dev_priv, + PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), + 1 << 24); + } while (i++ < 130); + } + + intel_de_write_fw(dev_priv, PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0); + } else { + lut_size = 32; + + /* + * First 3 planes are HDR, so reduce by 3 to get to the right + * SDR plane offset + */ + plane = plane - 3; + + intel_de_write_fw(dev_priv, PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, 0), + PLANE_PAL_PREC_AUTO_INCREMENT); + + if (pre_csc_lut) { + for (i = 0; i < lut_size; i++) + intel_de_write_fw(dev_priv, PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), + pre_csc_lut[i].green); + /* Program the max register to clamp values > 1.0. */ + while (i < 35) + intel_de_write_fw(dev_priv, PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), + pre_csc_lut[i++].green); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 16) - 1)) / (lut_size - 1); + + intel_de_write_fw(dev_priv, + PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), v); + } + + do { + intel_de_write_fw(dev_priv, PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0), + 1 << 16); + } while (i++ < 34); + } + + intel_de_write_fw(dev_priv, PLANE_PRE_CSC_GAMC_INDEX(pipe, plane, 0), 0); + } +} + +static void xelpd_plane_load_luts(const struct drm_plane_state *plane_state) +{ + const struct drm_property_blob *pre_csc_lut_blob = + plane_state->color.pre_csc_lut; + struct drm_color_lut_ext *pre_csc_lut = NULL; + + if (pre_csc_lut_blob) { + pre_csc_lut = pre_csc_lut_blob->data; + xelpd_program_plane_pre_csc_lut(plane_state, pre_csc_lut, 0); + } +} + void intel_color_load_luts(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); @@ -3712,6 +3831,7 @@ static const struct intel_color_funcs xelpd_color_funcs = { .read_luts = icl_read_luts, .lut_equal = icl_lut_equal, .read_csc = icl_read_csc, + .load_plane_luts = xelpd_plane_load_luts, }; static const struct intel_color_funcs tgl_color_funcs = { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5fa7461066ab..d26d6294d231 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6238,6 +6238,7 @@ enum skl_power_gate { #define PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, i) \ _MMIO_PLANE_GAMC(plane, i, _PLANE_PRE_CSC_GAMC_INDEX_ENH_1(pipe), \ _PLANE_PRE_CSC_GAMC_INDEX_ENH_2(pipe)) +#define PLANE_PAL_PREC_AUTO_INCREMENT REG_BIT(10) #define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_A 0x701d4 #define _PLANE_PRE_CSC_GAMC_DATA_ENH_1_B 0x711d4 From patchwork Tue Aug 29 16:04:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369146 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 548B7C6FA8F for ; Tue, 29 Aug 2023 16:01:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2930A10E42C; Tue, 29 Aug 2023 16:00:12 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3305D10E416; Tue, 29 Aug 2023 15:59:57 +0000 (UTC) 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X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555157" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:38 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 28/33] drm/i915/xelpd: Add register definitions for Plane Post CSC Date: Tue, 29 Aug 2023 21:34:17 +0530 Message-ID: <20230829160422.1251087-29-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add macros to define Plane Post CSC registers Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 73 +++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d26d6294d231..5e4271e7b735 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6226,6 +6226,79 @@ enum skl_power_gate { #define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) +/* Display13 Plane Gamma Reg */ +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A 0x70160 +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B 0x71160 +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A 0x70260 +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B 0x71260 +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_A, \ + _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1_B) +#define _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_A, \ + _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2_B) +#define PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_1(pipe), \ + _PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH_2(pipe)) + +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A 0x70164 +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B 0x71164 +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A 0x70264 +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B 0x71264 +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_A, \ + _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1_B) +#define _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_A, \ + _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2_B) +#define PLANE_POST_CSC_GAMC_SEG0_DATA_ENH(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_1(pipe), \ + _PLANE_POST_CSC_GAMC_SEG0_DATA_ENH_2(pipe)) + +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A 0x701d8 +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B 0x711d8 +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A 0x702d8 +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B 0x712d8 +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_1_A, \ + _PLANE_POST_CSC_GAMC_INDEX_ENH_1_B) +#define _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_ENH_2_A, \ + _PLANE_POST_CSC_GAMC_INDEX_ENH_2_B) +#define PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_ENH_1(pipe), \ + _PLANE_POST_CSC_GAMC_INDEX_ENH_2(pipe)) + +#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_A 0x701dc +#define _PLANE_POST_CSC_GAMC_DATA_ENH_1_B 0x711dc +#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_A 0x702dc +#define _PLANE_POST_CSC_GAMC_DATA_ENH_2_B 0x712dc +#define _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_1_A, \ + _PLANE_POST_CSC_GAMC_DATA_ENH_1_B) +#define _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_ENH_2_A, \ + _PLANE_POST_CSC_GAMC_DATA_ENH_2_B) +#define PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_ENH_1(pipe), \ + _PLANE_POST_CSC_GAMC_DATA_ENH_2(pipe)) + +#define _PLANE_POST_CSC_GAMC_INDEX_1_A 0x704d8 +#define _PLANE_POST_CSC_GAMC_INDEX_1_B 0x714d8 +#define _PLANE_POST_CSC_GAMC_INDEX_2_A 0x705d8 +#define _PLANE_POST_CSC_GAMC_INDEX_2_B 0x715d8 +#define _PLANE_POST_CSC_GAMC_INDEX_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_1_A, \ + _PLANE_POST_CSC_GAMC_INDEX_1_B) +#define _PLANE_POST_CSC_GAMC_INDEX_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_INDEX_2_A, \ + _PLANE_POST_CSC_GAMC_INDEX_2_B) +#define PLANE_POST_CSC_GAMC_INDEX(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_INDEX_1(pipe), \ + _PLANE_POST_CSC_GAMC_INDEX_2(pipe)) + +#define _PLANE_POST_CSC_GAMC_DATA_1_A 0x704dc +#define _PLANE_POST_CSC_GAMC_DATA_1_B 0x714dc +#define _PLANE_POST_CSC_GAMC_DATA_2_A 0x705dc +#define _PLANE_POST_CSC_GAMC_DATA_2_B 0x715dc +#define _PLANE_POST_CSC_GAMC_DATA_1(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_1_A, \ + _PLANE_POST_CSC_GAMC_DATA_1_B) +#define _PLANE_POST_CSC_GAMC_DATA_2(pipe) _PIPE(pipe, _PLANE_POST_CSC_GAMC_DATA_2_A, \ + _PLANE_POST_CSC_GAMC_DATA_2_B) +#define PLANE_POST_CSC_GAMC_DATA(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_POST_CSC_GAMC_DATA_1(pipe), \ + _PLANE_POST_CSC_GAMC_DATA_2(pipe)) + /* Display13 Plane Degmma Reg */ #define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_A 0x701d0 #define _PLANE_PRE_CSC_GAMC_INDEX_ENH_1_B 0x711d0 From patchwork Tue Aug 29 16:04:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369152 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31E7BC83F14 for ; Tue, 29 Aug 2023 16:01:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C9F2010E438; Tue, 29 Aug 2023 16:00:15 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id C271D10E414; Tue, 29 Aug 2023 15:59:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324797; x=1724860797; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PZ9YcLOC9X5oGxrhVOgeVRvJkh7ORpyVmvEZgbyqUTg=; b=XB69BLyIRvyq5zqTJJ2ksVtSPIV1T8Nkcp44YrqFCu3KESCEBbUZLM/R +tJYWVJ9zKaAMY9nEOIFmC/MJJ76EFJHapSOZXIPuNm11+rv6U08O+VHc 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Message-ID: <20230829160422.1251087-30-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Extract the LUT and program plane post csc registers. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 95 +++++++++++++++++++++- 1 file changed, 94 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 56bcf750b047..ff996b9ee77d 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1963,16 +1963,109 @@ static void xelpd_program_plane_pre_csc_lut(const struct drm_plane_state *state, } } +static void xelpd_program_plane_post_csc_lut(const struct drm_plane_state *state, + struct drm_color_lut_ext *post_csc_lut, + u32 offset) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + u32 i, lut_size; + + if (icl_is_hdr_plane(dev_priv, plane)) { + intel_de_write_fw(dev_priv, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), + offset | PLANE_PAL_PREC_AUTO_INCREMENT); + if (post_csc_lut) { + lut_size = 32; + for (i = 0; i < lut_size; i++) { + u64 word = drm_color_lut_extract_ext(post_csc_lut[i].green, 24); + u32 lut_val = (word & 0xffffff); + + intel_de_write_fw(dev_priv, + PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), + lut_val); + } + + do { + /* Program the max register to clamp values > 1.0. */ + intel_de_write_fw(dev_priv, + PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), + post_csc_lut[i].green); + } while (i++ < 34); + } else { + lut_size = 32; + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); + + intel_de_write_fw(dev_priv, + PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), v); + } + + do { + intel_de_write_fw(dev_priv, + PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), + 1 << 24); + } while (i++ < 34); + } + + intel_de_write_fw(dev_priv, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0); + } else { + lut_size = 32; + /* + * First 3 planes are HDR, so reduce by 3 to get to the right + * SDR plane offset + */ + plane = plane - 3; + + intel_de_write_fw(dev_priv, PLANE_POST_CSC_GAMC_INDEX(pipe, plane, 0), + offset | PLANE_PAL_PREC_AUTO_INCREMENT); + + if (post_csc_lut) { + for (i = 0; i < lut_size; i++) + intel_de_write_fw(dev_priv, + PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), + post_csc_lut[i].green & 0xffff); + /* Program the max register to clamp values > 1.0. */ + while (i < 35) + intel_de_write_fw(dev_priv, + PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), + post_csc_lut[i++].green & 0x3ffff); + } else { + for (i = 0; i < lut_size; i++) { + u32 v = (i * ((1 << 16) - 1)) / (lut_size - 1); + + intel_de_write_fw(dev_priv, + PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), v); + } + + do { + intel_de_write_fw(dev_priv, + PLANE_POST_CSC_GAMC_DATA(pipe, plane, 0), + (1 << 16)); + } while (i++ < 34); + } + + intel_de_write_fw(dev_priv, PLANE_POST_CSC_GAMC_INDEX(pipe, plane, 0), 0); + } +} + static void xelpd_plane_load_luts(const struct drm_plane_state *plane_state) { const struct drm_property_blob *pre_csc_lut_blob = plane_state->color.pre_csc_lut; - struct drm_color_lut_ext *pre_csc_lut = NULL; + const struct drm_property_blob *post_csc_lut_blob = + plane_state->color.post_csc_lut; + struct drm_color_lut_ext *pre_csc_lut, *post_csc_lut; if (pre_csc_lut_blob) { pre_csc_lut = pre_csc_lut_blob->data; xelpd_program_plane_pre_csc_lut(plane_state, pre_csc_lut, 0); } + + if (post_csc_lut_blob) { + post_csc_lut = post_csc_lut_blob->data; + xelpd_program_plane_post_csc_lut(plane_state, post_csc_lut, 0); + } } void intel_color_load_luts(const struct intel_crtc_state *crtc_state) From patchwork Tue Aug 29 16:04:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369147 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1A89C83F14 for ; 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X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769485" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769485" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555200" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555200" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:43 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 30/33] drm/i915/color: Enable Plane CSC Date: Tue, 29 Aug 2023 21:34:19 +0530 Message-ID: <20230829160422.1251087-31-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Implement plane CSC for Xe_LPD. Co-developed-by: Chaitanya Kumar Borah Signed-off-by: Chaitanya Kumar Borah Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 86 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_color.h | 1 + .../drm/i915/display/skl_universal_plane.c | 4 +- 3 files changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index ff996b9ee77d..956080fb7fcd 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -2068,6 +2068,83 @@ static void xelpd_plane_load_luts(const struct drm_plane_state *plane_state) } } +static void xelpd_load_plane_csc_matrix(const struct drm_plane_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + struct drm_color_ctm *ctm; + const u64 *input; + u16 coeffs[9] = {}; + u16 postoff = 0; + int i; + + if (!icl_is_hdr_plane(dev_priv, plane) || !state->color.ctm) + return; + + ctm = state->color.ctm->data; + input = ctm->matrix; + + /* + * Convert fixed point S31.32 input to format supported by the + * hardware. + */ + for (i = 0; i < ARRAY_SIZE(coeffs); i++) { + u64 abs_coeff = ((1ULL << 63) - 1) & input[i]; + + /* + * Clamp input value to min/max supported by + * hardware. + */ + abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1); + + /* sign bit */ + if (CTM_COEFF_NEGATIVE(input[i])) + coeffs[i] |= 1 << 15; + + if (abs_coeff < CTM_COEFF_0_125) + coeffs[i] |= (3 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 12); + else if (abs_coeff < CTM_COEFF_0_25) + coeffs[i] |= (2 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 11); + else if (abs_coeff < CTM_COEFF_0_5) + coeffs[i] |= (1 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 10); + else if (abs_coeff < CTM_COEFF_1_0) + coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9); + else if (abs_coeff < CTM_COEFF_2_0) + coeffs[i] |= (7 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 8); + else + coeffs[i] |= (6 << 12) | + ILK_CSC_COEFF_FP(abs_coeff, 7); + } + + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0), + coeffs[0] << 16 | coeffs[1]); + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1), + coeffs[2] << 16); + + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2), + coeffs[3] << 16 | coeffs[4]); + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3), + coeffs[5] << 16); + + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4), + coeffs[6] << 16 | coeffs[7]); + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5), + coeffs[8] << 16); + + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0); + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0); + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0); + + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 0), postoff); + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 1), postoff); + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2), postoff); +} + void intel_color_load_luts(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); @@ -2083,6 +2160,14 @@ void intel_color_load_plane_luts(const struct drm_plane_state *plane_state) i915->display.funcs.color->load_plane_luts(plane_state); } +void intel_color_load_plane_csc_matrix(const struct drm_plane_state *plane_state) +{ + struct drm_i915_private *i915 = to_i915(plane_state->plane->dev); + + if (i915->display.funcs.color->load_plane_csc_matrix) + i915->display.funcs.color->load_plane_csc_matrix(plane_state); +} + void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); @@ -3925,6 +4010,7 @@ static const struct intel_color_funcs xelpd_color_funcs = { .lut_equal = icl_lut_equal, .read_csc = icl_read_csc, .load_plane_luts = xelpd_plane_load_luts, + .load_plane_csc_matrix = xelpd_load_plane_csc_matrix, }; static const struct intel_color_funcs tgl_color_funcs = { diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h index 93382df101d9..a513c88d3bfc 100644 --- a/drivers/gpu/drm/i915/display/intel_color.h +++ b/drivers/gpu/drm/i915/display/intel_color.h @@ -33,4 +33,5 @@ bool intel_color_lut_equal(const struct intel_crtc_state *crtc_state, void intel_color_assert_luts(const struct intel_crtc_state *crtc_state); void intel_color_plane_init(struct drm_plane *plane); void intel_color_load_plane_luts(const struct drm_plane_state *plane_state); +void intel_color_load_plane_csc_matrix(const struct drm_plane_state *plane_state); #endif /* __INTEL_COLOR_H__ */ diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index c08875fa965e..c85548d3210a 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1280,8 +1280,10 @@ icl_plane_update_noarm(struct intel_plane *plane, if (plane_state->force_black) icl_plane_csc_load_black(plane); - if (plane_state->uapi.color_mgmt_changed) + if (plane_state->uapi.color_mgmt_changed) { intel_color_load_plane_luts(&plane_state->uapi); + intel_color_load_plane_csc_matrix(&plane_state->uapi); + } intel_psr2_program_plane_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane); } From patchwork Tue Aug 29 16:04:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 106A2C6FA8F for ; Tue, 29 Aug 2023 16:01:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF77510E431; Tue, 29 Aug 2023 16:00:14 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 241C110E41E; Tue, 29 Aug 2023 15:59:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324798; x=1724860798; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XwhxvOU3P16BtBGSMlwCxk6Zuwv0IuNz7yvBmEEaa6U=; b=heycHYv0ZZZKiXiCd1MC8909QmcWIi8RyTxdObwCUUYFIu8tRAq2gULf W3h4DMzw/TJBDUm1nH76Zqg5mthdb3Od4vqU2U5vcqnjdd7IqEXFWq/Z6 nToK6w8GGkrN/LqcxAuVx56LQLhY7f4y4cB515DUNmAEc+hmOboC8rGLg ENFrOomaRD9KwkfobZJClzgNXas66czJYXm6NMyHlADab5D6ZdtnV7OOL lKkkLCvIdQqMFOQdby5SQklVoQYPV1C3uVXztC4Ty2BXWS6S3igiACxKx silzZtmSn/6ARbUcs/apfoKzKyCMAY6BeViMmKCV1iKYCq7cVhZo8Xsw2 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769490" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769490" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555223" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555223" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:45 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 31/33] drm/i915/color: Enable plane color features Date: Tue, 29 Aug 2023 21:34:20 +0530 Message-ID: <20230829160422.1251087-32-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chaitanya Kumar Borah Initialize and expose all plane color features. Co-developed-by: Uma Shankar Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_color.c | 1 - drivers/gpu/drm/i915/display/skl_universal_plane.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 956080fb7fcd..4e5c82c88bd4 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -4361,7 +4361,6 @@ static int intel_prepare_plane_color_pipeline(struct drm_plane *plane) return ret; }; -__maybe_unused void intel_color_plane_init(struct drm_plane *plane) { struct drm_i915_private *i915 = to_i915(plane->dev); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index c85548d3210a..2e4ca55fdbb2 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2389,6 +2389,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR)); intel_plane_helper_add(plane); + intel_color_plane_init(&plane->base); return plane; From patchwork Tue Aug 29 16:04:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369148 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBBF8C83F12 for ; Tue, 29 Aug 2023 16:01:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EBBFB10E41D; Tue, 29 Aug 2023 16:00:13 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id A16F310E41A; Tue, 29 Aug 2023 16:00:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324800; x=1724860800; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T+wERlQG8R/pr72eTvqLBpH/8v2dX2AjwU8+RK3DLPI=; b=Nojbf046bEHThpGb5Cj+/Uk3r6TS30ozXbHliJ39wsDjwYfF/9R4y2Cb J2JNwT3hkbPtfGVmSJctSLgFCZrBKboOgRQflIpJjRNtkOcqTZRL9C5Vf Yn78nEz8yoZqNmUrS4jbp3QoMbGF2gdy6gwCjrvzqcLB4pF6BApPS/WkO z95mF5E9BA2VQ5AOAffzYgHVdx5XrtG1DSXwB8yvbc6zLprCH9lqxt2ec uwhbLV9FRx7a6AINaNu1e9EjnGaoePaaINse96FFZjV3V98flwSzI7KeE z4XXGzdT+P2HfAtVK3YeaXEA0pCuGXWlUgJrF3HqJT+b+NGZyFi6P3Hkk A==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769497" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769497" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555247" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555247" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:47 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 32/33] drm/i915/color: Add a dummy pipeline with 3D LUT Date: Tue, 29 Aug 2023 21:34:21 +0530 Message-ID: <20230829160422.1251087-33-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chaitanya Kumar Borah This patch is to demonstrate how a pipeline can be added. Co-developed-by: Uma Shankar Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/drm_atomic_state_helper.c | 3 ++ drivers/gpu/drm/drm_atomic_uapi.c | 15 +++++++++ drivers/gpu/drm/i915/display/intel_color.c | 37 ++++++++++++++++++++-- include/drm/drm_plane.h | 6 ++++ 4 files changed, 59 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index a554e04c2ce3..9c389d97b344 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -349,6 +349,8 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, drm_property_blob_get(state->color.post_csc_lut); if (state->color.private_color_op_data) drm_property_blob_get(state->color.private_color_op_data); + if (state->color.lut_3d) + drm_property_blob_get(state->color.lut_3d); state->color_mgmt_changed = false; } @@ -402,6 +404,7 @@ void __drm_atomic_helper_plane_destroy_state(struct drm_plane_state *state) drm_property_blob_put(state->color.ctm); drm_property_blob_put(state->color.post_csc_lut); drm_property_blob_put(state->color.private_color_op_data); + drm_property_blob_put(state->color.lut_3d); } EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state); diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 9e0fb36d1f47..5629db763fd1 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -482,6 +482,15 @@ int drm_plane_reset_color_op_blobs(struct drm_plane *plane, &blob_replaced); temp_replaced |= blob_replaced; + if (ret) + goto out; + + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->color.lut_3d, + 0, -1, -1, + &blob_replaced); + temp_replaced |= blob_replaced; + if (ret) goto out; out: @@ -551,6 +560,12 @@ int drm_plane_replace_color_op_blobs(struct drm_plane *plane, color_op[i].blob_id, -1, -1, &blob_replaced); + } else if (color_op[i].name == DRM_CB_3D_LUT) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->color.lut_3d, + color_op[i].blob_id, + -1, sizeof(struct drm_color_lut_ext), + &blob_replaced); } else { ret = -EINVAL; goto copy_fail; diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 4e5c82c88bd4..2352ddb4a96a 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -4265,6 +4265,19 @@ static const struct drm_color_lut_range xelpd_post_csc_hdr[] = { }, }; +static const struct drm_color_lut_range dummy_3d_lut_range[] = { + { + .flags = (DRM_MODE_LUT_POST_CSC | + DRM_MODE_LUT_REFLECT_NEGATIVE | + DRM_MODE_LUT_INTERPOLATE | + DRM_MODE_LUT_NON_DECREASING), + .count = 32, + .input_bpc = 24, .output_bpc = 16, + .start = 0, .end = (1 << 24) - 1, + .min = 0, .max = (1 << 24) - 1, + }, +}; + struct drm_color_op color_pipeline_sdr[] = { { .name = DRM_CB_PRE_CSC, @@ -4300,10 +4313,17 @@ struct drm_color_op color_pipeline_hdr[] = { }, }; +struct drm_color_op color_pipeline_3dlut[] = { + { + .name = DRM_CB_3D_LUT, + .type = CURVE_3D, + }, +}; + static int intel_prepare_plane_color_pipeline(struct drm_plane *plane) { struct drm_i915_private *i915 = to_i915(plane->dev); - struct drm_property_blob *blob[2] = {NULL}; + struct drm_property_blob *blob[3] = {NULL}; int ret = 0, i = 0; if (icl_is_hdr_plane(i915, to_intel_plane(plane)->id)) { @@ -4350,6 +4370,17 @@ static int intel_prepare_plane_color_pipeline(struct drm_plane *plane) color_pipeline_sdr[1].blob_id = blob[i++]->base.id; } + blob[i] = drm_property_create_blob(plane->dev, + sizeof(dummy_3d_lut_range), + dummy_3d_lut_range); + + if (IS_ERR(blob[i])) { + ret = PTR_ERR(blob[i]); + goto out; + } + + color_pipeline_3dlut[0].blob_id = blob[i++]->base.id; + out: if (ret) { for (int j = 0; j < i; j++) { @@ -4368,7 +4399,7 @@ void intel_color_plane_init(struct drm_plane *plane) if (DISPLAY_VER(i915) < 13) return; - drm_plane_create_get_color_pipeline_property(plane->dev, plane, 2); + drm_plane_create_get_color_pipeline_property(plane->dev, plane, 3); intel_prepare_plane_color_pipeline(plane); @@ -4387,6 +4418,8 @@ void intel_color_plane_init(struct drm_plane *plane) color_pipeline_sdr, sizeof(color_pipeline_sdr)); + drm_plane_add_color_pipeline(plane, "color pipeline 3dlut", color_pipeline_3dlut, + sizeof(color_pipeline_3dlut)); drm_plane_attach_get_color_pipeline_property(plane); drm_plane_create_set_color_pipeline_property(plane->dev, plane); diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 601b01e47a93..5cb84fa32dd5 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -284,6 +284,12 @@ struct drm_plane_state { * For example: Parameterized/non-parameterized fixed function operations */ struct drm_property_blob *private_color_op_data; + + /* @lut_3d: + * + * Three dimensional luts + */ + struct drm_property_blob *lut_3d; } color; /** From patchwork Tue Aug 29 16:04:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 13369151 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A291BC6FA8F for ; Tue, 29 Aug 2023 16:01:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A2F6510E436; Tue, 29 Aug 2023 16:00:15 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id AFB5E10E427; Tue, 29 Aug 2023 16:00:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693324800; x=1724860800; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=N0iIMb8qITZAdx5HadKHRx6hwV/mNvZm9aWyX0epqTk=; b=POWz73e+TBCxomaVGDSzpFYYURlXGlA8OpihimwnnLagS0aOyJUVIrIZ KxU8umG+fS6PrEBynm6mvUW9XLiGw6FclV1bW8xlsUlRzvFbu70e2K7lR FW0u4mOEVnm24xQJvSyI7LyrWyDj+Q9CDT2+otg5unclKeFva8PTmRhli c1O1BPyA7F+h/MQ9WKUM3MntFG/9JmY6EXLm9sZyF+157WsIXT3+rER3D YrIntfZNoASYrI5fsjdmA1in8kAo/ci4sdpKC0n8hmsortAL5TIjlrM8x JhacSFjAoaiIlDsidO3nIqCP0okJzfOz4hLbW/+uqPJGyX7LkZQguYoYn g==; X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="441769512" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="441769512" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2023 08:59:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10817"; a="688555278" X-IronPort-AV: E=Sophos;i="6.02,210,1688454000"; d="scan'208";a="688555278" Received: from cfl-desktop.iind.intel.com ([10.190.239.20]) by orsmga003.jf.intel.com with ESMTP; 29 Aug 2023 08:59:49 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [RFC 33/33] drm/i915/color: Add example implementation for vendor specific color operation Date: Tue, 29 Aug 2023 21:34:22 +0530 Message-ID: <20230829160422.1251087-34-uma.shankar@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230829160422.1251087-1-uma.shankar@intel.com> References: <20230829160422.1251087-1-uma.shankar@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Uma Shankar , Chaitanya Kumar Borah , wayland-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Chaitanya Kumar Borah This is an example of how vendor specific color operation could be supported by the uapi Co-developed-by: Uma Shankar Signed-off-by: Uma Shankar Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_color.c | 42 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_color.h | 1 + .../drm/i915/display/skl_universal_plane.c | 1 + include/uapi/drm/i915_drm.h | 25 +++++++++++ 4 files changed, 64 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 2352ddb4a96a..5acc89b0cbf7 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -21,6 +21,7 @@ * DEALINGS IN THE SOFTWARE. * */ +#include #include "i915_reg.h" #include "intel_color.h" @@ -87,6 +88,7 @@ struct intel_color_funcs { */ void (*load_plane_csc_matrix)(const struct drm_plane_state *plane_state); void (*load_plane_luts)(const struct drm_plane_state *plane_state); + void (*load_private)(const struct drm_plane_state *plane_state); }; #define CTM_COEFF_SIGN (1ULL << 63) @@ -2145,6 +2147,25 @@ static void xelpd_load_plane_csc_matrix(const struct drm_plane_state *state) intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2), postoff); } +static void xelpd_load_private(const struct drm_plane_state *state) +{ + struct drm_i915_private *i915 = to_i915(state->plane->dev); + struct i915_color_op_data *op_data; + enum plane_id plane = to_intel_plane(state->plane)->id; + int i, num; + + if (icl_is_hdr_plane(i915, plane) || !state->color.private_color_op_data) + return; + + op_data = state->color.private_color_op_data->data; + num = state->color.private_color_op_data->length / sizeof(struct i915_color_op_data); + + for (i = 0; i < num; i++) { + if (op_data[i].flag == I915_COLOR_OP_FIXED_FUNC_CSC) + DRM_DEBUG_KMS("CSC OP [%d]", op_data[i].csc_type); + } +} + void intel_color_load_luts(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); @@ -2168,6 +2189,14 @@ void intel_color_load_plane_csc_matrix(const struct drm_plane_state *plane_state i915->display.funcs.color->load_plane_csc_matrix(plane_state); } +void intel_color_load_private(const struct drm_plane_state *plane_state) +{ + struct drm_i915_private *i915 = to_i915(plane_state->plane->dev); + + if (i915->display.funcs.color->load_private) + i915->display.funcs.color->load_private(plane_state); +} + void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); @@ -4011,6 +4040,7 @@ static const struct intel_color_funcs xelpd_color_funcs = { .read_csc = icl_read_csc, .load_plane_luts = xelpd_plane_load_luts, .load_plane_csc_matrix = xelpd_load_plane_csc_matrix, + .load_private = xelpd_load_private, }; static const struct intel_color_funcs tgl_color_funcs = { @@ -4284,10 +4314,12 @@ struct drm_color_op color_pipeline_sdr[] = { .type = CURVE_1D, .blob_id = 0, /* To be updated during plane initialization */ }, - /* - * SDR planes have fixed function CSC capabilities. - * TODO: Add support for it - */ + { + .name = DRM_CB_PRIVATE, + .type = FIXED_FUNCTION, + .blob_id = 0, + .private_flags = I915_COLOR_OP_FIXED_FUNC_CSC, + }, { .name = DRM_CB_POST_CSC, .type = CURVE_1D, @@ -4367,7 +4399,7 @@ static int intel_prepare_plane_color_pipeline(struct drm_plane *plane) * LUT ranges for SDR planes are similar for pre and post-csc blocks */ color_pipeline_sdr[0].blob_id = - color_pipeline_sdr[1].blob_id = blob[i++]->base.id; + color_pipeline_sdr[2].blob_id = blob[i++]->base.id; } blob[i] = drm_property_create_blob(plane->dev, diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h index a513c88d3bfc..aa8841f1d1ef 100644 --- a/drivers/gpu/drm/i915/display/intel_color.h +++ b/drivers/gpu/drm/i915/display/intel_color.h @@ -34,4 +34,5 @@ void intel_color_assert_luts(const struct intel_crtc_state *crtc_state); void intel_color_plane_init(struct drm_plane *plane); void intel_color_load_plane_luts(const struct drm_plane_state *plane_state); void intel_color_load_plane_csc_matrix(const struct drm_plane_state *plane_state); +void intel_color_load_private(const struct drm_plane_state *plane_state); #endif /* __INTEL_COLOR_H__ */ diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 2e4ca55fdbb2..e7228da3358d 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1283,6 +1283,7 @@ icl_plane_update_noarm(struct intel_plane *plane, if (plane_state->uapi.color_mgmt_changed) { intel_color_load_plane_luts(&plane_state->uapi); intel_color_load_plane_csc_matrix(&plane_state->uapi); + intel_color_load_private(&plane_state->uapi); } intel_psr2_program_plane_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane); diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 7000e5910a1d..e7f87ad0645c 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -3841,6 +3841,31 @@ struct drm_i915_gem_create_ext_set_pat { /* ID of the protected content session managed by i915 when PXP is active */ #define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf +/* I915 specific color operation */ +#define I915_COLOR_OP_FIXED_FUNC_CSC (1 << 0) + +/** + * enum i915_csc_operation + * + * Color conversion operations which can be performed by a fixed function h/w + * of type I915_COLOR_OP_FIXED_FUNC_CSC + */ +enum i915_csc_operation { + I915_CSC_YUV601_TO_RGB601, + I915_CSC_YUV709_TO_RGB709, + I915_CSC_YUV2020_TO_RGB2020, + I915_CSC_RGB709_TO_RGB2020, + I915_CSC_MAX, +}; + +struct i915_color_op_data { + __u32 flag; /* to identify i915 specific color operation */ + union { + enum i915_csc_operation csc_type; + /* Add more structures here */ + }; +}; + #if defined(__cplusplus) } #endif