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Thu, 31 Aug 2023 16:14:49 +0000 From: hzy To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, quic_gokulsri@quicinc.com, quic_srichara@quicinc.com, quic_varada@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ziyang Huang Subject: [PATCH 1/1] arm64: dts: ipq5018: Correct uart1_pins pinconf Date: Thu, 31 Aug 2023 16:03:13 +0000 Message-ID: X-Mailer: git-send-email 2.40.1 X-TMN: [4BJq9U5NbH+gEKmEGmagbt4XGsADHS1/aDIulclQuM2Dz3DNhew2AQ==] X-ClientProxiedBy: PH8PR05CA0015.namprd05.prod.outlook.com (2603:10b6:510:2cc::16) To TYZPR01MB5556.apcprd01.prod.exchangelabs.com (2603:1096:400:363::9) X-Microsoft-Original-Message-ID: <20230831160313.1136641-1-hzyitc@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYZPR01MB5556:EE_|SI2PR01MB3979:EE_ X-MS-Office365-Filtering-Correlation-Id: 2dcfbf15-0916-431f-45a7-08dbaa3d6663 X-MS-Exchange-SLBlob-MailProps: dx7TrgQSB6fbW94R0lh08zY2i4OJd2lItBoAsJfVLJHJ6zabYk3VieAxWjt/MRvlclvRJt3qABpXSj1ysoGe5NsPmJRz9+FIexXBfMZaUImYEIYTZgHMBGJbwyCyCfmukLHxwPqZrTnoqlThnDDcLC9XDAAqfklkv7Q/gVK4rIdK2Cozd5ufvGFq5V+k0qEZqqbtoTTejUwj/Z1TX5ev457Z5QbM916fQg1QbwbX4ryCAeoIUdCfo5ZGSHd9Xn85Z6Vr1qJ340yQPz5S1Vmvnej5VA5T9L89XvyHgOVZRI34Is+Ag2g6IYy6q8C1Xxep2ba6b3CE4fIqV/8oZrUfM/gAByxp5nYhgVU9GYqqqiFc4LRa3YE9fm8h3cWyjh7WsWDwX5wUlndGHxtofuOoxN7rIZRlRnqPXtkHGxtrZBTdCP+Om+QHzOXhEE0YB3aBzFCL9gidbzK87LlNpTsj3UvPLl/ZPDpRKqXOaEwtwJnPvMMN24tIJxwdsULOImf+nuP1z7hXfWN64yFd7+wQ9aLWf2XYWcwa6h3SynvkwdtreoLFUxsYs/bRPgIF0la0DUhQH4dYeFmSdSHNXVe2nfDfLaMPWFJQR3wJh0XucL55YVQF2iVhiuDbujJC6vbT89SFbJHpANqvtcui4oP3QK7h7Uo57c7kB0oZO3FOyb3/AJTTQAD646aDOR+j7gqLX2eCEY6jIrM/rbEWXF9M6yK4/oQB4RaN2ivXHEKfM9XpntVh73kgkccTMPfth6ko1wK0QuuXMlU= X-Microsoft-Antispam: BCL:0; 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X is the UART ID. Starts from 1. 1-6 are in BLSP Block 1. 7-12 are in BLSP Block 2. Y is the index of mux config. Starts from 0. In dts, the serials are also named "blspX_uartY", but with different logic. X is the BLSP Block ID. Starts from 1. Y is the uart id inside block. In "ipq6018.dtsi" and "ipq8074.dtsi", it starts from 1. But in "ipq5332.dtsi" and "ipq9574.dtsi", it starts from 0. +-----------------+-----------------+-------------+-----------------+ | Block ID | ID inside Block | dts name | pinconfig name | | (Starts from 1) | (Starts from 1) | | | +-----------------+-----------------+-------------+-----------------+ | 1 | 1 | blsp1_uart1 | blsp0_uartY | | 1 | 2 | blsp1_uart2 | blsp1_uartY | | 1 | 6 | blsp1_uart6 | blsp5_uartY | | 2 | 1 | blsp2_uart1 | blsp6_uartY | | 2 | 6 | blsp2_uart6 | blsp12_uartY | +-----------------+-----------------+-------------+-----------------+ In "ipq5018.dts", "blsp1_uart1" (dts name) is the first serial (confimed by the address), So its pinconfig should be "blsp0_uart0" (pinconfig name, use GPIO 20 and 21) or "blsp0_uart1" (pinconfig name, use GPIO 28 and 29). Fixes: 570006756a16 ("arm64: dts: Add ipq5018 SoC and rdp432-c2 board support") Signed-off-by: Ziyang Huang --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 9f13d2dcdfd5..91b98020e1c6 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -104,10 +104,10 @@ tlmm: pinctrl@1000000 { #interrupt-cells = <2>; uart1_pins: uart1-state { - pins = "gpio31", "gpio32", "gpio33", "gpio34"; - function = "blsp1_uart1"; + pins = "gpio28", "gpio29"; + function = "blsp0_uart1"; drive-strength = <8>; - bias-pull-down; + bias-disabled; }; };