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Thu, 31 Aug 2023 19:39:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044F3.mail.protection.outlook.com (10.167.241.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6745.17 via Frontend Transport; Thu, 31 Aug 2023 19:39:00 +0000 Received: from hamza-pc.localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 31 Aug 2023 14:38:58 -0500 From: Hamza Mahfooz To: Subject: [PATCH v2 1/2] Revert "drm/amd/display: Remove v_startup workaround for dcn3+" Date: Thu, 31 Aug 2023 15:38:41 -0400 Message-ID: <20230831193844.154254-1-hamza.mahfooz@amd.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F3:EE_|PH7PR12MB9068:EE_ X-MS-Office365-Filtering-Correlation-Id: d913baeb-609d-4a44-ebb0-08dbaa59ed1a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230031)(4636009)(136003)(39860400002)(346002)(376002)(396003)(451199024)(1800799009)(82310400011)(186009)(36840700001)(46966006)(40470700004)(6666004)(2906002)(5660300002)(86362001)(316002)(6916009)(478600001)(44832011)(2616005)(47076005)(4326008)(36860700001)(8676002)(8936002)(966005)(40460700003)(1076003)(26005)(82740400003)(40480700001)(41300700001)(336012)(426003)(36756003)(356005)(81166007)(70206006)(70586007)(83380400001)(54906003)(16526019)(16060500005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2023 19:39:00.8426 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d913baeb-609d-4a44-ebb0-08dbaa59ed1a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9068 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Miess , Gabe Teeger , Leo Li , dri-devel@lists.freedesktop.org, "Pan, Xinhui" , Rodrigo Siqueira , linux-kernel@vger.kernel.org, stable@vger.kernel.org, Nicholas Kazlauskas , Wenjing Liu , Fangzhi Zuo , Aurabindo Pillai , Hamza Mahfooz , Alex Deucher , Sung Joon Kim , Jun Lei , =?utf-8?q?Christian_K=C3=B6nig?= , Alvin Lee Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This reverts commit 3a31e8b89b7240d9a17ace8a1ed050bdcb560f9e. We still need to call dcn20_adjust_freesync_v_startup() for older DCN3+ ASICs otherwise it can cause DP to HDMI 2.1 PCONs to fail to light up. Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2809 Signed-off-by: Hamza Mahfooz Reviewed-By: Fangzhi Zuo Reviewed-by: Harry Wentland --- .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 24 ++++--------------- 1 file changed, 4 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index 0989a0152ae8..1bfdf0271fdf 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -1099,6 +1099,10 @@ void dcn20_calculate_dlg_params(struct dc *dc, context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; + if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid) + dcn20_adjust_freesync_v_startup( + &context->res_ctx.pipe_ctx[i].stream->timing, + &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); pipe_idx++; } @@ -1927,7 +1931,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co int vlevel = 0; int pipe_split_from[MAX_PIPES]; int pipe_cnt = 0; - int i = 0; display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); DC_LOGGER_INIT(dc->ctx->logger); @@ -1951,15 +1954,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate); dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); - for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (!context->res_ctx.pipe_ctx[i].stream) - continue; - if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid) - dcn20_adjust_freesync_v_startup( - &context->res_ctx.pipe_ctx[i].stream->timing, - &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); - } - BW_VAL_TRACE_END_WATERMARKS(); goto validate_out; @@ -2232,7 +2226,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc, int vlevel = 0; int pipe_split_from[MAX_PIPES]; int pipe_cnt = 0; - int i = 0; display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); DC_LOGGER_INIT(dc->ctx->logger); @@ -2261,15 +2254,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc, dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate); dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); - for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (!context->res_ctx.pipe_ctx[i].stream) - continue; - if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid) - dcn20_adjust_freesync_v_startup( - &context->res_ctx.pipe_ctx[i].stream->timing, - &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); - } - BW_VAL_TRACE_END_WATERMARKS(); goto validate_out; From patchwork Thu Aug 31 19:38:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hamza Mahfooz X-Patchwork-Id: 13371827 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75B05C83F3E for ; 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Thu, 31 Aug 2023 14:39:01 -0500 From: Hamza Mahfooz To: Subject: [PATCH v2 2/2] drm/amd/display: limit the v_startup workaround for ASICs older than DCN3.1 Date: Thu, 31 Aug 2023 15:38:42 -0400 Message-ID: <20230831193844.154254-2-hamza.mahfooz@amd.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831193844.154254-1-hamza.mahfooz@amd.com> References: <20230831193844.154254-1-hamza.mahfooz@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F3:EE_|PH7PR12MB5710:EE_ X-MS-Office365-Filtering-Correlation-Id: f48e3f57-d8d5-495f-e7a5-08dbaa59ef1d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PViyb30tqUBzp6AbuFkZ3mKZTbrznUUwtBjtGbkmKqMwSoVpL/jEkMAio9oET6I5knyBvU1tq93UpSdSFHTkA79pz8WX0P7hI+zmVlVxgKvwkysFdUCs4O083wYhw3EqH/tRut/5jhRBfyt5Go7R41IotFzyg/Zbh+zBljsCm9v3oRrvSl0ujW7oHfB+TvoL1AZTIqc9dr61VXEtmEfU+ly1uCID7I20qe9vpRzQAdgM+x+2HFDB5QVEKWcQcVGt0pj2ywXDTg5Wz2Mgu08mHVEJp/95hR1RWihATk8U/769DQMMH+CuX3hWqsb/7E7ydpGTreR8JMu2FBchGaE3Q2gzwgKTVej8kPRMKaoeQ3NEWUr/8iB+bau7bqAFaGRpBUgnpWreC4MrT3SXuHcRmDMrqCT+SokFpg4R0RXWwdsVCd1DA/ukK1te0qDISYAcAX7hGAPSjuAvDEhyuguZU4UxP73jMl3z5s6jumCvA+TQ3u2kngayj/vbADgFIhAklKZL4DoMyoGaDXX17n92u3wJ0i0D5leB1pRuy1eb/JX8va5h2kgEwjUEkBkmJlQMCY9wcYIftGkq7NgAgCgo08+rT56I8uoqBchdbe1glysRMaXwFRKkqFrTLIgwRDaPFNeD6Dmr8YrBODZV4NALbXLubs0shuI4bxSzq92PM9smf5t2fHSat9Yo1VegVZn7YaU5JPMlrECpVodu7NEIoeK6qV6uYyqcnpqN3S+lC2NGJraogQtluHU19NAbXJiOKSNSfHpm7x1MiIRT1oO3ZVNIpnxO3JaLsB71qvF2lSugAkEVAX/mWSL8CXSvJYUy X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(396003)(346002)(39860400002)(136003)(376002)(1800799009)(186009)(451199024)(82310400011)(46966006)(36840700001)(40470700004)(82740400003)(356005)(6666004)(36756003)(40460700003)(86362001)(81166007)(36860700001)(40480700001)(47076005)(2616005)(1076003)(2906002)(426003)(336012)(26005)(16526019)(83380400001)(478600001)(70206006)(70586007)(8936002)(54906003)(8676002)(4326008)(5660300002)(44832011)(41300700001)(6916009)(316002)(16060500005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Aug 2023 19:39:04.2176 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f48e3f57-d8d5-495f-e7a5-08dbaa59ef1d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5710 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Miess , Gabe Teeger , Leo Li , dri-devel@lists.freedesktop.org, "Pan, Xinhui" , Rodrigo Siqueira , linux-kernel@vger.kernel.org, stable@vger.kernel.org, Nicholas Kazlauskas , Wenjing Liu , Fangzhi Zuo , Aurabindo Pillai , Hamza Mahfooz , Alex Deucher , Sung Joon Kim , Jun Lei , =?utf-8?q?Christian_K=C3=B6nig?= , Alvin Lee Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since, calling dcn20_adjust_freesync_v_startup() on DCN3.1+ ASICs can cause the display to flicker and underflow to occur we shouldn't call it for them. So, ensure that the DCN version is less than DCN_VERSION_3_1 before calling dcn20_adjust_freesync_v_startup(). Cc: stable@vger.kernel.org Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index 1bfdf0271fdf..a68fb45ed487 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -1099,7 +1099,8 @@ void dcn20_calculate_dlg_params(struct dc *dc, context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; - if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid) + if (dc->ctx->dce_version < DCN_VERSION_3_1 && + context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid) dcn20_adjust_freesync_v_startup( &context->res_ctx.pipe_ctx[i].stream->timing, &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);