From patchwork Fri Sep 1 11:42:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 13372444 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EE3ECA0FE9 for ; Fri, 1 Sep 2023 11:43:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349228AbjIALnM (ORCPT ); Fri, 1 Sep 2023 07:43:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349212AbjIALnH (ORCPT ); Fri, 1 Sep 2023 07:43:07 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B07410D5; Fri, 1 Sep 2023 04:43:03 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 381A0Cit009800; Fri, 1 Sep 2023 11:42:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=IPdEplR1fA97t+2tm9I9JuniHz5TEiMiIVvWm/BaUPE=; b=cn1fmYC0+lNylkMm0e7DU8aWWIue4JK6rqzQuM+hKlyNvsDFnRtQjOp9g+7x0TE/8SZu 43Qx1+u3JgCrT8zG1763DjBBvrgFXfxuNJxz27oQalrT1NHB/efk+WBTIJotOQklaE6k shPUi3Kj5GY/S1d8BNNMaiyap4Qusi40Mw++OFJiMnqZQWvBJHMryyElNVC9w3gC6K5e ciloFCivNaUAgNfHEahblR6XznkXdBl6XmmHJLhTqSyVKerSAkcmTSK7cDEcdUbus2TG +SaUwxYPRKibBLDfRykd4Aa5Y59eSWfEqi0RzU4ovzqVXzIzNZQsE/JFSoaLNJK5D3L4 Cg== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3stub8b3a8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 01 Sep 2023 11:42:52 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 381Bgm9H013931; Fri, 1 Sep 2023 11:42:48 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3sqafmj03v-1; Fri, 01 Sep 2023 11:42:48 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 381Bgmws013924; Fri, 1 Sep 2023 11:42:48 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 381BgmcW013923; Fri, 01 Sep 2023 11:42:48 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id DBD335006A8; Fri, 1 Sep 2023 17:12:47 +0530 (+0530) From: Nitin Rawat To: mani@kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, jejb@linux.ibm.com, martin.petersen@oracle.com Cc: quic_cang@quicinc.com, quic_nguyenb@quicinc.com, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Nitin Rawat , Naveen Kumar Goud Arepalli Subject: [PATCH V6 1/6] scsi: ufs: qcom: Align mask for core_clk_1us_cycles Date: Fri, 1 Sep 2023 17:12:37 +0530 Message-Id: <20230901114242.31219-2-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230901114242.31219-1-quic_nitirawa@quicinc.com> References: <20230901114242.31219-1-quic_nitirawa@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: P5PS0SifPxXz9hF08BDiHQI1X225CNGx X-Proofpoint-ORIG-GUID: P5PS0SifPxXz9hF08BDiHQI1X225CNGx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-01_09,2023-08-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=979 phishscore=0 priorityscore=1501 adultscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 bulkscore=0 impostorscore=0 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309010109 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Align core_clk_1us_cycles mask for Qualcomm UFS Controller V4.0.0 onwards as per Hardware Specification. Co-developed-by: Naveen Kumar Goud Arepalli Signed-off-by: Naveen Kumar Goud Arepalli Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 28 ++++++++++++++++++---------- drivers/ufs/host/ufs-qcom.h | 5 +++-- 2 files changed, 21 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index f88febb23123..fe36003faaa8 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1297,22 +1297,30 @@ static void ufs_qcom_exit(struct ufs_hba *hba) } static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, - u32 clk_cycles) + u32 cycles_in_1us) { - int err; + struct ufs_qcom_host *host = ufshcd_get_variant(hba); u32 core_clk_ctrl_reg; + int ret; - if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK) - return -EINVAL; - - err = ufshcd_dme_get(hba, + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), &core_clk_ctrl_reg); - if (err) - return err; + if (ret) + return ret; - core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK; - core_clk_ctrl_reg |= clk_cycles; + /* Bit mask is different for UFS host controller V4.0.0 onwards */ + if (host->hw_ver.major >= 4) { + if (!FIELD_FIT(CLK_1US_CYCLES_MASK_V4, cycles_in_1us)) + return -ERANGE; + core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK_V4; + core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK_V4, cycles_in_1us); + } else { + if (!FIELD_FIT(CLK_1US_CYCLES_MASK, cycles_in_1us)) + return -ERANGE; + core_clk_ctrl_reg &= ~CLK_1US_CYCLES_MASK; + core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us); + } /* Clear CORE_CLK_DIV_EN */ core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index d6f8e74bd538..8a9d3dbec297 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -129,8 +129,9 @@ enum { #define PA_VS_CONFIG_REG1 0x9000 #define DME_VS_CORE_CLK_CTRL 0xD002 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */ -#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) -#define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK 0xFF +#define CLK_1US_CYCLES_MASK_V4 GENMASK(27, 16) +#define CLK_1US_CYCLES_MASK GENMASK(7, 0) +#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) static inline void ufs_qcom_get_controller_revision(struct ufs_hba *hba, From patchwork Fri Sep 1 11:42:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 13372443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3756CA0FE8 for ; Fri, 1 Sep 2023 11:43:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349225AbjIALnL (ORCPT ); Fri, 1 Sep 2023 07:43:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231205AbjIALnE (ORCPT ); Fri, 1 Sep 2023 07:43:04 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5375B5; Fri, 1 Sep 2023 04:43:01 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 381A0Csi019941; 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Fri, 1 Sep 2023 11:42:49 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3sqafmj043-1; Fri, 01 Sep 2023 11:42:49 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 381BgnNi013941; Fri, 1 Sep 2023 11:42:49 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 381BgnHO013940; Fri, 01 Sep 2023 11:42:49 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id E44985006A6; Fri, 1 Sep 2023 17:12:48 +0530 (+0530) From: Nitin Rawat To: mani@kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, jejb@linux.ibm.com, martin.petersen@oracle.com Cc: quic_cang@quicinc.com, quic_nguyenb@quicinc.com, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Nitin Rawat , Naveen Kumar Goud Arepalli Subject: [PATCH V6 2/6] scsi: ufs: qcom: Configure PA_VS_CORE_CLK_40NS_CYCLES Date: Fri, 1 Sep 2023 17:12:38 +0530 Message-Id: <20230901114242.31219-3-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230901114242.31219-1-quic_nitirawa@quicinc.com> References: <20230901114242.31219-1-quic_nitirawa@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 8sHP9734E5S5QmK6GgQWATXr9xMC_F9x X-Proofpoint-ORIG-GUID: 8sHP9734E5S5QmK6GgQWATXr9xMC_F9x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-01_09,2023-08-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 mlxlogscore=999 spamscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 bulkscore=0 impostorscore=0 mlxscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309010109 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Configure PA_VS_CORE_CLK_40NS_CYCLES with frequency of unipro core clk for Qualcomm UFS controller V4.0 and onwards to align with the hardware specification. Co-developed-by: Naveen Kumar Goud Arepalli Signed-off-by: Naveen Kumar Goud Arepalli Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 47 ++++++++++++++++++++++++++++--------- drivers/ufs/host/ufs-qcom.h | 2 ++ 2 files changed, 38 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index fe36003faaa8..018e391c276e 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -93,8 +93,9 @@ static const struct __ufs_qcom_bw_table { static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS]; static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); -static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, - u32 clk_cycles); +static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, + u32 clk_cycles, + u32 clk_40ns_cycles); static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) { @@ -690,8 +691,8 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, * set unipro core clock cycles to 150 & clear clock * divider */ - err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, - 150); + err = ufs_qcom_set_core_clk_ctrl(hba, + 150, 6); /* * Some UFS devices (and may be host) have issues if LCC is @@ -1295,12 +1296,12 @@ static void ufs_qcom_exit(struct ufs_hba *hba) phy_power_off(host->generic_phy); phy_exit(host->generic_phy); } - -static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, - u32 cycles_in_1us) +static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, + u32 cycles_in_1us, + u32 cycles_in_40ns) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - u32 core_clk_ctrl_reg; + u32 core_clk_ctrl_reg, reg; int ret; ret = ufshcd_dme_get(hba, @@ -1325,9 +1326,33 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, /* Clear CORE_CLK_DIV_EN */ core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; - return ufshcd_dme_set(hba, + err = ufshcd_dme_set(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), core_clk_ctrl_reg); + /* + * UFS host controller V4.0.0 onwards needs to program + * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed + * frequency of unipro core clk of UFS host controller. + */ + if (!err && (host->hw_ver.major >= 4)) { + if (cycles_in_40ns > PA_VS_CORE_CLK_40NS_CYCLES_MASK) + return -EINVAL; + + err = ufshcd_dme_get(hba, + UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), + ®); + if (err) + return err; + + reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK; + reg |= cycles_in_40ns; + + err = ufshcd_dme_set(hba, + UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), + reg); + } + + return err; } static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) @@ -1344,7 +1369,7 @@ static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) return 0; /* set unipro core clock cycles to 150 and clear clock divider */ - return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150); + return ufs_qcom_set_core_clk_ctrl(hba, 150, 6); } static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) @@ -1380,7 +1405,7 @@ static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) return 0; /* set unipro core clock cycles to 75 and clear clock divider */ - return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75); + return ufs_qcom_set_core_clk_ctrl(hba, 75, 3); } static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index 8a9d3dbec297..d81bf1a1b77a 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -132,6 +132,8 @@ enum { #define CLK_1US_CYCLES_MASK_V4 GENMASK(27, 16) #define CLK_1US_CYCLES_MASK GENMASK(7, 0) #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) +#define PA_VS_CORE_CLK_40NS_CYCLES 0x9007 +#define PA_VS_CORE_CLK_40NS_CYCLES_MASK GENMASK(6, 0) static inline void ufs_qcom_get_controller_revision(struct ufs_hba *hba, From patchwork Fri Sep 1 11:42:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 13372446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5AE3BCA0FEC for ; Fri, 1 Sep 2023 11:43:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349219AbjIALnM (ORCPT ); Fri, 1 Sep 2023 07:43:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349209AbjIALnG (ORCPT ); Fri, 1 Sep 2023 07:43:06 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DC84E70; Fri, 1 Sep 2023 04:43:03 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3819rjKg005433; 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Fri, 1 Sep 2023 11:42:50 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3sqafmj049-1; Fri, 01 Sep 2023 11:42:50 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 381BgnNk013941; Fri, 1 Sep 2023 11:42:50 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 381BgoLM013954; Fri, 01 Sep 2023 11:42:50 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id D99B15006A6; Fri, 1 Sep 2023 17:12:49 +0530 (+0530) From: Nitin Rawat To: mani@kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, jejb@linux.ibm.com, martin.petersen@oracle.com Cc: quic_cang@quicinc.com, quic_nguyenb@quicinc.com, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Nitin Rawat , Naveen Kumar Goud Arepalli Subject: [PATCH V6 3/6] scsi: ufs: qcom: Add multiple frequency support for unipro clk attributes Date: Fri, 1 Sep 2023 17:12:39 +0530 Message-Id: <20230901114242.31219-4-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230901114242.31219-1-quic_nitirawa@quicinc.com> References: <20230901114242.31219-1-quic_nitirawa@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: hrcgzhUkZRnnvGcFQfeWgo_Z0-q2IHEr X-Proofpoint-ORIG-GUID: hrcgzhUkZRnnvGcFQfeWgo_Z0-q2IHEr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-01_09,2023-08-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 clxscore=1015 mlxscore=0 impostorscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309010109 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add Support to configure CORE_CLK_1US_CYCLES, PA_VS_CORE_CLK_40NS_CYCLES for multiple unipro clock frequencies. Currently this is handled only for only 150Mhz and 75MHz. Since different qualcomm targets support different unipro frequency, add support to handle all other frequencies like 403MHz, 300MHz, 202MHz, 150 MHz, 75Mhz, 37.5 MHz. Co-developed-by: Naveen Kumar Goud Arepalli Signed-off-by: Naveen Kumar Goud Arepalli Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 96 ++++++++++++++++++++++++++++--------- drivers/ufs/host/ufs-qcom.h | 10 ++++ 2 files changed, 84 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 018e391c276e..e3648e936498 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -94,8 +94,7 @@ static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS]; static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, - u32 clk_cycles, - u32 clk_40ns_cycles); + bool is_max_freq); static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) { @@ -686,13 +685,14 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, return -EINVAL; } - if (ufs_qcom_cap_qunipro(host)) - /* - * set unipro core clock cycles to 150 & clear clock - * divider - */ - err = ufs_qcom_set_core_clk_ctrl(hba, - 150, 6); + if (ufs_qcom_cap_qunipro(host)) { + err = ufs_qcom_set_core_clk_ctrl(hba, true); + if (err) { + dev_err(hba->dev, + "%s cfg core clk ctrl failed\n", + __func__); + } + } /* * Some UFS devices (and may be host) have issues if LCC is @@ -1297,13 +1297,67 @@ static void ufs_qcom_exit(struct ufs_hba *hba) phy_exit(host->generic_phy); } static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, - u32 cycles_in_1us, - u32 cycles_in_40ns) + bool is_max_freq) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct list_head *head = &hba->clk_list_head; u32 core_clk_ctrl_reg, reg; + struct ufs_clk_info *clki; + u32 cycles_in_1us, cycles_in_40ns; int ret; + list_for_each_entry(clki, head, list) { + if (!IS_ERR_OR_NULL(clki->clk) && + !strcmp(clki->name, "core_clk_unipro")) { + if (is_max_freq) + cycles_in_1us = clki->max_freq; + else + cycles_in_1us = clk_get_rate(clki->clk); + break; + } + } + + if ((cycles_in_1us % (1000 * 1000)) != 0) + cycles_in_1us = cycles_in_1us/(1000 * 1000) + 1; + else + cycles_in_1us = cycles_in_1us/(1000 * 1000); + + /* + * Generic formulae for cycles_in_40ns = (freq_unipro/25) is not + * applicable for all frequencies. For ex: ceil(37.5 MHz/25) will + * be 2 and ceil(403 MHZ/25) will be 17 whereas Hardware + * specification expect to be 16. Hence use exact hardware spec + * mandated value for cycles_in_40ns instead of calculating using + * generic formulae. + */ + switch (cycles_in_1us) { + case UNIPRO_CORE_CLK_FREQ_403_MHZ: + cycles_in_40ns = 16; + break; + case UNIPRO_CORE_CLK_FREQ_300_MHZ: + cycles_in_40ns = 12; + break; + case UNIPRO_CORE_CLK_FREQ_201_5_MHZ: + cycles_in_40ns = 8; + break; + case UNIPRO_CORE_CLK_FREQ_150_MHZ: + cycles_in_40ns = 6; + break; + case UNIPRO_CORE_CLK_FREQ_100_MHZ: + cycles_in_40ns = 4; + break; + case UNIPRO_CORE_CLK_FREQ_75_MHZ: + cycles_in_40ns = 3; + break; + case UNIPRO_CORE_CLK_FREQ_37_5_MHZ: + cycles_in_40ns = 2; + break; + default: + ret = -EINVAL; + dev_err(hba->dev, "UNIPRO clk freq %u MHz not supported\n", + cycles_in_1us); + } + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), &core_clk_ctrl_reg); @@ -1326,7 +1380,7 @@ static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, /* Clear CORE_CLK_DIV_EN */ core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; - err = ufshcd_dme_set(hba, + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), core_clk_ctrl_reg); /* @@ -1334,25 +1388,25 @@ static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed * frequency of unipro core clk of UFS host controller. */ - if (!err && (host->hw_ver.major >= 4)) { + if (!ret && (host->hw_ver.major >= 4)) { if (cycles_in_40ns > PA_VS_CORE_CLK_40NS_CYCLES_MASK) return -EINVAL; - err = ufshcd_dme_get(hba, + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), ®); - if (err) - return err; + if (ret) + return ret; reg &= ~PA_VS_CORE_CLK_40NS_CYCLES_MASK; reg |= cycles_in_40ns; - err = ufshcd_dme_set(hba, + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); } - return err; + return ret; } static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) @@ -1368,8 +1422,7 @@ static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) if (!ufs_qcom_cap_qunipro(host)) return 0; - /* set unipro core clock cycles to 150 and clear clock divider */ - return ufs_qcom_set_core_clk_ctrl(hba, 150, 6); + return ufs_qcom_set_core_clk_ctrl(hba, true); } static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) @@ -1404,8 +1457,7 @@ static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) if (!ufs_qcom_cap_qunipro(host)) return 0; - /* set unipro core clock cycles to 75 and clear clock divider */ - return ufs_qcom_set_core_clk_ctrl(hba, 75, 3); + return ufs_qcom_set_core_clk_ctrl(hba, false); } static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index d81bf1a1b77a..bc176ef58e3e 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -9,6 +9,7 @@ #include #include #include +#include #define MAX_UFS_QCOM_HOSTS 1 #define MAX_U32 (~(u32)0) @@ -79,6 +80,15 @@ enum { UFS_MEM_CQIS_VS = 0x8, }; +/* QCOM UFS host controller core clk frequencies */ +#define UNIPRO_CORE_CLK_FREQ_37_5_MHZ 38 +#define UNIPRO_CORE_CLK_FREQ_75_MHZ 75 +#define UNIPRO_CORE_CLK_FREQ_100_MHZ 100 +#define UNIPRO_CORE_CLK_FREQ_150_MHZ 150 +#define UNIPRO_CORE_CLK_FREQ_300_MHZ 300 +#define UNIPRO_CORE_CLK_FREQ_201_5_MHZ 202 +#define UNIPRO_CORE_CLK_FREQ_403_MHZ 403 + #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x) #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x) From patchwork Fri Sep 1 11:42:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 13372442 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1380CA0FEA for ; Fri, 1 Sep 2023 11:43:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349201AbjIALnF (ORCPT ); Fri, 1 Sep 2023 07:43:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348449AbjIALnD (ORCPT ); Fri, 1 Sep 2023 07:43:03 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C8EEE70; Fri, 1 Sep 2023 04:43:00 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 381AIxf2009705; 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Fri, 1 Sep 2023 11:42:51 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3sqafmj04e-1; Fri, 01 Sep 2023 11:42:51 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 381BgpDC013971; Fri, 1 Sep 2023 11:42:51 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 381Bgpks013970; Fri, 01 Sep 2023 11:42:51 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id D08335006A6; Fri, 1 Sep 2023 17:12:50 +0530 (+0530) From: Nitin Rawat To: mani@kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, jejb@linux.ibm.com, martin.petersen@oracle.com Cc: quic_cang@quicinc.com, quic_nguyenb@quicinc.com, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Nitin Rawat , Naveen Kumar Goud Arepalli Subject: [PATCH V6 4/6] scsi: ufs: qcom: Align unipro clk attributes configuration as per HPG Date: Fri, 1 Sep 2023 17:12:40 +0530 Message-Id: <20230901114242.31219-5-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230901114242.31219-1-quic_nitirawa@quicinc.com> References: <20230901114242.31219-1-quic_nitirawa@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 6yG7vwjlPUywsbpmvPitHWAq6XqjhCft X-Proofpoint-ORIG-GUID: 6yG7vwjlPUywsbpmvPitHWAq6XqjhCft X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-01_09,2023-08-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=902 bulkscore=0 clxscore=1015 phishscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309010109 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently CORE_CLK_1US_CYCLES, PA_VS_CORE_CLK_40NS_CYCLES are configured in clk scaling post change ops. Move this to clk scaling pre change ops to align completely with hardware specification. This doesn't bring any functionality change. Co-developed-by: Naveen Kumar Goud Arepalli Signed-off-by: Naveen Kumar Goud Arepalli Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index e3648e936498..d670fcc27ffb 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1410,12 +1410,6 @@ static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, } static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) -{ - /* nothing to do as of now */ - return 0; -} - -static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); @@ -1425,6 +1419,11 @@ static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) return ufs_qcom_set_core_clk_ctrl(hba, true); } +static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) +{ + return 0; +} + static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); From patchwork Fri Sep 1 11:42:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nitin Rawat X-Patchwork-Id: 13372445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43FF1CA0FE8 for ; Fri, 1 Sep 2023 11:43:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349227AbjIALnN (ORCPT ); Fri, 1 Sep 2023 07:43:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349218AbjIALnL (ORCPT ); Fri, 1 Sep 2023 07:43:11 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB4F010E5; Fri, 1 Sep 2023 04:43:04 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 381Af5b5015046; Fri, 1 Sep 2023 11:42:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=zOm8nndxYACZ2nRUgyy3rFPtQ/tGgW11wwbgkBluXvc=; b=dXVcdEAzgfqz33w/ZRNUTX9XFb8cUtaVXsTmcAnkDDaVp4XsP7J9p5p+hQoV5a/IaDKf cImrWrctEx98xmf2sNSHnRD3/Y55IsMRweLmJf/pTOnPAjZ9lqS9fPhMSk/jxEgVZAkc BLRcUDBSawpqiYIU6UrrUPRoLOafjTJB4DfCucSorREYEs5+bt+wHDRR2k9pNkRvVT6q J790emrJTNYf3gy7XlZJAjIp59sqGNngr2+3fopZUolPLVF7asXfpoLpKpBKkhoIVEDm eE5uEqTZpPXTwYfnE63iQfpT1tD6DKzJwL9QH9r6jj0rKjJEYJ+DLJLGhvPu0u5xKZtc xA== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3suc22gghf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 01 Sep 2023 11:42:56 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 381Bgm9J013931; Fri, 1 Sep 2023 11:42:52 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3sqafmj04r-1; Fri, 01 Sep 2023 11:42:52 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 381BgqOm013988; Fri, 1 Sep 2023 11:42:52 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 381Bgq9C013986; Fri, 01 Sep 2023 11:42:52 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id C34275006A6; Fri, 1 Sep 2023 17:12:51 +0530 (+0530) From: Nitin Rawat To: mani@kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, jejb@linux.ibm.com, martin.petersen@oracle.com Cc: quic_cang@quicinc.com, quic_nguyenb@quicinc.com, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Nitin Rawat , Naveen Kumar Goud Arepalli Subject: [PATCH V6 5/6] scsi: ufs: qcom: Refactor ufs_qcom_cfg_timers function. Date: Fri, 1 Sep 2023 17:12:41 +0530 Message-Id: <20230901114242.31219-6-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230901114242.31219-1-quic_nitirawa@quicinc.com> References: <20230901114242.31219-1-quic_nitirawa@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: y8rWzAKBEOJlzRnRJDTkpT5iEoUroKFq X-Proofpoint-ORIG-GUID: y8rWzAKBEOJlzRnRJDTkpT5iEoUroKFq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-01_09,2023-08-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 clxscore=1015 mlxscore=0 impostorscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309010109 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org a)Configure SYS1CLK_1US_REG for clock scaleup pre ops. b)Move ufs_qcom_cfg_timers from clk scaling post change ops to clk scaling pre change ops to align with the HPG. c)Introduce a new argument is_pre_scale_up for ufs_qcom_cfg_timers to configure sys_1us timer for max freq as per HPG. Co-developed-by: Naveen Kumar Goud Arepalli Signed-off-by: Naveen Kumar Goud Arepalli Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 63 +++++++++++++++++++++++++++---------- 1 file changed, 46 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index d670fcc27ffb..c251c98a74f0 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -532,7 +532,8 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, * Return: zero for success and non-zero in case of a failure. */ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, - u32 hs, u32 rate, bool update_link_startup_timer) + u32 hs, u32 rate, bool link_startup, + bool is_pre_scale_up) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); struct ufs_clk_info *clki; @@ -563,11 +564,16 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, /* * The Qunipro controller does not use following registers: * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG & - * UFS_REG_PA_LINK_STARTUP_TIMER - * But UTP controller uses SYS1CLK_1US_REG register for Interrupt - * Aggregation logic. - */ - if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba)) + * UFS_REG_PA_LINK_STARTUP_TIMER. + * However UTP controller uses SYS1CLK_1US_REG register for Interrupt + * Aggregation logic and Auto hibern8 logic. + * It is mandatory to write SYS1CLK_1US_REG register on UFS host + * controller V4.0.0 onwards. + */ + if (ufs_qcom_cap_qunipro(host) && + !(ufshcd_is_intr_aggr_allowed(hba) || + ufshcd_is_auto_hibern8_supported(hba) || + host->hw_ver.major >= 4)) return 0; if (gear == 0) { @@ -576,8 +582,14 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, } list_for_each_entry(clki, &hba->clk_list_head, list) { - if (!strcmp(clki->name, "core_clk")) - core_clk_rate = clk_get_rate(clki->clk); + if (!strcmp(clki->name, "core_clk")) { + if (is_pre_scale_up) + core_clk_rate = clki->max_freq; + else + core_clk_rate = clk_get_rate(clki->clk); + break; + } + } /* If frequency is smaller than 1MHz, set to 1MHz */ @@ -657,7 +669,7 @@ static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, mb(); } - if (update_link_startup_timer && host->hw_ver.major != 0x5) { + if (link_startup && host->hw_ver.major != 0x5) { ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100), REG_UFS_CFG0); /* @@ -679,7 +691,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, switch (status) { case PRE_CHANGE: if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE, - 0, true)) { + 0, true, false)) { dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); return -EINVAL; @@ -927,7 +939,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, case POST_CHANGE: if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, dev_req_params->pwr_rx, - dev_req_params->hs_rate, false)) { + dev_req_params->hs_rate, false, false)) { dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", __func__); /* @@ -1412,10 +1424,22 @@ static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct ufs_pa_layer_attr *attr = &host->dev_req_params; + int ret; if (!ufs_qcom_cap_qunipro(host)) return 0; + if (attr) { + ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, + attr->pwr_rx, attr->hs_rate, + false, true); + if (ret) { + dev_err(hba->dev, "%s ufs cfg timer failed\n", + __func__); + return ret; + } + } return ufs_qcom_set_core_clk_ctrl(hba, true); } @@ -1452,10 +1476,21 @@ static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); + struct ufs_pa_layer_attr *attr = &host->dev_req_params; + int ret; if (!ufs_qcom_cap_qunipro(host)) return 0; + if (attr) { + ret = ufs_qcom_cfg_timers(hba, attr->gear_rx, attr->pwr_rx, + attr->hs_rate, false, false); + if (ret) { + dev_err(hba->dev, "%s ufs cfg timer failed\n", + __func__); + return ret; + } + } return ufs_qcom_set_core_clk_ctrl(hba, false); } @@ -1463,7 +1498,6 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, bool scale_up, enum ufs_notify_change_status status) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params; int err = 0; /* check the host controller state before sending hibern8 cmd */ @@ -1493,11 +1527,6 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, return err; } - ufs_qcom_cfg_timers(hba, - dev_req_params->gear_rx, - dev_req_params->pwr_rx, - dev_req_params->hs_rate, - false); ufs_qcom_icc_update_bw(host); ufshcd_uic_hibern8_exit(hba); } From patchwork Fri Sep 1 11:42:42 2023 Content-Type: text/plain; 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Fri, 1 Sep 2023 11:43:26 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3sqafmj06y-1; Fri, 01 Sep 2023 11:43:26 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 381Bgmwu013924; Fri, 1 Sep 2023 11:43:25 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 381BhPL2014533; Fri, 01 Sep 2023 11:43:25 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id E56585006A6; Fri, 1 Sep 2023 17:13:24 +0530 (+0530) From: Nitin Rawat To: mani@kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, jejb@linux.ibm.com, martin.petersen@oracle.com Cc: quic_cang@quicinc.com, quic_nguyenb@quicinc.com, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Nitin Rawat , Naveen Kumar Goud Arepalli Subject: [PATCH V6 6/6] scsi: ufs: qcom: Configure clk HW division based on scaling conditions. Date: Fri, 1 Sep 2023 17:12:42 +0530 Message-Id: <20230901114242.31219-7-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230901114242.31219-1-quic_nitirawa@quicinc.com> References: <20230901114242.31219-1-quic_nitirawa@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: SYlh6frL2Vg0_uSm6skisQ5416HpPVID X-Proofpoint-GUID: SYlh6frL2Vg0_uSm6skisQ5416HpPVID X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-01_09,2023-08-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 impostorscore=0 suspectscore=0 adultscore=0 mlxlogscore=965 clxscore=1015 malwarescore=0 phishscore=0 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309010109 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org a) Enable internal HW division of unipro core_clk for scale up condition. b) Clear internal HW division of unipro core_clk for scale down condition. Co-developed-by: Naveen Kumar Goud Arepalli Signed-off-by: Naveen Kumar Goud Arepalli Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 31 +++++++++++++++++-------------- drivers/ufs/host/ufs-qcom.h | 2 +- 2 files changed, 18 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index c251c98a74f0..2ddda9356abc 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1389,18 +1389,21 @@ static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, core_clk_ctrl_reg |= FIELD_PREP(CLK_1US_CYCLES_MASK, cycles_in_1us); } - /* Clear CORE_CLK_DIV_EN */ - core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; + /* Enable CORE_CLK_DIV_EN for scale up condition */ + if (is_max_freq) + core_clk_ctrl_reg |= CORE_CLK_DIV_EN_BIT; ret = ufshcd_dme_set(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), core_clk_ctrl_reg); + if (ret) + return ret; /* * UFS host controller V4.0.0 onwards needs to program * PA_VS_CORE_CLK_40NS_CYCLES attribute per programmed * frequency of unipro core clk of UFS host controller. */ - if (!ret && (host->hw_ver.major >= 4)) { + if (host->hw_ver.major >= 4) { if (cycles_in_40ns > PA_VS_CORE_CLK_40NS_CYCLES_MASK) return -EINVAL; @@ -1451,26 +1454,26 @@ static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) { struct ufs_qcom_host *host = ufshcd_get_variant(hba); - int err; - u32 core_clk_ctrl_reg; + int ret; + u32 reg; if (!ufs_qcom_cap_qunipro(host)) return 0; - err = ufshcd_dme_get(hba, + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), - &core_clk_ctrl_reg); + ®); + if (ret) + return ret; /* make sure CORE_CLK_DIV_EN is cleared */ - if (!err && - (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { - core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; - err = ufshcd_dme_set(hba, + if (reg & CORE_CLK_DIV_EN_BIT) { + reg &= ~CORE_CLK_DIV_EN_BIT; + ret = ufshcd_dme_set(hba, UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), - core_clk_ctrl_reg); + reg); } - - return err; + return ret; } static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index bc176ef58e3e..bf0c370c79c7 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -141,7 +141,7 @@ enum { /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */ #define CLK_1US_CYCLES_MASK_V4 GENMASK(27, 16) #define CLK_1US_CYCLES_MASK GENMASK(7, 0) -#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8) +#define CORE_CLK_DIV_EN_BIT BIT(8) #define PA_VS_CORE_CLK_40NS_CYCLES 0x9007 #define PA_VS_CORE_CLK_40NS_CYCLES_MASK GENMASK(6, 0)