From patchwork Mon Sep 4 05:05:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linu Cherian X-Patchwork-Id: 13373473 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46754CA0FE3 for ; Mon, 4 Sep 2023 05:07:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wHc4bsjpAKzHYZMuY6LxAHgEv7g8qryxqvMxj0tQqms=; b=UnZK1UKNTlNJqR 4mSUG6vg+yShL6oPJvmD4mH6sEpx0gIGrLLifVtV0QU3Z9/QegMO+LI8UVf/cH39yURUQk5Jt6u70 s/E9eDiCv09bigrVz8my7z4fDJXoSl6rYT03jD5eAMB0EHmUC1L6rQluLWMnsv7/2NDL0HvzwcLOh aKa0bQ3K65KKP6hdvugg+5TdrGLlt1T82BpEWNXxXmi/0rhMNmEAGdWycZ6lEKmx2j6xPi3NMMP1A EJ/DXZ0i1DS77MRJqHqezbmSm5ZuY1yo2NTCBNSYjV+8vO7y+k7kkYm6YrWR08UO0Nrus+GaQwqFe Ly7TdOJHiMigdCJSsEnQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qd1nK-003KmF-0v; Mon, 04 Sep 2023 05:06:38 +0000 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174] helo=mx0b-0016f401.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qd1nE-003KlL-0k for linux-arm-kernel@lists.infradead.org; Mon, 04 Sep 2023 05:06:34 +0000 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 383KqLeD003842; Sun, 3 Sep 2023 22:06:16 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Elk1dRG/E2B2F9ZUpa+arA9I4Rkj60fotSKdV2l7deM=; b=dimGgfpAN+elWEJtk/kzlTXXeFijMukOx7YsmsZX6hsCdi2wG+O+16Fg93blVne3pN/c 4EvPY6l81GxNbfG3GPkorL/B3UW2MYcwmLmbifHBXpAunJ5yFC9p+Zr2LfpXr686jovv haEpd3AVrjwGYPw1QxyDHPlMpsW+ZS3UrvYeiZN1y4ZBJ852jM4i8mNHFhs4dD0hAPo+ Ew1X4Aywb1f9t0nmcqFtXjnzi8xczTyEtMnhkLOw8sYisJ7eWTzXVBNxfJlsR7GOHvx1 wW5WD7UVn2oDhmehC6/PndU2XUy2VsuSd15F1dMPLxlxsNCd+PgulKG7985i2Ncr/aq9 yQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sv2dp4hqu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 03 Sep 2023 22:06:16 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Sun, 3 Sep 2023 22:06:14 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Sun, 3 Sep 2023 22:06:14 -0700 Received: from localhost.localdomain (unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id B96013F706B; Sun, 3 Sep 2023 22:06:10 -0700 (PDT) From: Linu Cherian To: , , , CC: , , , , , , , , , Linu Cherian Subject: [RFC PATCH v3 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property Date: Mon, 4 Sep 2023 10:35:41 +0530 Message-ID: <20230904050548.28047-2-lcherian@marvell.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230904050548.28047-1-lcherian@marvell.com> References: <20230904050548.28047-1-lcherian@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: _EXjN5OSKf4NQKZ-Fz8loGHdgUkmDWMA X-Proofpoint-GUID: _EXjN5OSKf4NQKZ-Fz8loGHdgUkmDWMA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-04_02,2023-08-31_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230903_220632_279106_0D5C66F0 X-CRM114-Status: GOOD ( 14.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org memory-region 0: Reserved trace buffer memory TMC ETR: When available, use this reserved memory region for trace data capture. Same region is used for trace data retention after a panic or watchdog reset. TMC ETF: When available, use this reserved memory region for trace data retention synced from internal SRAM after a panic or watchdog reset. memory-region 1: Reserved meta data memory TMC ETR, ETF: When available, use this memory for register snapshot retention synced from hardware registers after a panic or watchdog reset. Signed-off-by: Linu Cherian --- .../devicetree/bindings/arm/arm,coresight-tmc.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml index cb8dceaca70e..dce54978554a 100644 --- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml +++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml @@ -101,6 +101,17 @@ properties: and ETF configurations. $ref: /schemas/graph.yaml#/properties/port + memory-region: + items: + - description: Reserved trace buffer memory for ETR and ETF sinks. + For ETR, this reserved memory region is used for trace data capture. + Same region is used for trace data retention as well after a panic + or watchdog reset. + For ETF, this reserved memory region is used for retention of trace + data synced from internal SRAM after a panic or watchdog reset. + + - description: Reserved meta data memory. Used for ETR and ETF sinks. + required: - compatible - reg @@ -115,6 +126,8 @@ examples: etr@20070000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x20070000 0x1000>; + memory-region = <&etr_trace_mem_reserved>, + <&etr_mdata_mem_reserved>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; From patchwork Mon Sep 4 05:05:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linu Cherian X-Patchwork-Id: 13373478 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14A06CA0FF6 for ; Mon, 4 Sep 2023 05:07:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xPoUInXIOT471nWsPZp5cX1gZM30wzI55SYsgXm9vUI=; b=dxWzfPetX251E8 nygRFpcH0deCB+XGNeFZws6i4VssEC2Rp8nEGBPvVQicF41Mvyx1C0f7GSl0otJeqpuAu3tfh0ezF 2EF5xbnglgFlL1jqVJ6u0KuVylYO536NYrWDhZo++cdqqlwp3RYekaxboQSXFgJaJ853rG3/AJnYQ Xmhp664MMaFP25W35vlUb9MlfrfEk+7L1q0HYQD+tdqbo9FC/kuE18NcB3eqT9jkfQPa/mYgcDlsx TP8y+ugFgRGfnh/8MapncBx5HLPDeWhb1w2/zx+HT9oFpt97SjeqZppyV8qv5fHt4AaABgeEyb3FG Ve1xjOsCPAg8G5x7EQAw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qd1nI-003Kls-2L; Mon, 04 Sep 2023 05:06:36 +0000 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174] helo=mx0b-0016f401.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qd1nD-003Kks-1M for linux-arm-kernel@lists.infradead.org; Mon, 04 Sep 2023 05:06:33 +0000 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 383KqLeE003842; Sun, 3 Sep 2023 22:06:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=uRgNw2A2sSti8hI3SOhkOY20cdl5J6DkqGnZK9mrSyU=; b=F5ZWoHykau8ZavqXPFVtqSpKgoN9U8mPcKW16p9ci3Y6ne6opK8Xv9MaBMwTn6yK5b1Q pXjVjjQdKeWkz5Q/fZgWXXSRv3N8javM3GvgFk+KOa5shpOjUl+I/IlD0XScKtvyAK3g t+3P5PZWIyN0ZVxSBhnJkBcgIfKldRwauZWJ1lFo0T4WgtIw9HAssQO6ekjc9TXUqiBZ 6hqHIJP/bPjb9cNzxzcgZV+OSn1DMU9KaTK1f1ciHodzm2zvoLMkLTOkvI2OCCy7nZaV VvLWQlaEMEmbvcc+3un3r+5YNrm0U2ityIpMN03n/AD8WCA7Y6B5MRCrDsOqnrFfbyxM ow== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sv2dp4hr1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 03 Sep 2023 22:06:21 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Sun, 3 Sep 2023 22:06:20 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Sun, 3 Sep 2023 22:06:20 -0700 Received: from localhost.localdomain (unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 47A343F708C; Sun, 3 Sep 2023 22:06:15 -0700 (PDT) From: Linu Cherian To: , , , CC: , , , , , , , , , Linu Cherian , Anil Kumar Reddy Subject: [RFC PATCH v3 2/7] coresight: tmc-etr: Add support to use reserved trace memory Date: Mon, 4 Sep 2023 10:35:42 +0530 Message-ID: <20230904050548.28047-3-lcherian@marvell.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230904050548.28047-1-lcherian@marvell.com> References: <20230904050548.28047-1-lcherian@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: MJ4V26WBZg3Y_6p5PccSq1A1G8A06Xtp X-Proofpoint-GUID: MJ4V26WBZg3Y_6p5PccSq1A1G8A06Xtp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-04_02,2023-08-31_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230903_220631_473364_D8C4D701 X-CRM114-Status: GOOD ( 28.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support to use reserved memory for coresight ETR trace buffer. Introduce a new ETR buffer mode called ETR_MODE_RESRV, which becomes available when ETR device tree node is supplied with a valid reserved memory region. ETR_MODE_RESRV can be selected only by explicit user request. $ echo resrv >/sys/bus/coresight/devices/tmc_etr/buf_mode_preferred Signed-off-by: Anil Kumar Reddy Signed-off-by: Linu Cherian --- .../hwtracing/coresight/coresight-tmc-core.c | 39 ++++++++++ .../hwtracing/coresight/coresight-tmc-etr.c | 74 ++++++++++++++++++- drivers/hwtracing/coresight/coresight-tmc.h | 24 ++++++ 3 files changed, 136 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index 7ec5365e2b64..c37dc629408b 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -370,6 +371,42 @@ static inline bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata) return (auth & TMC_AUTH_NSID_MASK) == 0x3; } +static void tmc_get_reserved_region(struct device *parent) +{ + struct tmc_drvdata *drvdata = dev_get_drvdata(parent); + struct device_node *node; + struct resource res; + int rc; + + node = of_parse_phandle(parent->of_node, "memory-region", 0); + if (!node) { + dev_dbg(parent, "No reserved trace buffer specified\n"); + goto out; + } + + rc = of_address_to_resource(node, 0, &res); + of_node_put(node); + if (rc || res.start == 0 || resource_size(&res) == 0) { + dev_err(parent, "Reserved trace buffer memory is invalid\n"); + goto out; + } + + drvdata->resrv_buf.vaddr = memremap(res.start, + resource_size(&res), + MEMREMAP_WB); + if (IS_ERR(drvdata->resrv_buf.vaddr)) { + dev_err(parent, "Reserved trace buffer mapping failed\n"); + rc = PTR_ERR(drvdata->resrv_buf.vaddr); + goto out; + } + + drvdata->resrv_buf.paddr = res.start; + drvdata->resrv_buf.size = resource_size(&res); + +out: + return; +} + /* Detect and initialise the capabilities of a TMC ETR */ static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps) { @@ -482,6 +519,8 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id) drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4; } + tmc_get_reserved_region(dev); + desc.dev = dev; switch (drvdata->config_type) { diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index cd2d85a86b68..334226cd7201 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -30,6 +30,7 @@ struct etr_buf_hw { bool has_iommu; bool has_etr_sg; bool has_catu; + bool has_resrv; }; /* @@ -692,6 +693,61 @@ static const struct etr_buf_operations etr_flat_buf_ops = { .get_data = tmc_etr_get_data_flat_buf, }; +/* + * tmc_etr_alloc_resrv_buf: Allocate a contiguous DMA buffer from reserved region. + */ +static int tmc_etr_alloc_resrv_buf(struct tmc_drvdata *drvdata, + struct etr_buf *etr_buf, int node, + void **pages) +{ + struct etr_flat_buf *resrv_buf; + struct device *real_dev = drvdata->csdev->dev.parent; + + /* We cannot reuse existing pages for resrv buf */ + if (pages) + return -EINVAL; + + resrv_buf = kzalloc(sizeof(*resrv_buf), GFP_KERNEL); + if (!resrv_buf) + return -ENOMEM; + + resrv_buf->daddr = dma_map_resource(real_dev, drvdata->resrv_buf.paddr, + etr_buf->size, DMA_FROM_DEVICE, 0); + if (dma_mapping_error(real_dev, resrv_buf->daddr)) { + dev_err(real_dev, "failed to map source buffer address\n"); + kfree(resrv_buf); + return -ENOMEM; + } + + resrv_buf->vaddr = drvdata->resrv_buf.vaddr; + resrv_buf->size = etr_buf->size; + resrv_buf->dev = &drvdata->csdev->dev; + etr_buf->hwaddr = resrv_buf->daddr; + etr_buf->mode = ETR_MODE_RESRV; + etr_buf->private = resrv_buf; + return 0; +} + +static void tmc_etr_free_resrv_buf(struct etr_buf *etr_buf) +{ + struct etr_flat_buf *resrv_buf = etr_buf->private; + + if (resrv_buf && resrv_buf->daddr) { + struct device *real_dev = resrv_buf->dev->parent; + + dma_unmap_resource(real_dev, resrv_buf->daddr, + resrv_buf->size, DMA_FROM_DEVICE, 0); + } + kfree(resrv_buf); +} + +static const struct etr_buf_operations etr_resrv_buf_ops = { + .alloc = tmc_etr_alloc_resrv_buf, + .free = tmc_etr_free_resrv_buf, + .sync = tmc_etr_sync_flat_buf, + .get_data = tmc_etr_get_data_flat_buf, +}; + /* * tmc_etr_alloc_sg_buf: Allocate an SG buf @etr_buf. Setup the parameters * appropriately. @@ -798,6 +854,7 @@ static const struct etr_buf_operations *etr_buf_ops[] = { [ETR_MODE_FLAT] = &etr_flat_buf_ops, [ETR_MODE_ETR_SG] = &etr_sg_buf_ops, [ETR_MODE_CATU] = NULL, + [ETR_MODE_RESRV] = &etr_resrv_buf_ops }; void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu) @@ -823,6 +880,7 @@ static inline int tmc_etr_mode_alloc_buf(int mode, case ETR_MODE_FLAT: case ETR_MODE_ETR_SG: case ETR_MODE_CATU: + case ETR_MODE_RESRV: if (etr_buf_ops[mode] && etr_buf_ops[mode]->alloc) rc = etr_buf_ops[mode]->alloc(drvdata, etr_buf, node, pages); @@ -841,6 +899,7 @@ static void get_etr_buf_hw(struct device *dev, struct etr_buf_hw *buf_hw) buf_hw->has_iommu = iommu_get_domain_for_dev(dev->parent); buf_hw->has_etr_sg = tmc_etr_has_cap(drvdata, TMC_ETR_SG); buf_hw->has_catu = !!tmc_etr_get_catu_device(drvdata); + buf_hw->has_resrv = is_tmc_reserved_region_valid(dev->parent); } static bool etr_can_use_flat_mode(struct etr_buf_hw *buf_hw, ssize_t etr_buf_size) @@ -872,13 +931,19 @@ static struct etr_buf *tmc_alloc_etr_buf(struct tmc_drvdata *drvdata, if (!etr_buf) return ERR_PTR(-ENOMEM); - etr_buf->size = size; + /* Overiride the buffer size here for reserved mode */ + etr_buf->size = (drvdata->etr_mode == ETR_MODE_RESRV) ? + drvdata->resrv_buf.size : size; /* If there is user directive for buffer mode, try that first */ if (drvdata->etr_mode != ETR_MODE_AUTO) rc = tmc_etr_mode_alloc_buf(drvdata->etr_mode, drvdata, etr_buf, node, pages); + /* Fallback mechanism is not valid for reserved mode */ + if (rc && (drvdata->etr_mode == ETR_MODE_RESRV)) + goto done; + /* * If we have to use an existing list of pages, we cannot reliably * use a contiguous DMA memory (even if we have an IOMMU). Otherwise, @@ -900,6 +965,7 @@ static struct etr_buf *tmc_alloc_etr_buf(struct tmc_drvdata *drvdata, if (rc && buf_hw.has_catu) rc = tmc_etr_mode_alloc_buf(ETR_MODE_CATU, drvdata, etr_buf, node, pages); +done: if (rc) { kfree(etr_buf); return ERR_PTR(rc); @@ -1827,6 +1893,7 @@ static const char *const buf_modes_str[] = { [ETR_MODE_FLAT] = "flat", [ETR_MODE_ETR_SG] = "tmc-sg", [ETR_MODE_CATU] = "catu", + [ETR_MODE_RESRV] = "resrv", [ETR_MODE_AUTO] = "auto", }; @@ -1845,6 +1912,9 @@ static ssize_t buf_modes_available_show(struct device *dev, if (buf_hw.has_catu) size += sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_CATU]); + if (buf_hw.has_resrv) + size += sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_RESRV]); + size += sysfs_emit_at(buf, size, "\n"); return size; } @@ -1872,6 +1942,8 @@ static ssize_t buf_mode_preferred_store(struct device *dev, drvdata->etr_mode = ETR_MODE_ETR_SG; else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_CATU]) && buf_hw.has_catu) drvdata->etr_mode = ETR_MODE_CATU; + else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_RESRV]) && buf_hw.has_resrv) + drvdata->etr_mode = ETR_MODE_RESRV; else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_AUTO])) drvdata->etr_mode = ETR_MODE_AUTO; else diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index e59d423a9749..942fcd960586 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -135,6 +135,7 @@ enum etr_mode { ETR_MODE_FLAT, /* Uses contiguous flat buffer */ ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */ ETR_MODE_CATU, /* Use SG mechanism in CATU */ + ETR_MODE_RESRV, /* Use reserved region contiguous buffer */ ETR_MODE_AUTO, /* Use the default mechanism */ }; @@ -164,6 +165,17 @@ struct etr_buf { void *private; }; +/** + * @paddr : Start address of reserved memory region. + * @vaddr : Corresponding CPU virtual address. + * @size : Size of reserved memory region. + */ +struct tmc_resrv_buf { + phys_addr_t paddr; + void *vaddr; + size_t size; +}; + /** * struct tmc_drvdata - specifics associated to an TMC component * @base: memory mapped base address for this component. @@ -188,6 +200,7 @@ struct etr_buf { * @idr_mutex: Access serialisation for idr. * @sysfs_buf: SYSFS buffer for ETR. * @perf_buf: PERF buffer for ETR. + * @resrv_buf: Reserved Memory for trace data buffer. Used by ETR/ETF. */ struct tmc_drvdata { void __iomem *base; @@ -213,6 +226,7 @@ struct tmc_drvdata { struct mutex idr_mutex; struct etr_buf *sysfs_buf; struct etr_buf *perf_buf; + struct tmc_resrv_buf resrv_buf; }; struct etr_buf_operations { @@ -330,6 +344,16 @@ tmc_sg_table_buf_size(struct tmc_sg_table *sg_table) return sg_table->data_pages.nr_pages << PAGE_SHIFT; } +static inline bool is_tmc_reserved_region_valid(struct device *dev) +{ + struct tmc_drvdata *drvdata = dev_get_drvdata(dev); + + if (drvdata->resrv_buf.paddr && + drvdata->resrv_buf.size) + return true; + return false; +} + struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata); void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu); From patchwork Mon Sep 4 05:05:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linu Cherian X-Patchwork-Id: 13373475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2CC9C83F33 for ; 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Sun, 03 Sep 2023 22:06:26 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Sun, 3 Sep 2023 22:06:24 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Sun, 3 Sep 2023 22:06:24 -0700 Received: from localhost.localdomain (unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 13E203F7062; Sun, 3 Sep 2023 22:06:19 -0700 (PDT) From: Linu Cherian To: , , , CC: , , , , , , , , , Linu Cherian Subject: [RFC PATCH v3 3/7] coresight: core: Add provision for panic callbacks Date: Mon, 4 Sep 2023 10:35:43 +0530 Message-ID: <20230904050548.28047-4-lcherian@marvell.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230904050548.28047-1-lcherian@marvell.com> References: <20230904050548.28047-1-lcherian@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: KjlDWI-iRg6_PHu3z-O9R_bu0MWUlHMa X-Proofpoint-ORIG-GUID: KjlDWI-iRg6_PHu3z-O9R_bu0MWUlHMa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-04_02,2023-08-31_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230903_220642_467354_2EFF8A0E X-CRM114-Status: GOOD ( 21.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Panic callback handlers allows coresight device drivers to sync relevant trace data and trace metadata to reserved memory regions so that they can be retrieved later in the subsequent boot or in the crashdump kernel. Signed-off-by: Linu Cherian --- drivers/hwtracing/coresight/coresight-core.c | 32 ++++++++++++++++++++ include/linux/coresight.h | 12 ++++++++ 2 files changed, 44 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index 118fcf27854d..de4e3947c8e5 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "coresight-etm-perf.h" #include "coresight-priv.h" @@ -1800,6 +1801,31 @@ struct bus_type coresight_bustype = { .name = "coresight", }; +static int coresight_panic_sync(struct device *dev, void *data) +{ + + struct coresight_device *csdev = container_of(dev, struct coresight_device, dev); + + /* Run through panic sync handlers for all enabled devices */ + if (csdev->enable && panic_ops(csdev)) + panic_ops(csdev)->sync(csdev); + + return 0; +} + +static int coresight_panic_cb(struct notifier_block *self, + unsigned long v, void *p) +{ + bus_for_each_dev(&coresight_bustype, NULL, NULL, + coresight_panic_sync); + + return 0; +} + +static struct notifier_block coresight_notifier = { + .notifier_call = coresight_panic_cb, +}; + static int __init coresight_init(void) { int ret; @@ -1812,6 +1838,10 @@ static int __init coresight_init(void) if (ret) goto exit_bus_unregister; + /* Register function to be called for panic */ + ret = atomic_notifier_chain_register(&panic_notifier_list, + &coresight_notifier); + /* initialise the coresight syscfg API */ ret = cscfg_init(); if (!ret) @@ -1826,6 +1856,8 @@ static int __init coresight_init(void) static void __exit coresight_exit(void) { cscfg_exit(); + atomic_notifier_chain_unregister(&panic_notifier_list, + &coresight_notifier); etm_perf_exit(); bus_unregister(&coresight_bustype); } diff --git a/include/linux/coresight.h b/include/linux/coresight.h index bf70987240e4..09978ea6abe1 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -299,6 +299,7 @@ enum cs_mode { #define link_ops(csdev) csdev->ops->link_ops #define helper_ops(csdev) csdev->ops->helper_ops #define ect_ops(csdev) csdev->ops->ect_ops +#define panic_ops(csdev) csdev->ops->panic_ops /** * struct coresight_ops_sink - basic operations for a sink @@ -368,11 +369,22 @@ struct coresight_ops_helper { int (*disable)(struct coresight_device *csdev, void *data); }; + +/** + * struct coresight_ops_panic - Generic device ops for panic handing + * + * @sync : Sync the device register state/trace data + */ +struct coresight_ops_panic { + int (*sync)(struct coresight_device *csdev); +}; + struct coresight_ops { const struct coresight_ops_sink *sink_ops; const struct coresight_ops_link *link_ops; const struct coresight_ops_source *source_ops; const struct coresight_ops_helper *helper_ops; + const struct coresight_ops_panic *panic_ops; }; #if IS_ENABLED(CONFIG_CORESIGHT) From patchwork Mon Sep 4 05:05:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linu Cherian X-Patchwork-Id: 13373476 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 710D8C83F3E for ; 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Sun, 03 Sep 2023 22:06:31 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Sun, 3 Sep 2023 22:06:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Sun, 3 Sep 2023 22:06:28 -0700 Received: from localhost.localdomain (unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 93DAF3F7070; Sun, 3 Sep 2023 22:06:24 -0700 (PDT) From: Linu Cherian To: , , , CC: , , , , , , , , , Linu Cherian Subject: [RFC PATCH v3 4/7] coresight: tmc: Enable panic sync handling Date: Mon, 4 Sep 2023 10:35:44 +0530 Message-ID: <20230904050548.28047-5-lcherian@marvell.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230904050548.28047-1-lcherian@marvell.com> References: <20230904050548.28047-1-lcherian@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: psMgese3u7WKmVqDnFfoFmk5Qdtlifd5 X-Proofpoint-GUID: psMgese3u7WKmVqDnFfoFmk5Qdtlifd5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-04_02,2023-08-31_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230903_220640_531121_AAEC76E5 X-CRM114-Status: GOOD ( 24.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org - Get reserved region from device tree node for metadata - Define metadata format for TMC - Add TMC ETR panic sync handler that syncs register snapshot to metadata region - Add TMC ETF panic sync handler that syncs register snapshot to metadata region and internal SRAM to reserved trace buffer region. Signed-off-by: Linu Cherian --- .../hwtracing/coresight/coresight-tmc-core.c | 26 +++++++++ .../hwtracing/coresight/coresight-tmc-etf.c | 56 +++++++++++++++++++ .../hwtracing/coresight/coresight-tmc-etr.c | 52 +++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 19 ++++++- 4 files changed, 152 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index c37dc629408b..d69da50136ec 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -403,6 +403,32 @@ static void tmc_get_reserved_region(struct device *parent) drvdata->resrv_buf.paddr = res.start; drvdata->resrv_buf.size = resource_size(&res); + /* Metadata region */ + node = of_parse_phandle(parent->of_node, "memory-region", 1); + if (!node) { + dev_dbg(parent, "No metadata memory-region specified\n"); + goto out; + } + + rc = of_address_to_resource(node, 0, &res); + of_node_put(node); + if (rc || res.start == 0 || resource_size(&res) == 0) { + dev_err(parent, "Metadata memory is invalid\n"); + goto out; + } + + drvdata->metadata.vaddr = memremap(res.start, + resource_size(&res), + MEMREMAP_WB); + if (IS_ERR(drvdata->metadata.vaddr)) { + dev_err(parent, "Metadata memory mapping failed\n"); + rc = PTR_ERR(drvdata->metadata.vaddr); + goto out; + } + + drvdata->metadata.paddr = res.start; + drvdata->metadata.size = resource_size(&res); + out: return; } diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 79d8c64eac49..1dfaa3ccfff7 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -588,6 +588,57 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev, return to_read; } +static int tmc_panic_sync_etf(struct coresight_device *csdev) +{ + u32 val; + struct tmc_register_snapshot *tmc; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct csdev_access *csa = &drvdata->csdev->access; + + /* Make sure we have valid reserved memory */ + if (!drvdata->metadata.vaddr || !drvdata->resrv_buf.vaddr) + return 0; + + tmc = (struct tmc_register_snapshot *)drvdata->metadata.vaddr; + tmc->valid = 0x0; + + CS_UNLOCK(drvdata->base); + + /* Proceed only if ETF is enabled or configured as sink */ + val = readl(drvdata->base + TMC_CTL); + if (!(val & TMC_CTL_CAPT_EN)) + goto out; + + val = readl(drvdata->base + TMC_MODE); + if (val != TMC_MODE_CIRCULAR_BUFFER) + goto out; + + tmc_flush_and_stop(drvdata); + + /* Sync registers from hardware to metadata region */ + tmc->sts = csdev_access_relaxed_read32(csa, TMC_STS); + tmc->trc_paddr = drvdata->resrv_buf.paddr; + + /* Sync Internal SRAM to reserved trace buffer region */ + tmc_etb_dump_hw(drvdata); + memcpy(drvdata->resrv_buf.vaddr, drvdata->buf, drvdata->len); + tmc->size = drvdata->len; + + /* + * Make sure all previous writes are completed, + * before we mark valid + */ + dsb(sy); + tmc->valid = 0x1; + + tmc_disable_hw(drvdata); + + dev_info(&csdev->dev, "%s: success\n", __func__); +out: + CS_UNLOCK(drvdata->base); + return 0; +} + static const struct coresight_ops_sink tmc_etf_sink_ops = { .enable = tmc_enable_etf_sink, .disable = tmc_disable_etf_sink, @@ -601,6 +652,10 @@ static const struct coresight_ops_link tmc_etf_link_ops = { .disable = tmc_disable_etf_link, }; +static const struct coresight_ops_panic tmc_etf_sync_ops = { + .sync = tmc_panic_sync_etf, +}; + const struct coresight_ops tmc_etb_cs_ops = { .sink_ops = &tmc_etf_sink_ops, }; @@ -608,6 +663,7 @@ const struct coresight_ops tmc_etb_cs_ops = { const struct coresight_ops tmc_etf_cs_ops = { .sink_ops = &tmc_etf_sink_ops, .link_ops = &tmc_etf_link_ops, + .panic_ops = &tmc_etf_sync_ops, }; int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 334226cd7201..1983a6772775 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1803,6 +1803,53 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev) return 0; } +static int tmc_panic_sync_etr(struct coresight_device *csdev) +{ + u32 val; + struct tmc_register_snapshot *tmc; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + struct csdev_access *csa = &drvdata->csdev->access; + + /* Being in RESRV mode implies valid reserved memory as well */ + if (drvdata->etr_mode != ETR_MODE_RESRV) + return 0; + + tmc = (struct tmc_register_snapshot *)drvdata->metadata.vaddr; + tmc->valid = 0x0; + + CS_UNLOCK(drvdata->base); + + /* Proceed only if ETR is enabled */ + val = readl(drvdata->base + TMC_CTL); + if (!(val & TMC_CTL_CAPT_EN)) + goto out; + + tmc_flush_and_stop(drvdata); + + /* Sync registers from hardware to metadata region */ + tmc->size = csdev_access_relaxed_read32(csa, TMC_RSZ); + tmc->sts = csdev_access_relaxed_read32(csa, TMC_RSZ); + tmc->rrp = tmc_read_rrp(drvdata); + tmc->rwp = tmc_read_rwp(drvdata); + tmc->dba = tmc_read_dba(drvdata); + tmc->trc_paddr = drvdata->resrv_buf.paddr; + + /* + * Make sure all previous writes are completed, + * before we mark valid + */ + dsb(sy); + tmc->valid = 0x1; + + tmc_disable_hw(drvdata); + + dev_info(&csdev->dev, "%s: success\n", __func__); +out: + CS_UNLOCK(drvdata->base); + + return 0; +} + static const struct coresight_ops_sink tmc_etr_sink_ops = { .enable = tmc_enable_etr_sink, .disable = tmc_disable_etr_sink, @@ -1811,8 +1858,13 @@ static const struct coresight_ops_sink tmc_etr_sink_ops = { .free_buffer = tmc_free_etr_buffer, }; +static const struct coresight_ops_panic tmc_etr_sync_ops = { + .sync = tmc_panic_sync_etr, +}; + const struct coresight_ops tmc_etr_cs_ops = { .sink_ops = &tmc_etr_sink_ops, + .panic_ops = &tmc_etr_sync_ops, }; int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 942fcd960586..af93d3ce0e78 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -131,6 +131,19 @@ enum tmc_mem_intf_width { #define CORESIGHT_SOC_600_ETR_CAPS \ (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE) +/* TMC metadata region for ETR and ETF configurations */ +struct tmc_register_snapshot { + uint32_t valid; /* Indicate if this ETF/ETR was enabled */ + uint32_t size; /* Size of trace data */ + uint32_t sts; /* Status register */ + uint32_t reserved32[3]; + uint64_t rrp; /* Read pointer */ + uint64_t rwp; /* Write pointer */ + uint64_t dba; /* Data buffer address */ + uint64_t trc_paddr; /* Phys address of trace buffer */ + uint64_t reserved64[3]; +}; + enum etr_mode { ETR_MODE_FLAT, /* Uses contiguous flat buffer */ ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */ @@ -201,6 +214,7 @@ struct tmc_resrv_buf { * @sysfs_buf: SYSFS buffer for ETR. * @perf_buf: PERF buffer for ETR. * @resrv_buf: Reserved Memory for trace data buffer. Used by ETR/ETF. + * @metadata: Reserved memory for metadata. Used by ETR/ETF. */ struct tmc_drvdata { void __iomem *base; @@ -227,6 +241,7 @@ struct tmc_drvdata { struct etr_buf *sysfs_buf; struct etr_buf *perf_buf; struct tmc_resrv_buf resrv_buf; + struct tmc_resrv_buf metadata; }; struct etr_buf_operations { @@ -349,7 +364,9 @@ static inline bool is_tmc_reserved_region_valid(struct device *dev) struct tmc_drvdata *drvdata = dev_get_drvdata(dev); if (drvdata->resrv_buf.paddr && - drvdata->resrv_buf.size) + drvdata->resrv_buf.size && + drvdata->metadata.paddr && + drvdata->metadata.size) return true; return false; } From patchwork Mon Sep 4 05:05:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linu Cherian X-Patchwork-Id: 13373477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E46E6CA0FF3 for ; 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Sun, 03 Sep 2023 22:06:35 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Sun, 3 Sep 2023 22:06:33 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Sun, 3 Sep 2023 22:06:33 -0700 Received: from localhost.localdomain (unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 1EB883F7062; Sun, 3 Sep 2023 22:06:28 -0700 (PDT) From: Linu Cherian To: , , , CC: , , , , , , , , , Linu Cherian , Anil Kumar Reddy , Tanmay Jagdale Subject: [RFC PATCH v3 5/7] coresight: tmc: Add support for reading tracedata from previous boot Date: Mon, 4 Sep 2023 10:35:45 +0530 Message-ID: <20230904050548.28047-6-lcherian@marvell.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230904050548.28047-1-lcherian@marvell.com> References: <20230904050548.28047-1-lcherian@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 38hY_PgcRncz7bI137P3SZJzKptJS2kU X-Proofpoint-GUID: 38hY_PgcRncz7bI137P3SZJzKptJS2kU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-04_02,2023-08-31_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230903_220644_211256_8D60ECF5 X-CRM114-Status: GOOD ( 28.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org * Introduce a new mode CS_MODE_READ_PREVBOOT for reading tracedata captured in previous boot. * Add special handlers for preparing ETR/ETF for this special mode * User can read the trace data as below For example, for reading trace data from tmc_etf sink 1. cd /sys/bus/coresight/devices/tmc_etfXX/ 2. Change mode to READ_PREVBOOT #echo 1 > read_prevboot 3. Dump trace buffer data to a file, #dd if=/dev/tmc_etrXX of=~/cstrace.bin 4. Reset back to normal mode #echo 0 > read_prevboot Signed-off-by: Anil Kumar Reddy Signed-off-by: Tanmay Jagdale Signed-off-by: Linu Cherian --- .../coresight/coresight-etm4x-core.c | 1 + .../hwtracing/coresight/coresight-tmc-core.c | 81 +++++++++- .../hwtracing/coresight/coresight-tmc-etf.c | 62 ++++++++ .../hwtracing/coresight/coresight-tmc-etr.c | 140 +++++++++++++++++- drivers/hwtracing/coresight/coresight-tmc.h | 6 + include/linux/coresight.h | 13 ++ 6 files changed, 301 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 7e307022303a..7c65d152aebb 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1001,6 +1001,7 @@ static void etm4_disable(struct coresight_device *csdev, switch (mode) { case CS_MODE_DISABLED: + case CS_MODE_READ_PREVBOOT: break; case CS_MODE_SYSFS: etm4_disable_sysfs(csdev); diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c index d69da50136ec..76dde0292b92 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -103,6 +103,45 @@ u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata) return mask; } +int tmc_read_prepare_prevboot(struct tmc_drvdata *drvdata) +{ + int ret = 0; + struct tmc_register_snapshot *reg_ptr; + struct coresight_device *csdev = drvdata->csdev; + + if (!drvdata->metadata.vaddr) { + ret = -ENOMEM; + goto out; + } + + reg_ptr = drvdata->metadata.vaddr; + if (!reg_ptr->valid) { + dev_err(&drvdata->csdev->dev, + "Invalid metadata captured from previous boot\n"); + ret = -EINVAL; + goto out; + } + + /* Sink specific prevboot mode preparation */ + ret = prevboot_ops(csdev)->prepare(csdev); + if (ret) + goto out; + + if (reg_ptr->sts & 0x1) + coresight_insert_barrier_packet(drvdata->buf); + +out: + return ret; +} + +int tmc_read_unprepare_prevboot(struct tmc_drvdata *drvdata) +{ + struct coresight_device *csdev = drvdata->csdev; + + /* Sink specific prevboot mode preparation */ + return prevboot_ops(csdev)->unprepare(csdev); +} + static int tmc_read_prepare(struct tmc_drvdata *drvdata) { int ret = 0; @@ -153,6 +192,10 @@ static int tmc_open(struct inode *inode, struct file *file) struct tmc_drvdata *drvdata = container_of(file->private_data, struct tmc_drvdata, miscdev); + /* Advertise if we are opening with a special mode */ + if (drvdata->mode == CS_MODE_READ_PREVBOOT) + dev_dbg(&drvdata->csdev->dev, "TMC read mode for previous boot\n"); + ret = tmc_read_prepare(drvdata); if (ret) return ret; @@ -331,9 +374,44 @@ static ssize_t buffer_size_store(struct device *dev, static DEVICE_ATTR_RW(buffer_size); +static ssize_t read_prevboot_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); + + return sprintf(buf, "%#x\n", (drvdata->mode == CS_MODE_READ_PREVBOOT)); +} + +static ssize_t read_prevboot_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret; + unsigned long val, flags; + struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent); + + ret = kstrtoul(buf, 0, &val); + if (ret) + return ret; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + if (val && (drvdata->mode == CS_MODE_DISABLED)) + drvdata->mode = CS_MODE_READ_PREVBOOT; + else if (!val && (drvdata->mode == CS_MODE_READ_PREVBOOT)) + drvdata->mode = CS_MODE_DISABLED; + + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + return size; +} + +static DEVICE_ATTR_RW(read_prevboot); + static struct attribute *coresight_tmc_attrs[] = { &dev_attr_trigger_cntr.attr, &dev_attr_buffer_size.attr, + &dev_attr_read_prevboot.attr, NULL, }; @@ -623,7 +701,8 @@ static void tmc_shutdown(struct amba_device *adev) spin_lock_irqsave(&drvdata->spinlock, flags); - if (drvdata->mode == CS_MODE_DISABLED) + if (drvdata->mode == CS_MODE_DISABLED || + drvdata->mode == CS_MODE_READ_PREVBOOT) goto out; if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 1dfaa3ccfff7..fd883e579141 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -639,6 +639,45 @@ static int tmc_panic_sync_etf(struct coresight_device *csdev) return 0; } +static int tmc_etb_setup_prevboot_buf(struct tmc_drvdata *drvdata) +{ + struct tmc_register_snapshot *reg_ptr; + + reg_ptr = drvdata->metadata.vaddr; + + drvdata->buf = memremap(reg_ptr->trc_paddr, reg_ptr->size, + MEMREMAP_WB); + if (IS_ERR(drvdata->buf)) + return -ENOMEM; + drvdata->len = reg_ptr->size; + return 0; +} + +static void tmc_etb_free_prevboot_buf(struct tmc_drvdata *drvdata) +{ + void *buf = drvdata->buf; + + if (!buf) + return; + memunmap(buf); + drvdata->buf = NULL; +} + +static int tmc_etb_prepare_prevboot(struct coresight_device *csdev) +{ + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + return tmc_etb_setup_prevboot_buf(drvdata); +} + +static int tmc_etb_unprepare_prevboot(struct coresight_device *csdev) +{ + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + tmc_etb_free_prevboot_buf(drvdata); + return 0; +} + static const struct coresight_ops_sink tmc_etf_sink_ops = { .enable = tmc_enable_etf_sink, .disable = tmc_disable_etf_sink, @@ -656,6 +695,11 @@ static const struct coresight_ops_panic tmc_etf_sync_ops = { .sync = tmc_panic_sync_etf, }; +static const struct coresight_ops_prevboot tmc_etf_prevboot_ops = { + .prepare = tmc_etb_prepare_prevboot, + .unprepare = tmc_etb_unprepare_prevboot, +}; + const struct coresight_ops tmc_etb_cs_ops = { .sink_ops = &tmc_etf_sink_ops, }; @@ -664,6 +708,7 @@ const struct coresight_ops tmc_etf_cs_ops = { .sink_ops = &tmc_etf_sink_ops, .link_ops = &tmc_etf_link_ops, .panic_ops = &tmc_etf_sync_ops, + .prevboot_ops = &tmc_etf_prevboot_ops, }; int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) @@ -684,6 +729,14 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) goto out; } + if (drvdata->mode == CS_MODE_READ_PREVBOOT) { + ret = tmc_read_prepare_prevboot(drvdata); + if (ret) + goto out; + else + goto mode_valid; + } + /* Don't interfere if operated from Perf */ if (drvdata->mode == CS_MODE_PERF) { ret = -EINVAL; @@ -707,6 +760,7 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata) __tmc_etb_disable_hw(drvdata); } +mode_valid: drvdata->reading = true; out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -726,8 +780,16 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata) drvdata->config_type != TMC_CONFIG_TYPE_ETF)) return -EINVAL; + spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->mode == CS_MODE_READ_PREVBOOT) { + tmc_read_unprepare_prevboot(drvdata); + drvdata->reading = false; + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return 0; + } + /* Re-enable the TMC if need be */ if (drvdata->mode == CS_MODE_SYSFS) { /* There is no point in reading a TMC in HW FIFO mode */ diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 1983a6772775..7fe5d70a393a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1151,7 +1151,12 @@ ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, { s64 offset; ssize_t actual = len; - struct etr_buf *etr_buf = drvdata->sysfs_buf; + struct etr_buf *etr_buf; + + if (drvdata->mode == CS_MODE_READ_PREVBOOT) + etr_buf = drvdata->prevboot_buf; + else + etr_buf = drvdata->sysfs_buf; if (pos + actual > etr_buf->len) actual = etr_buf->len - pos; @@ -1850,6 +1855,116 @@ static int tmc_panic_sync_etr(struct coresight_device *csdev) return 0; } +static int tmc_etr_setup_prevboot_buf(struct tmc_drvdata *drvdata) +{ + int rc = 0; + u64 trace_addr; + struct etr_buf *etr_buf; + struct etr_flat_buf *resrv_buf; + struct tmc_register_snapshot *reg_ptr; + + etr_buf = kzalloc(sizeof(*etr_buf), GFP_KERNEL); + if (!etr_buf) { + rc = -ENOMEM; + goto out; + } + etr_buf->size = drvdata->resrv_buf.size; + + resrv_buf = kzalloc(sizeof(*resrv_buf), GFP_KERNEL); + if (!resrv_buf) { + rc = -ENOMEM; + goto rmem_err; + } + + reg_ptr = drvdata->metadata.vaddr; + trace_addr = reg_ptr->trc_paddr; + + resrv_buf->vaddr = memremap(trace_addr, reg_ptr->size * 4, + MEMREMAP_WB); + if (IS_ERR(drvdata->buf)) { + rc = -ENOMEM; + goto map_err; + } + resrv_buf->size = etr_buf->size; + resrv_buf->dev = &drvdata->csdev->dev; + etr_buf->hwaddr = trace_addr; + etr_buf->mode = ETR_MODE_RESRV; + etr_buf->private = resrv_buf; + etr_buf->ops = etr_buf_ops[ETR_MODE_RESRV]; + + drvdata->prevboot_buf = etr_buf; + + return 0; + +map_err: + kfree(resrv_buf); + +rmem_err: + kfree(etr_buf); + +out: + return rc; +} + +static int tmc_etr_sync_prevboot_buf(struct tmc_drvdata *drvdata) +{ + u32 status; + u64 rrp, rwp, dba; + struct tmc_register_snapshot *reg_ptr; + struct etr_buf *etr_buf = drvdata->prevboot_buf; + + reg_ptr = drvdata->metadata.vaddr; + + rrp = reg_ptr->rrp; + rwp = reg_ptr->rwp; + dba = reg_ptr->dba; + status = reg_ptr->sts; + + etr_buf->full = !!(status & TMC_STS_FULL); + + /* Sync the buffer pointers */ + etr_buf->offset = rrp - dba; + if (etr_buf->full) + etr_buf->len = etr_buf->size; + else + etr_buf->len = rwp - rrp; + + return 0; +} + +static void tmc_etr_free_prevboot_buf(struct tmc_drvdata *drvdata) +{ + void *buf = drvdata->prevboot_buf; + + if (!buf) + return; + + memunmap(buf); + drvdata->prevboot_buf = NULL; +} + +static int tmc_etr_prepare_prevboot(struct coresight_device *csdev) +{ + int ret = 0; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + ret = tmc_etr_setup_prevboot_buf(drvdata); + if (ret) + goto out; + tmc_etr_sync_prevboot_buf(drvdata); + +out: + return ret; +} + +static int tmc_etr_unprepare_prevboot(struct coresight_device *csdev) +{ + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + tmc_etr_free_prevboot_buf(drvdata); + return 0; +} + static const struct coresight_ops_sink tmc_etr_sink_ops = { .enable = tmc_enable_etr_sink, .disable = tmc_disable_etr_sink, @@ -1862,9 +1977,15 @@ static const struct coresight_ops_panic tmc_etr_sync_ops = { .sync = tmc_panic_sync_etr, }; +static const struct coresight_ops_prevboot tmc_etr_prevboot_ops = { + .prepare = tmc_etr_prepare_prevboot, + .unprepare = tmc_etr_unprepare_prevboot, +}; + const struct coresight_ops tmc_etr_cs_ops = { .sink_ops = &tmc_etr_sink_ops, .panic_ops = &tmc_etr_sync_ops, + .prevboot_ops = &tmc_etr_prevboot_ops, }; int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) @@ -1876,12 +1997,21 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETR)) return -EINVAL; + spin_lock_irqsave(&drvdata->spinlock, flags); if (drvdata->reading) { ret = -EBUSY; goto out; } + if (drvdata->mode == CS_MODE_READ_PREVBOOT) { + ret = tmc_read_prepare_prevboot(drvdata); + if (ret) + goto out; + else + goto mode_valid; + } + /* * We can safely allow reads even if the ETR is operating in PERF mode, * since the sysfs session is captured in mode specific data. @@ -1896,6 +2026,7 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) if (drvdata->mode == CS_MODE_SYSFS) __tmc_etr_disable_hw(drvdata); +mode_valid: drvdata->reading = true; out: spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -1914,6 +2045,13 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata) spin_lock_irqsave(&drvdata->spinlock, flags); + if (drvdata->mode == CS_MODE_READ_PREVBOOT) { + tmc_read_unprepare_prevboot(drvdata); + drvdata->reading = false; + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return 0; + } + /* RE-enable the TMC if need be */ if (drvdata->mode == CS_MODE_SYSFS) { /* diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index af93d3ce0e78..a95ba0a8ed93 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -213,6 +213,9 @@ struct tmc_resrv_buf { * @idr_mutex: Access serialisation for idr. * @sysfs_buf: SYSFS buffer for ETR. * @perf_buf: PERF buffer for ETR. + * @prevboot_buf: Previous boot buffer for ETR. This is a special purpose + * buffer that is used only for mapping the trace buffer from + * previous boot and not for capturing trace. * @resrv_buf: Reserved Memory for trace data buffer. Used by ETR/ETF. * @metadata: Reserved memory for metadata. Used by ETR/ETF. */ @@ -240,6 +243,7 @@ struct tmc_drvdata { struct mutex idr_mutex; struct etr_buf *sysfs_buf; struct etr_buf *perf_buf; + struct etr_buf *prevboot_buf; struct tmc_resrv_buf resrv_buf; struct tmc_resrv_buf metadata; }; @@ -291,6 +295,8 @@ void tmc_flush_and_stop(struct tmc_drvdata *drvdata); void tmc_enable_hw(struct tmc_drvdata *drvdata); void tmc_disable_hw(struct tmc_drvdata *drvdata); u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata); +int tmc_read_prepare_prevboot(struct tmc_drvdata *drvdata); +int tmc_read_unprepare_prevboot(struct tmc_drvdata *drvdata); /* ETB/ETF functions */ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata); diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 09978ea6abe1..699a433261c9 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -292,6 +292,7 @@ enum cs_mode { CS_MODE_DISABLED, CS_MODE_SYSFS, CS_MODE_PERF, + CS_MODE_READ_PREVBOOT, /* Trace data from previous boot */ }; #define source_ops(csdev) csdev->ops->source_ops @@ -300,6 +301,7 @@ enum cs_mode { #define helper_ops(csdev) csdev->ops->helper_ops #define ect_ops(csdev) csdev->ops->ect_ops #define panic_ops(csdev) csdev->ops->panic_ops +#define prevboot_ops(csdev) csdev->ops->prevboot_ops /** * struct coresight_ops_sink - basic operations for a sink @@ -379,12 +381,23 @@ struct coresight_ops_panic { int (*sync)(struct coresight_device *csdev); }; +/** + * struct coresight_ops_prevboot - Generic device ops for prevboot mode + * + * @prepare : Preparation for prevboot mode + */ +struct coresight_ops_prevboot { + int (*prepare)(struct coresight_device *csdev); + int (*unprepare)(struct coresight_device *csdev); +}; + struct coresight_ops { const struct coresight_ops_sink *sink_ops; const struct coresight_ops_link *link_ops; const struct coresight_ops_source *source_ops; const struct coresight_ops_helper *helper_ops; const struct coresight_ops_panic *panic_ops; + const struct coresight_ops_prevboot *prevboot_ops; }; #if IS_ENABLED(CONFIG_CORESIGHT) From patchwork Mon Sep 4 05:05:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linu Cherian X-Patchwork-Id: 13373474 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5535C83F2C for ; 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Sun, 03 Sep 2023 22:06:40 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Sun, 3 Sep 2023 22:06:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Sun, 3 Sep 2023 22:06:38 -0700 Received: from localhost.localdomain (unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 2270C3F7070; Sun, 3 Sep 2023 22:06:33 -0700 (PDT) From: Linu Cherian To: , , , CC: , , , , , , , , , Linu Cherian Subject: [RFC PATCH v3 6/7] coresight: tmc: Stop trace capture on FlIn Date: Mon, 4 Sep 2023 10:35:46 +0530 Message-ID: <20230904050548.28047-7-lcherian@marvell.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230904050548.28047-1-lcherian@marvell.com> References: <20230904050548.28047-1-lcherian@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Nc_ZLAFaYfHyj0H4sofZlXvVu5QzCleU X-Proofpoint-ORIG-GUID: Nc_ZLAFaYfHyj0H4sofZlXvVu5QzCleU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-04_02,2023-08-31_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230903_220646_170926_A50963DE X-CRM114-Status: GOOD ( 17.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Configure TMC ETR and ETF to flush and stop trace capture on FlIn event. As a side effect, do manual flush only if auto flush fails. Signed-off-by: Linu Cherian --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 ++++++++-- drivers/hwtracing/coresight/coresight-tmc-etr.c | 10 ++++++++-- drivers/hwtracing/coresight/coresight-tmc.h | 3 +++ 3 files changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index fd883e579141..9b4c208b6dc4 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -34,7 +34,7 @@ static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdata) writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT | - TMC_FFCR_TRIGON_TRIGIN, + TMC_FFCR_TRIGON_TRIGIN | TMC_FFCR_STOP_ON_FLUSH, drvdata->base + TMC_FFCR); writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG); @@ -613,7 +613,13 @@ static int tmc_panic_sync_etf(struct coresight_device *csdev) if (val != TMC_MODE_CIRCULAR_BUFFER) goto out; - tmc_flush_and_stop(drvdata); + val = readl(drvdata->base + TMC_FFSR); + /* Do manual flush and stop only if its not auto-stopped */ + if (!(val & TMC_FFSR_FT_STOPPED)) { + dev_info(&csdev->dev, + "%s: Triggering manual flush\n", __func__); + tmc_flush_and_stop(drvdata); + } /* Sync registers from hardware to metadata region */ tmc->sts = csdev_access_relaxed_read32(csa, TMC_STS); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 7fe5d70a393a..323e503bcfa7 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1098,7 +1098,7 @@ static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT | - TMC_FFCR_TRIGON_TRIGIN, + TMC_FFCR_TRIGON_TRIGIN | TMC_FFCR_STOP_ON_FLUSH, drvdata->base + TMC_FFCR); writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG); tmc_enable_hw(drvdata); @@ -1829,7 +1829,13 @@ static int tmc_panic_sync_etr(struct coresight_device *csdev) if (!(val & TMC_CTL_CAPT_EN)) goto out; - tmc_flush_and_stop(drvdata); + val = readl(drvdata->base + TMC_FFSR); + /* Do manual flush and stop only if its not auto-stopped */ + if (!(val & TMC_FFSR_FT_STOPPED)) { + dev_info(&csdev->dev, + "%s: Triggering manual flush\n", __func__); + tmc_flush_and_stop(drvdata); + } /* Sync registers from hardware to metadata region */ tmc->size = csdev_access_relaxed_read32(csa, TMC_RSZ); diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index a95ba0a8ed93..b08b649f1fd4 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -76,6 +76,9 @@ #define TMC_AXICTL_AXCACHE_OS (0xf << 2) #define TMC_AXICTL_ARCACHE_OS (0xf << 16) +/* TMC_FFSR - 0x300 */ +#define TMC_FFSR_FT_STOPPED BIT(1) + /* TMC_FFCR - 0x304 */ #define TMC_FFCR_FLUSHMAN_BIT 6 #define TMC_FFCR_EN_FMT BIT(0) From patchwork Mon Sep 4 05:05:47 2023 Content-Type: text/plain; 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Sun, 3 Sep 2023 22:06:42 -0700 Received: from localhost.localdomain (unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id A55153F7062; Sun, 3 Sep 2023 22:06:38 -0700 (PDT) From: Linu Cherian To: , , , CC: , , , , , , , , , Linu Cherian Subject: [RFC PATCH v3 7/7] coresight: etm4x: Configure ETM to trigger on panic Date: Mon, 4 Sep 2023 10:35:47 +0530 Message-ID: <20230904050548.28047-8-lcherian@marvell.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230904050548.28047-1-lcherian@marvell.com> References: <20230904050548.28047-1-lcherian@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: QfyJEHZeyVL3BEQykJWrkM8OqEG_W2ia X-Proofpoint-GUID: QfyJEHZeyVL3BEQykJWrkM8OqEG_W2ia X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-04_02,2023-08-31_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230903_220652_866712_23F6915F X-CRM114-Status: GOOD ( 18.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Configure ETM to generate a trigger on Ext out [0] on panic. This is achieved by configuring a single address comparator with the address of "panic" and by configuring Ext out [0] to trigger on the comparator event. This trigger can be used by the sinks to stop capture on panic. Signed-off-by: Linu Cherian --- .../coresight/coresight-etm4x-core.c | 17 +++++++++--- drivers/hwtracing/coresight/coresight-etm4x.h | 26 +++++++++++++++++++ 2 files changed, 40 insertions(+), 3 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 7c65d152aebb..423934efcd9d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -62,6 +62,7 @@ static void etm4_set_default_config(struct etmv4_config *config); static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, struct perf_event *event); static u64 etm4_get_access_type(struct etmv4_config *config); +static u64 etm4_get_comparator_access_type(struct etmv4_config *config); static enum cpuhp_state hp_online; @@ -1291,9 +1292,8 @@ static void etm4_set_victlr_access(struct etmv4_config *config) static void etm4_set_default_config(struct etmv4_config *config) { - /* disable all events tracing */ - config->eventctrl0 = 0x0; - config->eventctrl1 = 0x0; + int rselector = 2; /* 0 and 1 are reserved */ + int comp_idx = 0; /* disable stalling */ config->stall_ctrl = 0x0; @@ -1309,6 +1309,17 @@ static void etm4_set_default_config(struct etmv4_config *config) /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */ etm4_set_victlr_access(config); + + /* Configure the comparator with kernel panic address */ + config->addr_val[comp_idx] = (u64)panic; + config->addr_acc[comp_idx] = etm4_get_comparator_access_type(config); + config->addr_type[comp_idx] = ETM_ADDR_TYPE_STOP; + config->res_ctrl[rselector] = ETM_RESGRP_SADDRCMP << 16 | BIT(comp_idx); + + /* Connect external output [0] with comparator out */ + config->eventctrl0 = 0x0 << 7 | rselector; + + config->eventctrl1 = 0x0; } static u64 etm4_get_ns_access_type(struct etmv4_config *config) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 27c8a9901868..6ac5d5ee1877 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -612,6 +612,32 @@ #define ETM_CNTR_MAX_VAL 0xFFFF #define ETM_TRACEID_MASK 0x3f +/* ETM resource group encoding */ +#define ETM_RESGRP_EXTIN 0x0 +#define ETM_RESGRP_PECMP 0x1 +#define ETM_RESGRP_CNTRSEQ 0x2 +#define ETM_RESGRP_SSCMP 0x3 +#define ETM_RESGRP_SADDRCMP 0x4 +#define ETM_RESGRP_ADDRRANGECMP 0x5 +#define ETM_RESGRP_CIDCMP 0x6 +#define ETM_RESGRP_VCIDCMP 0x7 + +#define ETM_EXTIN_0 0x0 + + +/* ETM resource group encoding */ +#define ETM_RESGRP_EXTIN 0x0 +#define ETM_RESGRP_PECMP 0x1 +#define ETM_RESGRP_CNTRSEQ 0x2 +#define ETM_RESGRP_SSCMP 0x3 +#define ETM_RESGRP_SADDRCMP 0x4 +#define ETM_RESGRP_ADDRRANGECMP 0x5 +#define ETM_RESGRP_CIDCMP 0x6 +#define ETM_RESGRP_VCIDCMP 0x7 + +#define ETM_EXTIN_0 0x0 + + /* ETMv4 programming modes */ #define ETM_MODE_EXCLUDE BIT(0) #define ETM_MODE_LOAD BIT(1)